1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2009 DENX Software Engineering
4 * Author: John Rigby <jrigby@gmail.com>
6 * Based on mx27/generic.c:
7 * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
8 * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
12 #include <clock_legacy.h>
18 #include <asm/global_data.h>
20 #include <asm/arch-imx/cpu.h>
21 #include <asm/arch/imx-regs.h>
22 #include <asm/arch/clock.h>
24 #ifdef CONFIG_FSL_ESDHC_IMX
25 #include <fsl_esdhc_imx.h>
27 DECLARE_GLOBAL_DATA_PTR;
31 * get the system pll clock in Hz
33 * mfi + mfn / (mfd +1)
34 * f = 2 * f_ref * --------------------
37 static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
39 unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
41 int mfn = (pll >> CCM_PLL_MFN_SHIFT)
43 unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
45 unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
48 mfi = mfi <= 5 ? 5 : mfi;
49 mfn = mfn >= 512 ? mfn - 1024 : mfn;
53 return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
57 static ulong imx_get_mpllclk(void)
59 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
60 ulong fref = MXC_HCLK;
62 return imx_decode_pll(readl(&ccm->mpctl), fref);
65 static ulong imx_get_upllclk(void)
67 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
68 ulong fref = MXC_HCLK;
70 return imx_decode_pll(readl(&ccm->upctl), fref);
73 static ulong imx_get_armclk(void)
75 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
76 ulong cctl = readl(&ccm->cctl);
77 ulong fref = imx_get_mpllclk();
80 if (cctl & CCM_CCTL_ARM_SRC)
81 fref = lldiv((u64) fref * 3, 4);
83 div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
84 & CCM_CCTL_ARM_DIV_MASK) + 1;
89 static ulong imx_get_ahbclk(void)
91 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
92 ulong cctl = readl(&ccm->cctl);
93 ulong fref = imx_get_armclk();
96 div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
97 & CCM_CCTL_AHB_DIV_MASK) + 1;
102 static ulong imx_get_ipgclk(void)
104 return imx_get_ahbclk() / 2;
107 static ulong imx_get_perclk(int clk)
109 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
110 ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() :
114 div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
115 div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
120 int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq)
122 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
123 ulong fref = from_upll ? imx_get_upllclk() : imx_get_ahbclk();
124 ulong div = (fref + freq - 1) / freq;
126 if (clk > MXC_UART_CLK || !div || --div > CCM_PERCLK_MASK)
129 clrsetbits_le32(&ccm->pcdr[CCM_PERCLK_REG(clk)],
130 CCM_PERCLK_MASK << CCM_PERCLK_SHIFT(clk),
131 div << CCM_PERCLK_SHIFT(clk));
133 setbits_le32(&ccm->mcr, 1 << clk);
135 clrbits_le32(&ccm->mcr, 1 << clk);
139 unsigned int mxc_get_clock(enum mxc_clock clk)
141 if (clk >= MXC_CLK_NUM)
145 return imx_get_armclk();
147 return imx_get_ahbclk();
151 return imx_get_ipgclk();
153 return imx_get_perclk(clk);
157 u32 get_cpu_rev(void)
160 u32 system_rev = 0x25000;
162 /* read SREV register from IIM module */
163 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
164 srev = readl(&iim->iim_srev);
168 system_rev |= CHIP_REV_1_0;
171 system_rev |= CHIP_REV_1_1;
174 system_rev |= CHIP_REV_1_2;
177 system_rev |= 0x8000;
184 #if defined(CONFIG_DISPLAY_CPUINFO)
185 static char *get_reset_cause(void)
187 /* read RCSR register from CCM module */
188 struct ccm_regs *ccm =
189 (struct ccm_regs *)IMX_CCM_BASE;
191 u32 cause = readl(&ccm->rcsr) & 0x0f;
197 else if ((cause & 2) == 2)
199 else if ((cause & 4) == 4)
201 else if ((cause & 8) == 8)
204 return "unknown reset";
208 int print_cpuinfo(void)
211 u32 cpurev = get_cpu_rev();
213 printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n",
214 (cpurev & 0xF0) >> 4, (cpurev & 0x0F),
215 ((cpurev & 0x8000) ? " unknown" : ""),
216 strmhz(buf, imx_get_armclk()));
217 printf("Reset cause: %s\n", get_reset_cause());
222 #if defined(CONFIG_FEC_MXC)
224 * Initializes on-chip ethernet controllers.
225 * to override, implement board_eth_init()
227 int cpu_eth_init(struct bd_info *bis)
229 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
232 val = readl(&ccm->cgr0);
234 writel(val, &ccm->cgr0);
235 return fecmxc_initialize(bis);
241 #ifdef CONFIG_FSL_ESDHC_IMX
242 #if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
243 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
245 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
251 #ifdef CONFIG_FSL_ESDHC_IMX
253 * Initializes on-chip MMC controllers.
254 * to override, implement board_mmc_init()
256 int cpu_mmc_init(struct bd_info *bis)
258 return fsl_esdhc_mmc_init(bis);
262 #ifdef CONFIG_FEC_MXC
263 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
266 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
267 struct fuse_bank *bank = &iim->bank[0];
268 struct fuse_bank0_regs *fuse =
269 (struct fuse_bank0_regs *)bank->fuse_regs;
271 for (i = 0; i < 6; i++)
272 mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
274 #endif /* CONFIG_FEC_MXC */