2 * (C) Copyright 2009 DENX Software Engineering
3 * Author: John Rigby <jrigby@gmail.com>
5 * Based on mx27/generic.c:
6 * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
7 * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/imx-regs.h>
30 #include <asm/arch/imx25-pinmux.h>
31 #include <asm/arch/clock.h>
33 #include <asm/arch/mxcmmc.h>
36 #ifdef CONFIG_FSL_ESDHC
37 DECLARE_GLOBAL_DATA_PTR;
41 * get the system pll clock in Hz
43 * mfi + mfn / (mfd +1)
44 * f = 2 * f_ref * --------------------
47 static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
49 unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
51 unsigned int mfn = (pll >> CCM_PLL_MFN_SHIFT)
53 unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
55 unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
58 mfi = mfi <= 5 ? 5 : mfi;
60 return lldiv(2 * (u64) f_ref * (mfi * (mfd + 1) + mfn),
61 (mfd + 1) * (pd + 1));
64 static ulong imx_get_mpllclk(void)
66 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
67 ulong fref = MXC_HCLK;
69 return imx_decode_pll(readl(&ccm->mpctl), fref);
72 ulong imx_get_armclk(void)
74 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
75 ulong cctl = readl(&ccm->cctl);
76 ulong fref = imx_get_mpllclk();
79 if (cctl & CCM_CCTL_ARM_SRC)
80 fref = lldiv((fref * 3), 4);
82 div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
83 & CCM_CCTL_ARM_DIV_MASK) + 1;
85 return lldiv(fref, div);
88 ulong imx_get_ahbclk(void)
90 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
91 ulong cctl = readl(&ccm->cctl);
92 ulong fref = imx_get_armclk();
95 div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
96 & CCM_CCTL_AHB_DIV_MASK) + 1;
98 return lldiv(fref, div);
101 ulong imx_get_perclk(int clk)
103 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
104 ulong fref = imx_get_ahbclk();
107 div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
108 div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
110 return lldiv(fref, div);
113 unsigned int mxc_get_clock(enum mxc_clock clk)
115 if (clk >= MXC_CLK_NUM)
119 return imx_get_armclk();
121 return imx_get_ahbclk();
123 return imx_get_perclk(clk);
127 u32 get_cpu_rev(void)
130 u32 system_rev = 0x25000;
132 /* read SREV register from IIM module */
133 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
134 srev = readl(&iim->iim_srev);
138 system_rev |= CHIP_REV_1_0;
141 system_rev |= CHIP_REV_1_1;
144 system_rev |= CHIP_REV_1_2;
147 system_rev |= 0x8000;
154 #if defined(CONFIG_DISPLAY_CPUINFO)
155 static char *get_reset_cause(void)
157 /* read RCSR register from CCM module */
158 struct ccm_regs *ccm =
159 (struct ccm_regs *)IMX_CCM_BASE;
161 u32 cause = readl(&ccm->rcsr) & 0x0f;
167 else if ((cause & 2) == 2)
169 else if ((cause & 4) == 4)
171 else if ((cause & 8) == 8)
174 return "unknown reset";
178 int print_cpuinfo(void)
181 u32 cpurev = get_cpu_rev();
183 printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n",
184 (cpurev & 0xF0) >> 4, (cpurev & 0x0F),
185 ((cpurev & 0x8000) ? " unknown" : ""),
186 strmhz(buf, imx_get_armclk()));
187 printf("Reset cause: %s\n\n", get_reset_cause());
192 void enable_caches(void)
194 #ifndef CONFIG_SYS_DCACHE_OFF
195 /* Enable D-cache. I-cache is already enabled in start.S */
200 int cpu_eth_init(bd_t *bis)
202 #if defined(CONFIG_FEC_MXC)
203 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
206 val = readl(&ccm->cgr0);
208 writel(val, &ccm->cgr0);
209 return fecmxc_initialize(bis);
217 #ifdef CONFIG_FSL_ESDHC
218 gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
224 * Initializes on-chip MMC controllers.
225 * to override, implement board_mmc_init()
227 int cpu_mmc_init(bd_t *bis)
229 #ifdef CONFIG_MXC_MMC
230 return mxc_mmc_init(bis);
236 #ifdef CONFIG_MXC_UART
237 void mx25_uart1_init_pins(void)
239 struct iomuxc_mux_ctl *muxctl;
240 struct iomuxc_pad_ctl *padctl;
245 muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
246 padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
247 muxmode0 = MX25_PIN_MUX_MODE(0);
249 * set up input pins with hysteresis and 100K pull-ups
251 inpadctl = MX25_PIN_PAD_CTL_HYS
252 | MX25_PIN_PAD_CTL_PKE
253 | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PU;
256 * set up output pins with 100K pull-downs
257 * FIXME: need to revisit this
258 * PUE is ignored if PKE is not set
259 * so the right value here is likely
260 * 0x0 for no pull up/down
262 * 0xc0 for 100k pull down
264 outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
268 writel(muxmode0, &muxctl->pad_uart1_rxd);
269 writel(inpadctl, &padctl->pad_uart1_rxd);
272 writel(muxmode0, &muxctl->pad_uart1_txd);
273 writel(outpadctl, &padctl->pad_uart1_txd);
276 writel(muxmode0, &muxctl->pad_uart1_rts);
277 writel(outpadctl, &padctl->pad_uart1_rts);
280 writel(muxmode0, &muxctl->pad_uart1_cts);
281 writel(inpadctl, &padctl->pad_uart1_cts);
283 #endif /* CONFIG_MXC_UART */
285 #ifdef CONFIG_FEC_MXC
286 void mx25_fec_init_pins(void)
288 struct iomuxc_mux_ctl *muxctl;
289 struct iomuxc_pad_ctl *padctl;
295 muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
296 padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
297 muxmode0 = MX25_PIN_MUX_MODE(0);
298 inpadctl_100kpd = MX25_PIN_PAD_CTL_HYS
299 | MX25_PIN_PAD_CTL_PKE
300 | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
301 inpadctl_22kpu = MX25_PIN_PAD_CTL_HYS
302 | MX25_PIN_PAD_CTL_PKE
303 | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_22K_PU;
305 * set up output pins with 100K pull-downs
306 * FIXME: need to revisit this
307 * PUE is ignored if PKE is not set
308 * so the right value here is likely
311 * 0xc0 for 100k pull down
313 outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
316 writel(muxmode0, &muxctl->pad_fec_tx_clk);
317 writel(inpadctl_100kpd, &padctl->pad_fec_tx_clk);
320 writel(muxmode0, &muxctl->pad_fec_rx_dv);
321 writel(inpadctl_100kpd, &padctl->pad_fec_rx_dv);
324 writel(muxmode0, &muxctl->pad_fec_rdata0);
325 writel(inpadctl_100kpd, &padctl->pad_fec_rdata0);
328 writel(muxmode0, &muxctl->pad_fec_tdata0);
329 writel(outpadctl, &padctl->pad_fec_tdata0);
332 writel(muxmode0, &muxctl->pad_fec_tx_en);
333 writel(outpadctl, &padctl->pad_fec_tx_en);
336 writel(muxmode0, &muxctl->pad_fec_mdc);
337 writel(outpadctl, &padctl->pad_fec_mdc);
340 writel(muxmode0, &muxctl->pad_fec_mdio);
341 writel(inpadctl_22kpu, &padctl->pad_fec_mdio);
344 writel(muxmode0, &muxctl->pad_fec_rdata1);
345 writel(inpadctl_100kpd, &padctl->pad_fec_rdata1);
348 writel(muxmode0, &muxctl->pad_fec_tdata1);
349 writel(outpadctl, &padctl->pad_fec_tdata1);
353 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
356 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
357 struct fuse_bank *bank = &iim->bank[0];
358 struct fuse_bank0_regs *fuse =
359 (struct fuse_bank0_regs *)bank->fuse_regs;
361 for (i = 0; i < 6; i++)
362 mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
364 #endif /* CONFIG_FEC_MXC */