1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2009 DENX Software Engineering
4 * Author: John Rigby <jrigby@gmail.com>
6 * Based on mx27/generic.c:
7 * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
8 * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
12 #include <clock_legacy.h>
17 #include <asm/arch-imx/cpu.h>
18 #include <asm/arch/imx-regs.h>
19 #include <asm/arch/clock.h>
21 #ifdef CONFIG_FSL_ESDHC_IMX
22 #include <fsl_esdhc_imx.h>
24 DECLARE_GLOBAL_DATA_PTR;
28 * get the system pll clock in Hz
30 * mfi + mfn / (mfd +1)
31 * f = 2 * f_ref * --------------------
34 static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
36 unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
38 int mfn = (pll >> CCM_PLL_MFN_SHIFT)
40 unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
42 unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
45 mfi = mfi <= 5 ? 5 : mfi;
46 mfn = mfn >= 512 ? mfn - 1024 : mfn;
50 return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
54 static ulong imx_get_mpllclk(void)
56 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
57 ulong fref = MXC_HCLK;
59 return imx_decode_pll(readl(&ccm->mpctl), fref);
62 static ulong imx_get_upllclk(void)
64 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
65 ulong fref = MXC_HCLK;
67 return imx_decode_pll(readl(&ccm->upctl), fref);
70 static ulong imx_get_armclk(void)
72 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
73 ulong cctl = readl(&ccm->cctl);
74 ulong fref = imx_get_mpllclk();
77 if (cctl & CCM_CCTL_ARM_SRC)
78 fref = lldiv((u64) fref * 3, 4);
80 div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
81 & CCM_CCTL_ARM_DIV_MASK) + 1;
86 static ulong imx_get_ahbclk(void)
88 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
89 ulong cctl = readl(&ccm->cctl);
90 ulong fref = imx_get_armclk();
93 div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
94 & CCM_CCTL_AHB_DIV_MASK) + 1;
99 static ulong imx_get_ipgclk(void)
101 return imx_get_ahbclk() / 2;
104 static ulong imx_get_perclk(int clk)
106 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
107 ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() :
111 div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
112 div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
117 int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq)
119 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
120 ulong fref = from_upll ? imx_get_upllclk() : imx_get_ahbclk();
121 ulong div = (fref + freq - 1) / freq;
123 if (clk > MXC_UART_CLK || !div || --div > CCM_PERCLK_MASK)
126 clrsetbits_le32(&ccm->pcdr[CCM_PERCLK_REG(clk)],
127 CCM_PERCLK_MASK << CCM_PERCLK_SHIFT(clk),
128 div << CCM_PERCLK_SHIFT(clk));
130 setbits_le32(&ccm->mcr, 1 << clk);
132 clrbits_le32(&ccm->mcr, 1 << clk);
136 unsigned int mxc_get_clock(enum mxc_clock clk)
138 if (clk >= MXC_CLK_NUM)
142 return imx_get_armclk();
144 return imx_get_ahbclk();
148 return imx_get_ipgclk();
150 return imx_get_perclk(clk);
154 u32 get_cpu_rev(void)
157 u32 system_rev = 0x25000;
159 /* read SREV register from IIM module */
160 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
161 srev = readl(&iim->iim_srev);
165 system_rev |= CHIP_REV_1_0;
168 system_rev |= CHIP_REV_1_1;
171 system_rev |= CHIP_REV_1_2;
174 system_rev |= 0x8000;
181 #if defined(CONFIG_DISPLAY_CPUINFO)
182 static char *get_reset_cause(void)
184 /* read RCSR register from CCM module */
185 struct ccm_regs *ccm =
186 (struct ccm_regs *)IMX_CCM_BASE;
188 u32 cause = readl(&ccm->rcsr) & 0x0f;
194 else if ((cause & 2) == 2)
196 else if ((cause & 4) == 4)
198 else if ((cause & 8) == 8)
201 return "unknown reset";
205 int print_cpuinfo(void)
208 u32 cpurev = get_cpu_rev();
210 printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n",
211 (cpurev & 0xF0) >> 4, (cpurev & 0x0F),
212 ((cpurev & 0x8000) ? " unknown" : ""),
213 strmhz(buf, imx_get_armclk()));
214 printf("Reset cause: %s\n", get_reset_cause());
219 #if defined(CONFIG_FEC_MXC)
221 * Initializes on-chip ethernet controllers.
222 * to override, implement board_eth_init()
224 int cpu_eth_init(bd_t *bis)
226 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
229 val = readl(&ccm->cgr0);
231 writel(val, &ccm->cgr0);
232 return fecmxc_initialize(bis);
238 #ifdef CONFIG_FSL_ESDHC_IMX
239 #if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
240 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
242 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
248 #ifdef CONFIG_FSL_ESDHC_IMX
250 * Initializes on-chip MMC controllers.
251 * to override, implement board_mmc_init()
253 int cpu_mmc_init(bd_t *bis)
255 return fsl_esdhc_mmc_init(bis);
259 #ifdef CONFIG_FEC_MXC
260 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
263 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
264 struct fuse_bank *bank = &iim->bank[0];
265 struct fuse_bank0_regs *fuse =
266 (struct fuse_bank0_regs *)bank->fuse_regs;
268 for (i = 0; i < 6; i++)
269 mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
271 #endif /* CONFIG_FEC_MXC */