3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/cache.h>
12 #include <u-boot/md5.h>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/soc.h>
16 #include <mvebu_mmc.h>
20 void reset_cpu(unsigned long ignored)
22 struct kwcpu_registers *cpureg =
23 (struct kwcpu_registers *)KW_CPU_REG_BASE;
25 writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
26 &cpureg->rstoutn_mask);
27 writel(readl(&cpureg->sys_soft_rst) | 1,
28 &cpureg->sys_soft_rst);
33 * Generates Ramdom hex number reading some time varient system registers
34 * and using md5 algorithm
36 unsigned char get_random_hex(void)
43 * in case of 88F6281/88F6282/88F6192 A0,
44 * Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470
45 * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are
46 * reserved regs and does not have names at this moment
47 * (no errata available)
49 writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478);
50 for (i = 0; i < BUFLEN; i++) {
51 inbuf[i] = readl(KW_REG_UNDOC_0x1470);
53 md5((u8 *) inbuf, (BUFLEN * sizeof(u32)), outbuf);
54 return outbuf[outbuf[7] % 0x0f];
59 * Used with the Base register to set the address window size and location.
60 * Must be programmed from LSB to MSB as sequence of ones followed by
61 * sequence of zeros. The number of ones specifies the size of the window in
62 * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
63 * NOTE: A value of 0x0 specifies 64-KByte size.
65 unsigned int kw_winctrl_calcsize(unsigned int sizeval)
69 u32 val = sizeval >> 1;
71 for (i = 0; val >= 0x10000; i++) {
75 return (0x0000ffff & j);
79 * kw_config_adr_windows - Configure address Windows
81 * There are 8 address windows supported by Kirkwood Soc to addess different
82 * devices. Each window can be configured for size, BAR and remap addr
83 * Below configuration is standard for most of the cases
85 * If remap function not used, remap_lo must be set as base
87 * Reference Documentation:
88 * Mbus-L to Mbus Bridge Registers Configuration.
89 * (Sec 25.1 and 25.3 of Datasheet)
91 int kw_config_adr_windows(void)
93 struct kwwin_registers *winregs =
94 (struct kwwin_registers *)KW_CPU_WIN_BASE;
96 /* Window 0: PCIE MEM address space */
97 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE,
98 KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl);
100 writel(KW_DEFADR_PCI_MEM, &winregs[0].base);
101 writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo);
102 writel(0x0, &winregs[0].remap_hi);
104 /* Window 1: PCIE IO address space */
105 writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE,
106 KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl);
107 writel(KW_DEFADR_PCI_IO, &winregs[1].base);
108 writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo);
109 writel(0x0, &winregs[1].remap_hi);
111 /* Window 2: NAND Flash address space */
112 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
113 KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl);
114 writel(KW_DEFADR_NANDF, &winregs[2].base);
115 writel(KW_DEFADR_NANDF, &winregs[2].remap_lo);
116 writel(0x0, &winregs[2].remap_hi);
118 /* Window 3: SPI Flash address space */
119 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
120 KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl);
121 writel(KW_DEFADR_SPIF, &winregs[3].base);
122 writel(KW_DEFADR_SPIF, &winregs[3].remap_lo);
123 writel(0x0, &winregs[3].remap_hi);
125 /* Window 4: BOOT Memory address space */
126 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
127 KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl);
128 writel(KW_DEFADR_BOOTROM, &winregs[4].base);
130 /* Window 5: Security SRAM address space */
131 writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM,
132 KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl);
133 writel(KW_DEFADR_SASRAM, &winregs[5].base);
135 /* Window 6-7: Disabled */
136 writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl);
137 writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl);
143 * kw_config_mpp - Multi-Purpose Pins Functionality configuration
145 * Each MPP can be configured to different functionality through
146 * MPP control register, ref (sec 6.1 of kirkwood h/w specification)
148 * There are maximum 64 Multi-Pourpose Pins on Kirkwood
149 * Each MPP functionality can be configuration by a 4bit value
150 * of MPP control reg, the value and associated functionality depends
151 * upon used SoC varient
153 int kw_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31,
154 u32 mpp32_39, u32 mpp40_47, u32 mpp48_55)
156 u32 *mppreg = (u32 *) KW_MPP_BASE;
158 /* program mpp registers */
159 writel(mpp0_7, &mppreg[0]);
160 writel(mpp8_15, &mppreg[1]);
161 writel(mpp16_23, &mppreg[2]);
162 writel(mpp24_31, &mppreg[3]);
163 writel(mpp32_39, &mppreg[4]);
164 writel(mpp40_47, &mppreg[5]);
165 writel(mpp48_55, &mppreg[6]);
170 * SYSRSTn Duration Counter Support
172 * Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
173 * When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
174 * The SYSRSTn duration counter is useful for implementing a manufacturer
175 * or factory reset. Upon a long reset assertion that is greater than a
176 * pre-configured environment variable value for sysrstdelay,
177 * The counter value is stored in the SYSRSTn Length Counter Register
178 * The counter is based on the 25-MHz reference clock (40ns)
179 * It is a 29-bit counter, yielding a maximum counting duration of
180 * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
181 * it remains at this value until counter reset is triggered by setting
182 * bit 31 of KW_REG_SYSRST_CNT
184 static void kw_sysrst_action(void)
187 char *s = getenv("sysrstcmd");
190 debug("Error.. %s failed, check sysrstcmd\n",
195 debug("Starting %s process...\n", __FUNCTION__);
196 ret = run_command(s, 0);
198 debug("Error.. %s failed\n", __FUNCTION__);
200 debug("%s process finished\n", __FUNCTION__);
203 static void kw_sysrst_check(void)
205 u32 sysrst_cnt, sysrst_dly;
209 * no action if sysrstdelay environment variable is not defined
211 s = getenv("sysrstdelay");
215 /* read sysrstdelay value */
216 sysrst_dly = (u32) simple_strtoul(s, NULL, 10);
218 /* read SysRst Length counter register (bits 28:0) */
219 sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT));
220 debug("H/w Rst hold time: %d.%d secs\n",
221 sysrst_cnt / SYSRST_CNT_1SEC_VAL,
222 sysrst_cnt % SYSRST_CNT_1SEC_VAL);
224 /* clear the counter for next valid read*/
225 writel(1 << 31, KW_REG_SYSRST_CNT);
229 * if H/w Reset key is pressed and hold for time
230 * more than sysrst_dly in seconds
232 if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly)
236 #if defined(CONFIG_DISPLAY_CPUINFO)
237 int print_cpuinfo(void)
240 u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
241 u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
243 if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
244 printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
263 printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev);
266 #endif /* CONFIG_DISPLAY_CPUINFO */
268 #ifdef CONFIG_ARCH_CPU_INIT
269 int arch_cpu_init(void)
272 struct kwcpu_registers *cpureg =
273 (struct kwcpu_registers *)KW_CPU_REG_BASE;
275 /* Linux expects` the internal registers to be at 0xf1000000 */
276 writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
278 /* Enable and invalidate L2 cache in write through mode */
279 writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
280 invalidate_l2_cache();
282 kw_config_adr_windows();
284 #ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
286 * Configures the I/O voltage of the pads connected to Egigabit
287 * Ethernet interface to 1.8V
288 * By default it is set to 3.3V
290 reg = readl(KW_REG_MPP_OUT_DRV_REG);
292 writel(reg, KW_REG_MPP_OUT_DRV_REG);
294 #ifdef CONFIG_KIRKWOOD_EGIGA_INIT
296 * Set egiga port0/1 in normal functional mode
297 * This is required becasue on kirkwood by default ports are in reset mode
298 * OS egiga driver may not have provision to set them in normal mode
299 * and if u-boot is build without network support, network may fail at OS level
301 reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
302 reg &= ~(1 << 4); /* Clear PortReset Bit */
303 writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
304 reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
305 reg &= ~(1 << 4); /* Clear PortReset Bit */
306 writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
308 #ifdef CONFIG_KIRKWOOD_PCIE_INIT
310 * Enable PCI Express Port0
312 reg = readl(&cpureg->ctrl_stat);
313 reg |= (1 << 0); /* Set PEX0En Bit */
314 writel(reg, &cpureg->ctrl_stat);
318 #endif /* CONFIG_ARCH_CPU_INIT */
321 * SOC specific misc init
323 #if defined(CONFIG_ARCH_MISC_INIT)
324 int arch_misc_init(void)
328 /*CPU streaming & write allocate */
329 temp = readfr_extra_feature_reg();
330 temp &= ~(1 << 28); /* disable wr alloc */
331 writefr_extra_feature_reg(temp);
333 temp = readfr_extra_feature_reg();
334 temp &= ~(1 << 29); /* streaming disabled */
335 writefr_extra_feature_reg(temp);
337 /* L2Cache settings */
338 temp = readfr_extra_feature_reg();
339 /* Disable L2C pre fetch - Set bit 24 */
341 /* enable L2C - Set bit 22 */
343 writefr_extra_feature_reg(temp);
346 /* Change reset vector to address 0x0 */
348 set_cr(temp & ~CR_V);
350 /* checks and execute resset to factory event */
355 #endif /* CONFIG_ARCH_MISC_INIT */
358 int cpu_eth_init(bd_t *bis)
360 mvgbe_initialize(bis);
365 #ifdef CONFIG_MVEBU_MMC
366 int board_mmc_init(bd_t *bis)
371 #endif /* CONFIG_MVEBU_MMC */