3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
27 #include <asm/cache.h>
28 #include <u-boot/md5.h>
29 #include <asm/arch/kirkwood.h>
34 void reset_cpu(unsigned long ignored)
36 struct kwcpu_registers *cpureg =
37 (struct kwcpu_registers *)KW_CPU_REG_BASE;
39 writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
40 &cpureg->rstoutn_mask);
41 writel(readl(&cpureg->sys_soft_rst) | 1,
42 &cpureg->sys_soft_rst);
47 * Generates Ramdom hex number reading some time varient system registers
48 * and using md5 algorithm
50 unsigned char get_random_hex(void)
57 * in case of 88F6281/88F6282/88F6192 A0,
58 * Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470
59 * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are
60 * reserved regs and does not have names at this moment
61 * (no errata available)
63 writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478);
64 for (i = 0; i < BUFLEN; i++) {
65 inbuf[i] = readl(KW_REG_UNDOC_0x1470);
67 md5((u8 *) inbuf, (BUFLEN * sizeof(u32)), outbuf);
68 return outbuf[outbuf[7] % 0x0f];
73 * Used with the Base register to set the address window size and location.
74 * Must be programmed from LSB to MSB as sequence of ones followed by
75 * sequence of zeros. The number of ones specifies the size of the window in
76 * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
77 * NOTE: A value of 0x0 specifies 64-KByte size.
79 unsigned int kw_winctrl_calcsize(unsigned int sizeval)
83 u32 val = sizeval >> 1;
85 for (i = 0; val >= 0x10000; i++) {
89 return (0x0000ffff & j);
93 * kw_config_adr_windows - Configure address Windows
95 * There are 8 address windows supported by Kirkwood Soc to addess different
96 * devices. Each window can be configured for size, BAR and remap addr
97 * Below configuration is standard for most of the cases
99 * If remap function not used, remap_lo must be set as base
101 * Reference Documentation:
102 * Mbus-L to Mbus Bridge Registers Configuration.
103 * (Sec 25.1 and 25.3 of Datasheet)
105 int kw_config_adr_windows(void)
107 struct kwwin_registers *winregs =
108 (struct kwwin_registers *)KW_CPU_WIN_BASE;
110 /* Window 0: PCIE MEM address space */
111 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE,
112 KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl);
114 writel(KW_DEFADR_PCI_MEM, &winregs[0].base);
115 writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo);
116 writel(0x0, &winregs[0].remap_hi);
118 /* Window 1: PCIE IO address space */
119 writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE,
120 KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl);
121 writel(KW_DEFADR_PCI_IO, &winregs[1].base);
122 writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo);
123 writel(0x0, &winregs[1].remap_hi);
125 /* Window 2: NAND Flash address space */
126 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
127 KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl);
128 writel(KW_DEFADR_NANDF, &winregs[2].base);
129 writel(KW_DEFADR_NANDF, &winregs[2].remap_lo);
130 writel(0x0, &winregs[2].remap_hi);
132 /* Window 3: SPI Flash address space */
133 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
134 KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl);
135 writel(KW_DEFADR_SPIF, &winregs[3].base);
136 writel(KW_DEFADR_SPIF, &winregs[3].remap_lo);
137 writel(0x0, &winregs[3].remap_hi);
139 /* Window 4: BOOT Memory address space */
140 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
141 KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl);
142 writel(KW_DEFADR_BOOTROM, &winregs[4].base);
144 /* Window 5: Security SRAM address space */
145 writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM,
146 KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl);
147 writel(KW_DEFADR_SASRAM, &winregs[5].base);
149 /* Window 6-7: Disabled */
150 writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl);
151 writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl);
157 * kw_config_gpio - GPIO configuration
159 void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe)
161 struct kwgpio_registers *gpio0reg =
162 (struct kwgpio_registers *)KW_GPIO0_BASE;
163 struct kwgpio_registers *gpio1reg =
164 (struct kwgpio_registers *)KW_GPIO1_BASE;
166 /* Init GPIOS to default values as per board requirement */
167 writel(gpp0_oe_val, &gpio0reg->dout);
168 writel(gpp1_oe_val, &gpio1reg->dout);
169 writel(gpp0_oe, &gpio0reg->oe);
170 writel(gpp1_oe, &gpio1reg->oe);
174 * kw_config_mpp - Multi-Purpose Pins Functionality configuration
176 * Each MPP can be configured to different functionality through
177 * MPP control register, ref (sec 6.1 of kirkwood h/w specification)
179 * There are maximum 64 Multi-Pourpose Pins on Kirkwood
180 * Each MPP functionality can be configuration by a 4bit value
181 * of MPP control reg, the value and associated functionality depends
182 * upon used SoC varient
184 int kw_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31,
185 u32 mpp32_39, u32 mpp40_47, u32 mpp48_55)
187 u32 *mppreg = (u32 *) KW_MPP_BASE;
189 /* program mpp registers */
190 writel(mpp0_7, &mppreg[0]);
191 writel(mpp8_15, &mppreg[1]);
192 writel(mpp16_23, &mppreg[2]);
193 writel(mpp24_31, &mppreg[3]);
194 writel(mpp32_39, &mppreg[4]);
195 writel(mpp40_47, &mppreg[5]);
196 writel(mpp48_55, &mppreg[6]);
201 * SYSRSTn Duration Counter Support
203 * Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
204 * When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
205 * The SYSRSTn duration counter is useful for implementing a manufacturer
206 * or factory reset. Upon a long reset assertion that is greater than a
207 * pre-configured environment variable value for sysrstdelay,
208 * The counter value is stored in the SYSRSTn Length Counter Register
209 * The counter is based on the 25-MHz reference clock (40ns)
210 * It is a 29-bit counter, yielding a maximum counting duration of
211 * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
212 * it remains at this value until counter reset is triggered by setting
213 * bit 31 of KW_REG_SYSRST_CNT
215 static void kw_sysrst_action(void)
218 char *s = getenv("sysrstcmd");
221 debug("Error.. %s failed, check sysrstcmd\n",
226 debug("Starting %s process...\n", __FUNCTION__);
227 #if !defined(CONFIG_SYS_HUSH_PARSER)
228 ret = run_command (s, 0);
230 ret = parse_string_outer(s, FLAG_PARSE_SEMICOLON
231 | FLAG_EXIT_FROM_LOOP);
234 debug("Error.. %s failed\n", __FUNCTION__);
236 debug("%s process finished\n", __FUNCTION__);
239 static void kw_sysrst_check(void)
241 u32 sysrst_cnt, sysrst_dly;
245 * no action if sysrstdelay environment variable is not defined
247 s = getenv("sysrstdelay");
251 /* read sysrstdelay value */
252 sysrst_dly = (u32) simple_strtoul(s, NULL, 10);
254 /* read SysRst Length counter register (bits 28:0) */
255 sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT));
256 debug("H/w Rst hold time: %d.%d secs\n",
257 sysrst_cnt / SYSRST_CNT_1SEC_VAL,
258 sysrst_cnt % SYSRST_CNT_1SEC_VAL);
260 /* clear the counter for next valid read*/
261 writel(1 << 31, KW_REG_SYSRST_CNT);
265 * if H/w Reset key is pressed and hold for time
266 * more than sysrst_dly in seconds
268 if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly)
272 #if defined(CONFIG_DISPLAY_CPUINFO)
273 int print_cpuinfo(void)
276 u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
277 u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
279 if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
280 printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
299 printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev);
302 #endif /* CONFIG_DISPLAY_CPUINFO */
304 #ifdef CONFIG_ARCH_CPU_INIT
305 int arch_cpu_init(void)
308 struct kwcpu_registers *cpureg =
309 (struct kwcpu_registers *)KW_CPU_REG_BASE;
311 /* Linux expects` the internal registers to be at 0xf1000000 */
312 writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
314 /* Enable and invalidate L2 cache in write through mode */
315 writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
316 invalidate_l2_cache();
318 kw_config_adr_windows();
320 #ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
322 * Configures the I/O voltage of the pads connected to Egigabit
323 * Ethernet interface to 1.8V
324 * By defult it is set to 3.3V
326 reg = readl(KW_REG_MPP_OUT_DRV_REG);
328 writel(reg, KW_REG_MPP_OUT_DRV_REG);
330 #ifdef CONFIG_KIRKWOOD_EGIGA_INIT
332 * Set egiga port0/1 in normal functional mode
333 * This is required becasue on kirkwood by default ports are in reset mode
334 * OS egiga driver may not have provision to set them in normal mode
335 * and if u-boot is build without network support, network may fail at OS level
337 reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
338 reg &= ~(1 << 4); /* Clear PortReset Bit */
339 writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
340 reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
341 reg &= ~(1 << 4); /* Clear PortReset Bit */
342 writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
344 #ifdef CONFIG_KIRKWOOD_PCIE_INIT
346 * Enable PCI Express Port0
348 reg = readl(&cpureg->ctrl_stat);
349 reg |= (1 << 0); /* Set PEX0En Bit */
350 writel(reg, &cpureg->ctrl_stat);
354 #endif /* CONFIG_ARCH_CPU_INIT */
357 * SOC specific misc init
359 #if defined(CONFIG_ARCH_MISC_INIT)
360 int arch_misc_init(void)
364 /*CPU streaming & write allocate */
365 temp = readfr_extra_feature_reg();
366 temp &= ~(1 << 28); /* disable wr alloc */
367 writefr_extra_feature_reg(temp);
369 temp = readfr_extra_feature_reg();
370 temp &= ~(1 << 29); /* streaming disabled */
371 writefr_extra_feature_reg(temp);
373 /* L2Cache settings */
374 temp = readfr_extra_feature_reg();
375 /* Disable L2C pre fetch - Set bit 24 */
377 /* enable L2C - Set bit 22 */
379 writefr_extra_feature_reg(temp);
382 /* Change reset vector to address 0x0 */
384 set_cr(temp & ~CR_V);
386 /* checks and execute resset to factory event */
391 #endif /* CONFIG_ARCH_MISC_INIT */
394 int cpu_eth_init(bd_t *bis)
396 mvgbe_initialize(bis);