2 * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <asm/arch/clock.h>
20 #include <asm/arch/flow.h>
21 #include <asm/arch/tegra.h>
22 #include <asm/arch-tegra/clk_rst.h>
23 #include <asm/arch-tegra/pmc.h>
24 #include <asm/arch-tegra/tegra_i2c.h>
25 #include "../tegra-common/cpu.h"
27 /* Tegra30-specific CPU init code */
28 void tegra_i2c_ll_write_addr(uint addr, uint config)
30 struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
32 writel(addr, ®->cmd_addr0);
33 writel(config, ®->cnfg);
36 void tegra_i2c_ll_write_data(uint data, uint config)
38 struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
40 writel(data, ®->cmd_data1);
41 writel(config, ®->cnfg);
44 #define TPS65911_I2C_ADDR 0x5A
45 #define TPS65911_VDDCTRL_OP_REG 0x28
46 #define TPS65911_VDDCTRL_SR_REG 0x27
47 #define TPS65911_VDDCTRL_OP_DATA (0x2300 | TPS65911_VDDCTRL_OP_REG)
48 #define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
49 #define I2C_SEND_2_BYTES 0x0A02
51 static void enable_cpu_power_rail(void)
53 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
56 debug("enable_cpu_power_rail entry\n");
57 reg = readl(&pmc->pmc_cntrl);
59 writel(reg, &pmc->pmc_cntrl);
62 * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
63 * First set VDD to 1.4V, then enable the VDD regulator.
65 tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2);
66 tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES);
68 tegra_i2c_ll_write_data(TPS65911_VDDCTRL_SR_DATA, I2C_SEND_2_BYTES);
73 * The T30 requires some special clock initialization, including setting up
74 * the dvc i2c, turning on mselect and selecting the G CPU cluster
76 void t30_init_clocks(void)
78 struct clk_rst_ctlr *clkrst =
79 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
80 struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
83 debug("t30_init_clocks entry\n");
84 /* Set active CPU cluster to G */
85 clrbits_le32(flow->cluster_control, 1 << 0);
87 writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
89 val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |
90 (1 << CLK_SYS_RATE_AHB_RATE_SHIFT) |
91 (0 << CLK_SYS_RATE_PCLK_DISABLE_SHIFT) |
92 (0 << CLK_SYS_RATE_APB_RATE_SHIFT);
93 writel(val, &clkrst->crc_clk_sys_rate);
95 /* Put i2c, mselect in reset and enable clocks */
96 reset_set_enable(PERIPH_ID_DVC_I2C, 1);
97 clock_set_enable(PERIPH_ID_DVC_I2C, 1);
98 reset_set_enable(PERIPH_ID_MSELECT, 1);
99 clock_set_enable(PERIPH_ID_MSELECT, 1);
101 /* Switch MSELECT clock to PLLP (00) and use a divisor of 2 */
102 clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 2);
105 * Our high-level clock routines are not available prior to
106 * relocation. We use the low-level functions which require a
107 * hard-coded divisor. Use CLK_M with divide by (n + 1 = 17)
109 clock_ll_set_source_divisor(PERIPH_ID_DVC_I2C, 3, 16);
112 * Give clocks time to stabilize, then take i2c and mselect out of
116 reset_set_enable(PERIPH_ID_DVC_I2C, 0);
117 reset_set_enable(PERIPH_ID_MSELECT, 0);
120 static void set_cpu_running(int run)
122 struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
124 debug("set_cpu_running entry, run = %d\n", run);
125 writel(run ? FLOW_MODE_NONE : FLOW_MODE_STOP, &flow->halt_cpu_events);
128 void start_cpu(u32 reset_vector)
130 debug("start_cpu entry, reset_vector = %x\n", reset_vector);
134 enable_cpu_power_rail();
138 /* Hold the CPUs in reset */
141 /* Disable the CPU clock */
144 /* Enable CoreSight */
145 clock_enable_coresight(1);
148 * Set the entry point for CPU execution from reset,
149 * if it's a non-zero value.
152 writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
154 /* Enable the CPU clock */
157 /* If the CPU doesn't already have power, power it up */
160 /* Take the CPU out of reset */