2 * (C) Copyright 2010-2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/types.h>
25 /* Stabilization delays, in usec */
26 #define PLL_STABILIZATION_DELAY (300)
27 #define IO_STABILIZATION_DELAY (1000)
29 #if defined(CONFIG_TEGRA20)
30 #define NVBL_PLLP_KHZ (216000)
31 #elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
32 #define NVBL_PLLP_KHZ (408000)
34 #error "Unknown Tegra chip!"
37 #define PLLX_ENABLED (1 << 30)
38 #define CCLK_BURST_POLICY 0x20008888
39 #define SUPER_CCLK_DIVIDER 0x80000000
41 /* Calculate clock fractional divider value from ref and target frequencies */
42 #define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2)
44 /* Calculate clock frequency value from reference and clock divider value */
45 #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2))
48 #define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
49 #define PG_UP_TAG_0 0x0
51 #define CORESIGHT_UNLOCK 0xC5ACCE55;
53 #define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
54 #define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
55 #define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0)
56 #define CSITE_CPU_DBG2_LAR (NV_PA_CSITE_BASE + 0x14FB0)
57 #define CSITE_CPU_DBG3_LAR (NV_PA_CSITE_BASE + 0x16FB0)
59 #define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4)
60 #define FLOW_MODE_STOP 2
61 #define HALT_COP_EVENT_JTAG (1 << 28)
62 #define HALT_COP_EVENT_IRQ_1 (1 << 11)
63 #define HALT_COP_EVENT_FIQ_1 (1 << 9)
65 #define FLOW_MODE_NONE 0
67 #define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
69 struct clk_pll_table {
76 void clock_enable_coresight(int enable);
77 void enable_cpu_clock(int enable);
78 void halt_avp(void) __attribute__ ((noreturn));
80 void powerup_cpu(void);
81 void reset_A9_cpu(int reset);
82 void start_cpu(u32 reset_vector);
83 int tegra_get_chip_type(void);
84 void adjust_pllp_out_freqs(void);