2 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <asm/arch/clock.h>
20 #include <asm/arch/gp_padctrl.h>
21 #include <asm/arch/pinmux.h>
22 #include <asm/arch/tegra.h>
23 #include <asm/arch-tegra/clk_rst.h>
24 #include <asm/arch-tegra/pmc.h>
25 #include <asm/arch-tegra/scu.h>
34 enum tegra_family_t get_family(void)
38 reg = readl(NV_PA_APB_MISC_BASE + GP_HIDREV);
42 debug(" tegra_get_family: chip_id = %x\n", chip_id);
44 return TEGRA_FAMILY_T3x;
46 return TEGRA_FAMILY_T2x;
49 int get_num_cpus(void)
51 return get_family() == TEGRA_FAMILY_T3x ? 4 : 2;
55 * Timing tables for each SOC for all four oscillator options.
57 struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
59 {{ 1000, 13, 0, 12}, /* OSC 13M */
60 { 625, 12, 0, 8}, /* OSC 19.2M */
61 { 1000, 12, 0, 12}, /* OSC 12M */
62 { 1000, 26, 0, 12}, /* OSC 26M */
80 void adjust_pllp_out_freqs(void)
82 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
83 struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH];
86 /* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
87 reg = readl(&pll->pll_out[0]); /* OUTA, contains OUT2 / OUT1 */
88 reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR
89 | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR;
90 writel(reg, &pll->pll_out[0]);
92 reg = readl(&pll->pll_out[1]); /* OUTB, contains OUT4 / OUT3 */
93 reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR
94 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR;
95 writel(reg, &pll->pll_out[1]);
98 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
103 /* If PLLX is already enabled, just return */
104 if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
105 debug("pllx_set_rate: PLLX already enabled, returning\n");
109 debug(" pllx_set_rate entry\n");
111 /* Set BYPASS, m, n and p to PLLX_BASE */
112 reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
113 reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
114 writel(reg, &pll->pll_base);
116 /* Set cpcon to PLLX_MISC */
117 reg = (cpcon << PLL_CPCON_SHIFT);
119 /* Set dccon to PLLX_MISC if freq > 600MHz */
121 reg |= (1 << PLL_DCCON_SHIFT);
122 writel(reg, &pll->pll_misc);
125 reg = readl(&pll->pll_base);
126 reg |= PLL_ENABLE_MASK;
129 reg &= ~PLL_BYPASS_MASK;
130 writel(reg, &pll->pll_base);
132 /* Set lock_enable to PLLX_MISC */
133 reg = readl(&pll->pll_misc);
134 reg |= PLL_LOCK_ENABLE_MASK;
135 writel(reg, &pll->pll_misc);
142 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
143 struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
145 enum clock_osc_freq osc;
146 struct clk_pll_table *sel;
148 debug("init_pllx entry\n");
151 chip_type = tegra_get_chip_type();
152 debug(" init_pllx: chip_type = %d\n", chip_type);
155 osc = clock_get_osc_freq();
156 debug(" init_pllx: osc = %d\n", osc);
159 sel = &tegra_pll_x_table[chip_type][osc];
160 pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
162 /* adjust PLLP_out1-4 on T30 */
163 if (chip_type == TEGRA_SOC_T30) {
164 debug(" init_pllx: adjusting PLLP out freqs\n");
165 adjust_pllp_out_freqs();
169 void enable_cpu_clock(int enable)
171 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
176 * Regardless of whether the request is to enable or disable the CPU
177 * clock, every processor in the CPU complex except the master (CPU 0)
178 * will have it's clock stopped because the AVP only talks to the
183 /* Initialize PLLX */
186 /* Wait until all clocks are stable */
187 udelay(PLL_STABILIZATION_DELAY);
189 writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
190 writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
194 * Read the register containing the individual CPU clock enables and
195 * always stop the clocks to CPUs > 0.
197 clk = readl(&clkrst->crc_clk_cpu_cmplx);
198 clk |= 1 << CPU1_CLK_STP_SHIFT;
199 #if defined(CONFIG_TEGRA30)
200 clk |= 1 << CPU2_CLK_STP_SHIFT;
201 clk |= 1 << CPU3_CLK_STP_SHIFT;
203 /* Stop/Unstop the CPU clock */
204 clk &= ~CPU0_CLK_STP_MASK;
205 clk |= !enable << CPU0_CLK_STP_SHIFT;
206 writel(clk, &clkrst->crc_clk_cpu_cmplx);
208 clock_enable(PERIPH_ID_CPU);
211 static int is_cpu_powered(void)
213 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
215 return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
218 static void remove_cpu_io_clamps(void)
220 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
223 /* Remove the clamps on the CPU I/O signals */
224 reg = readl(&pmc->pmc_remove_clamping);
226 writel(reg, &pmc->pmc_remove_clamping);
228 /* Give I/O signals time to stabilize */
229 udelay(IO_STABILIZATION_DELAY);
232 void powerup_cpu(void)
234 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
236 int timeout = IO_STABILIZATION_DELAY;
238 if (!is_cpu_powered()) {
239 /* Toggle the CPU power state (OFF -> ON) */
240 reg = readl(&pmc->pmc_pwrgate_toggle);
243 writel(reg, &pmc->pmc_pwrgate_toggle);
245 /* Wait for the power to come up */
246 while (!is_cpu_powered()) {
248 printf("CPU failed to power up!\n");
254 * Remove the I/O clamps from CPU power partition.
255 * Recommended only on a Warm boot, if the CPU partition gets
256 * power gated. Shouldn't cause any harm when called after a
257 * cold boot according to HW, probably just redundant.
259 remove_cpu_io_clamps();
263 void reset_A9_cpu(int reset)
266 * NOTE: Regardless of whether the request is to hold the CPU in reset
267 * or take it out of reset, every processor in the CPU complex
268 * except the master (CPU 0) will be held in reset because the
269 * AVP only talks to the master. The AVP does not know that there
270 * are multiple processors in the CPU complex.
272 int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
273 int num_cpus = get_num_cpus();
276 debug("reset_a9_cpu entry\n");
277 /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
278 for (cpu = 1; cpu < num_cpus; cpu++)
279 reset_cmplx_set_enable(cpu, mask, 1);
280 reset_cmplx_set_enable(0, mask, reset);
282 /* Enable/Disable master CPU reset */
283 reset_set_enable(PERIPH_ID_CPU, reset);
286 void clock_enable_coresight(int enable)
290 debug("clock_enable_coresight entry\n");
291 clock_set_enable(PERIPH_ID_CORESIGHT, enable);
292 reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
296 * Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by
297 * 1.5, giving an effective frequency of 144MHz.
298 * Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor
299 * (bits 7:0), so 00000001b == 1.5 (n+1 + .5)
301 * Clock divider request for 204MHz would setup CSITE clock as
302 * 144MHz for PLLP base 216MHz and 204MHz for PLLP base 408MHz
304 if (tegra_get_chip_type() == TEGRA_SOC_T30)
305 src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000);
307 src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
308 clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
310 /* Unlock the CPU CoreSight interfaces */
311 rst = CORESIGHT_UNLOCK;
312 writel(rst, CSITE_CPU_DBG0_LAR);
313 writel(rst, CSITE_CPU_DBG1_LAR);
314 #if defined(CONFIG_TEGRA30)
315 writel(rst, CSITE_CPU_DBG2_LAR);
316 writel(rst, CSITE_CPU_DBG3_LAR);
324 writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
325 | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
326 FLOW_CTLR_HALT_COP_EVENTS);