2 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <asm/arch/clock.h>
20 #include <asm/arch/gp_padctrl.h>
21 #include <asm/arch/pinmux.h>
22 #include <asm/arch/tegra.h>
23 #include <asm/arch-tegra/clk_rst.h>
24 #include <asm/arch-tegra/pmc.h>
25 #include <asm/arch-tegra/scu.h>
28 int get_num_cpus(void)
30 struct apb_misc_gp_ctlr *gp;
33 gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
34 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
49 * Timing tables for each SOC for all four oscillator options.
51 struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
55 * Register Field Bits Width
56 * ------------------------------
58 * PLLX_BASE n 17: 8 10
60 * PLLX_MISC cpcon 11: 8 4
63 { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
64 { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
65 { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
66 { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
71 * Register Field Bits Width
72 * ------------------------------
74 * PLLX_BASE n 17: 8 10
76 * PLLX_MISC cpcon 11: 8 4
79 { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
80 { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
81 { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
82 { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
87 * Register Field Bits Width
88 * ------------------------------
90 * PLLX_BASE n 17: 8 10
92 * PLLX_MISC cpcon 11: 8 4
95 { .n = 862, .m = 8, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
96 { .n = 583, .m = 8, .p = 0, .cpcon = 4 }, /* OSC: 19.2 MHz */
97 { .n = 700, .m = 6, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
98 { .n = 700, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
103 * Register Field Bits Width
104 * ------------------------------
105 * PLLX_BASE p 23:20 4
106 * PLLX_BASE n 15: 8 8
110 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
111 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
112 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
113 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
117 void adjust_pllp_out_freqs(void)
119 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
120 struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_PERIPH];
123 /* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
124 reg = readl(&pll->pll_out[0]); /* OUTA, contains OUT2 / OUT1 */
125 reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR
126 | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR;
127 writel(reg, &pll->pll_out[0]);
129 reg = readl(&pll->pll_out[1]); /* OUTB, contains OUT4 / OUT3 */
130 reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR
131 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR;
132 writel(reg, &pll->pll_out[1]);
135 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
140 /* If PLLX is already enabled, just return */
141 if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
142 debug("pllx_set_rate: PLLX already enabled, returning\n");
146 debug(" pllx_set_rate entry\n");
148 /* Set BYPASS, m, n and p to PLLX_BASE */
149 reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT);
150 reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT));
151 writel(reg, &pll->pll_base);
153 /* Set cpcon to PLLX_MISC */
154 reg = (cpcon << PLL_CPCON_SHIFT);
156 /* Set dccon to PLLX_MISC if freq > 600MHz */
158 reg |= (1 << PLL_DCCON_SHIFT);
159 writel(reg, &pll->pll_misc);
162 reg = readl(&pll->pll_base);
163 reg |= PLL_ENABLE_MASK;
166 reg &= ~PLL_BYPASS_MASK;
167 writel(reg, &pll->pll_base);
169 /* Set lock_enable to PLLX_MISC */
170 reg = readl(&pll->pll_misc);
171 reg |= PLL_LOCK_ENABLE_MASK;
172 writel(reg, &pll->pll_misc);
179 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
180 struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
181 int soc_type, sku_info, chip_sku;
182 enum clock_osc_freq osc;
183 struct clk_pll_table *sel;
185 debug("init_pllx entry\n");
187 /* get SOC (chip) type */
188 soc_type = tegra_get_chip();
189 debug(" init_pllx: SoC = 0x%02X\n", soc_type);
192 sku_info = tegra_get_sku_info();
193 debug(" init_pllx: SKU info byte = 0x%02X\n", sku_info);
195 /* get chip SKU, combo of the above info */
196 chip_sku = tegra_get_chip_sku();
197 debug(" init_pllx: Chip SKU = %d\n", chip_sku);
200 osc = clock_get_osc_freq();
201 debug(" init_pllx: osc = %d\n", osc);
204 sel = &tegra_pll_x_table[chip_sku][osc];
205 pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
207 /* adjust PLLP_out1-4 on T3x/T114 */
208 if (soc_type >= CHIPID_TEGRA30) {
209 debug(" init_pllx: adjusting PLLP out freqs\n");
210 adjust_pllp_out_freqs();
214 void enable_cpu_clock(int enable)
216 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
221 * Regardless of whether the request is to enable or disable the CPU
222 * clock, every processor in the CPU complex except the master (CPU 0)
223 * will have it's clock stopped because the AVP only talks to the
228 /* Initialize PLLX */
231 /* Wait until all clocks are stable */
232 udelay(PLL_STABILIZATION_DELAY);
234 writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
235 writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
239 * Read the register containing the individual CPU clock enables and
240 * always stop the clocks to CPUs > 0.
242 clk = readl(&clkrst->crc_clk_cpu_cmplx);
243 clk |= 1 << CPU1_CLK_STP_SHIFT;
244 if (get_num_cpus() == 4)
245 clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
247 /* Stop/Unstop the CPU clock */
248 clk &= ~CPU0_CLK_STP_MASK;
249 clk |= !enable << CPU0_CLK_STP_SHIFT;
250 writel(clk, &clkrst->crc_clk_cpu_cmplx);
252 clock_enable(PERIPH_ID_CPU);
255 static int is_cpu_powered(void)
257 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
259 return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
262 static void remove_cpu_io_clamps(void)
264 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
267 /* Remove the clamps on the CPU I/O signals */
268 reg = readl(&pmc->pmc_remove_clamping);
270 writel(reg, &pmc->pmc_remove_clamping);
272 /* Give I/O signals time to stabilize */
273 udelay(IO_STABILIZATION_DELAY);
276 void powerup_cpu(void)
278 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
280 int timeout = IO_STABILIZATION_DELAY;
282 if (!is_cpu_powered()) {
283 /* Toggle the CPU power state (OFF -> ON) */
284 reg = readl(&pmc->pmc_pwrgate_toggle);
287 writel(reg, &pmc->pmc_pwrgate_toggle);
289 /* Wait for the power to come up */
290 while (!is_cpu_powered()) {
292 printf("CPU failed to power up!\n");
298 * Remove the I/O clamps from CPU power partition.
299 * Recommended only on a Warm boot, if the CPU partition gets
300 * power gated. Shouldn't cause any harm when called after a
301 * cold boot according to HW, probably just redundant.
303 remove_cpu_io_clamps();
307 void reset_A9_cpu(int reset)
310 * NOTE: Regardless of whether the request is to hold the CPU in reset
311 * or take it out of reset, every processor in the CPU complex
312 * except the master (CPU 0) will be held in reset because the
313 * AVP only talks to the master. The AVP does not know that there
314 * are multiple processors in the CPU complex.
316 int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
317 int num_cpus = get_num_cpus();
320 debug("reset_a9_cpu entry\n");
321 /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
322 for (cpu = 1; cpu < num_cpus; cpu++)
323 reset_cmplx_set_enable(cpu, mask, 1);
324 reset_cmplx_set_enable(0, mask, reset);
326 /* Enable/Disable master CPU reset */
327 reset_set_enable(PERIPH_ID_CPU, reset);
330 void clock_enable_coresight(int enable)
335 debug("clock_enable_coresight entry\n");
336 clock_set_enable(PERIPH_ID_CORESIGHT, enable);
337 reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
341 * Put CoreSight on PLLP_OUT0 and divide it down as per
342 * PLLP base frequency based on SoC type (T20/T30/T114).
343 * Clock divider request would setup CSITE clock as 144MHz
344 * for PLLP base 216MHz and 204MHz for PLLP base 408MHz
347 soc_type = tegra_get_chip();
348 if (soc_type == CHIPID_TEGRA30 || soc_type == CHIPID_TEGRA114)
349 src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000);
350 else if (soc_type == CHIPID_TEGRA20)
351 src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
353 printf("%s: Unknown SoC type %X!\n",
356 clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
358 /* Unlock the CPU CoreSight interfaces */
359 rst = CORESIGHT_UNLOCK;
360 writel(rst, CSITE_CPU_DBG0_LAR);
361 writel(rst, CSITE_CPU_DBG1_LAR);
362 if (get_num_cpus() == 4) {
363 writel(rst, CSITE_CPU_DBG2_LAR);
364 writel(rst, CSITE_CPU_DBG3_LAR);
372 writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
373 | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
374 FLOW_CTLR_HALT_COP_EVENTS);