2 * armboot - Startup Code for ARM720 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm-offsets.h>
29 #include <asm/hardware.h>
32 *************************************************************************
34 * Jump vector table as in table 3.1 in [1]
36 *************************************************************************
42 ldr pc, _undefined_instruction
43 ldr pc, _software_interrupt
44 ldr pc, _prefetch_abort
50 #ifdef CONFIG_SPL_BUILD
51 _undefined_instruction: .word _undefined_instruction
52 _software_interrupt: .word _software_interrupt
53 _prefetch_abort: .word _prefetch_abort
54 _data_abort: .word _data_abort
55 _not_used: .word _not_used
58 _pad: .word 0x12345678 /* now 16*4=64 */
60 _undefined_instruction: .word undefined_instruction
61 _software_interrupt: .word software_interrupt
62 _prefetch_abort: .word prefetch_abort
63 _data_abort: .word data_abort
64 _not_used: .word not_used
67 _pad: .word 0x12345678 /* now 16*4=64 */
68 #endif /* CONFIG_SPL_BUILD */
70 .balignl 16,0xdeadbeef
74 *************************************************************************
76 * Startup Code (reset vector)
78 * do important init only if we don't start from RAM!
79 * relocate armboot to ram
81 * jump to second stage
83 *************************************************************************
88 #ifdef CONFIG_SPL_BUILD
89 .word CONFIG_SPL_TEXT_BASE
91 .word CONFIG_SYS_TEXT_BASE
95 * These are defined in the board-specific linker script.
96 * Subtracting _start from them lets the linker put their
97 * relative position in the executable instead of leaving
100 .globl _bss_start_ofs
102 .word __bss_start - _start
106 .word __bss_end__ - _start
112 #ifdef CONFIG_USE_IRQ
113 /* IRQ stack memory (calculated at run-time) */
114 .globl IRQ_STACK_START
118 /* IRQ stack memory (calculated at run-time) */
119 .globl FIQ_STACK_START
124 /* IRQ stack memory (calculated at run-time) + 8 bytes */
125 .globl IRQ_STACK_START_IN
130 * the actual reset code
135 * set the cpu to SVC32 mode
143 * we do sys-critical inits only at reboot,
144 * not when booting from ram!
146 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
150 /* Set stackpointer in internal RAM to call board_init_f */
152 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
153 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
157 /*------------------------------------------------------------------------------*/
160 * void relocate_code (addr_sp, gd, addr_moni)
162 * This "function" does not return, instead it continues in RAM
163 * after relocating the monitor code.
168 mov r4, r0 /* save addr_sp */
169 mov r5, r1 /* save addr of gd */
170 mov r6, r2 /* save addr of destination */
172 /* Set up the stack */
178 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
179 beq clear_bss /* skip relocation */
180 mov r1, r6 /* r1 <- scratch for copy_loop */
181 ldr r3, _bss_start_ofs
182 add r2, r0, r3 /* r2 <- source end address */
185 ldmia r0!, {r9-r10} /* copy from source address [r0] */
186 stmia r1!, {r9-r10} /* copy to target address [r1] */
187 cmp r0, r2 /* until source end address [r2] */
190 #ifndef CONFIG_SPL_BUILD
192 * fix .rel.dyn relocations
194 ldr r0, _TEXT_BASE /* r0 <- Text base */
195 sub r9, r6, r0 /* r9 <- relocation offset */
196 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
197 add r10, r10, r0 /* r10 <- sym table in FLASH */
198 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
199 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
200 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
201 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
203 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
204 add r0, r0, r9 /* r0 <- location to fix up in RAM */
207 cmp r7, #23 /* relative fixup? */
209 cmp r7, #2 /* absolute fixup? */
211 /* ignore unknown type of fixup */
214 /* absolute fix: set location to (offset) symbol value */
215 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
216 add r1, r10, r1 /* r1 <- address of symbol in table */
217 ldr r1, [r1, #4] /* r1 <- symbol value */
218 add r1, r1, r9 /* r1 <- relocated sym addr */
221 /* relative fix: increase location by offset */
226 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
232 #ifndef CONFIG_SPL_BUILD
233 ldr r0, _bss_start_ofs
235 mov r4, r6 /* reloc addr */
238 mov r2, #0x00000000 /* clear */
240 clbss_l:cmp r0, r1 /* clear loop... */
241 bhs clbss_e /* if reached end of bss, exit */
252 * We are done. Do not return, instead branch to second part of board
253 * initialization, now running from RAM.
255 ldr r0, _board_init_r_ofs
259 /* setup parameters for board_init_r */
260 mov r0, r5 /* gd_t */
261 mov r1, r6 /* dest_addr */
266 .word board_init_r - _start
269 .word __rel_dyn_start - _start
271 .word __rel_dyn_end - _start
273 .word __dynsym_start - _start
276 *************************************************************************
278 * CPU_init_critical registers
280 * setup important registers
281 * setup memory timing
283 *************************************************************************
287 #if defined(CONFIG_NETARM)
289 * prior to software reset : need to set pin PORTC4 to be *HRESET
291 ldr r0, =NETARM_GEN_MODULE_BASE
292 ldr r1, =(NETARM_GEN_PORT_MODE(0x10) | \
293 NETARM_GEN_PORT_DIR(0x10))
294 str r1, [r0, #+NETARM_GEN_PORTC]
296 * software reset : see HW Ref. Guide 8.2.4 : Software Service register
297 * for an explanation of this process
299 ldr r0, =NETARM_GEN_MODULE_BASE
300 ldr r1, =NETARM_GEN_SW_SVC_RESETA
301 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
302 ldr r1, =NETARM_GEN_SW_SVC_RESETB
303 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
304 ldr r1, =NETARM_GEN_SW_SVC_RESETA
305 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
306 ldr r1, =NETARM_GEN_SW_SVC_RESETB
307 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
309 * setup PLL and System Config
311 ldr r0, =NETARM_GEN_MODULE_BASE
313 ldr r1, =( NETARM_GEN_SYS_CFG_LENDIAN | \
314 NETARM_GEN_SYS_CFG_BUSFULL | \
315 NETARM_GEN_SYS_CFG_USER_EN | \
316 NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
317 NETARM_GEN_SYS_CFG_BUSARB_INT | \
318 NETARM_GEN_SYS_CFG_BUSMON_EN )
320 str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
322 #ifndef CONFIG_NETARM_PLL_BYPASS
323 ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
324 NETARM_GEN_PLL_CTL_POLTST_DEF | \
325 NETARM_GEN_PLL_CTL_INDIV(1) | \
326 NETARM_GEN_PLL_CTL_ICP_DEF | \
327 NETARM_GEN_PLL_CTL_OUTDIV(2) )
328 str r1, [r0, #+NETARM_GEN_PLL_CONTROL]
332 * mask all IRQs by clearing all bits in the INTMRs
335 ldr r0, =NETARM_GEN_MODULE_BASE
336 str r1, [r0, #+NETARM_GEN_INTR_ENABLE]
338 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
339 /* No specific initialisation for IntegratorAP/CM720T as yet */
340 #elif defined(CONFIG_TEGRA)
341 /* No cpu_init_crit for tegra as yet */
343 #error No cpu_init_crit() defined for current CPU type
346 #ifdef CONFIG_ARM7_REVD
347 /* set clock speed */
348 /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
349 /* !!! not doing DRAM refresh properly! */
353 orr r1, r1, #CLKCTL_36
357 #if !defined(CONFIG_TEGRA)
360 * before relocating, we have to setup RAM timing
361 * because memory timing is board-dependent, you will
362 * find a lowlevel_init.S in your board directory.
371 #ifndef CONFIG_SPL_BUILD
373 *************************************************************************
377 *************************************************************************
383 #define S_FRAME_SIZE 72
405 #define MODE_SVC 0x13
409 * use bad_save_user_regs for abort/prefetch/undef/swi ...
410 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
413 .macro bad_save_user_regs
414 sub sp, sp, #S_FRAME_SIZE
415 stmia sp, {r0 - r12} @ Calling r0-r12
418 ldr r2, IRQ_STACK_START_IN
419 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
420 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
424 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
428 .macro irq_save_user_regs
429 sub sp, sp, #S_FRAME_SIZE
430 stmia sp, {r0 - r12} @ Calling r0-r12
432 stmdb r8, {sp, lr}^ @ Calling SP, LR
433 str lr, [r8, #0] @ Save calling PC
435 str r6, [r8, #4] @ Save CPSR
436 str r0, [r8, #8] @ Save OLD_R0
440 .macro irq_restore_user_regs
441 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
443 ldr lr, [sp, #S_PC] @ Get PC
444 add sp, sp, #S_FRAME_SIZE
445 subs pc, lr, #4 @ return & move spsr_svc into cpsr
449 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
451 str lr, [r13] @ save caller lr / spsr
455 mov r13, #MODE_SVC @ prepare SVC-Mode
461 .macro get_irq_stack @ setup IRQ stack
462 ldr sp, IRQ_STACK_START
465 .macro get_fiq_stack @ setup FIQ stack
466 ldr sp, FIQ_STACK_START
473 undefined_instruction:
476 bl do_undefined_instruction
482 bl do_software_interrupt
502 #ifdef CONFIG_USE_IRQ
509 irq_restore_user_regs
514 /* someone ought to write a more effiction fiq_save_user_regs */
517 irq_restore_user_regs
534 #endif /* CONFIG_SPL_BUILD */
536 #if defined(CONFIG_NETARM)
540 ldr r1, =NETARM_MEM_MODULE_BASE
541 ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
544 ldr r1, =(relocate-CONFIG_SYS_TEXT_BASE)
546 ldr r4, =NETARM_GEN_MODULE_BASE
547 ldr r1, =NETARM_GEN_SW_SVC_RESETA
548 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
549 ldr r1, =NETARM_GEN_SW_SVC_RESETB
550 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
551 ldr r1, =NETARM_GEN_SW_SVC_RESETA
552 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
553 ldr r1, =NETARM_GEN_SW_SVC_RESETB
554 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
556 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
557 /* No specific reset actions for IntegratorAP/CM720T as yet */
558 #elif defined(CONFIG_TEGRA)
559 /* No specific reset actions for tegra as yet */
561 #error No reset_cpu() defined for current CPU type