2 * armboot - Startup Code for ARM1176 CPU-core
4 * Copyright (c) 2007 Samsung Electronics
7 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
28 * 2007-09-21 - Added MoviNAND and OneNAND boot codes by
29 * jsgood (jsgood.yang@samsung.com)
30 * Base codes by scsuh (sc.suh)
33 #include <asm-offsets.h>
36 #ifdef CONFIG_ENABLE_MMU
37 #include <asm/proc/domain.h>
40 #if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
41 #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
45 *************************************************************************
47 * Jump vector table as in table 3.1 in [1]
49 *************************************************************************
54 #ifndef CONFIG_NAND_SPL
55 ldr pc, _undefined_instruction
56 ldr pc, _software_interrupt
57 ldr pc, _prefetch_abort
63 _undefined_instruction:
64 .word undefined_instruction
66 .word software_interrupt
78 .word 0x12345678 /* now 16*4=64 */
85 .balignl 16,0xdeadbeef
87 *************************************************************************
89 * Startup Code (reset vector)
91 * do important init only if we don't start from memory!
92 * setup Memory and board specific bits prior to relocation.
93 * relocate armboot to ram
96 *************************************************************************
101 #ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
102 .word CONFIG_SYS_TEXT_BASE
104 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
105 .word CONFIG_SPL_TEXT_BASE
107 .word CONFIG_SYS_TEXT_BASE
112 * Below variable is very important because we use MMU in U-Boot.
113 * Without it, we cannot run code correctly before MMU is ON.
117 .word CONFIG_SYS_PHY_UBOOT_BASE
120 * These are defined in the board-specific linker script.
121 * Subtracting _start from them lets the linker put their
122 * relative position in the executable instead of leaving
126 .globl _bss_start_ofs
128 .word __bss_start - _start
132 .word __bss_end - _start
138 /* IRQ stack memory (calculated at run-time) + 8 bytes */
139 .globl IRQ_STACK_START_IN
144 * the actual reset code
149 * set the cpu to SVC32 mode
157 *************************************************************************
159 * CPU_init_critical registers
161 * setup important registers
162 * setup memory timing
164 *************************************************************************
167 * we do sys-critical inits only at reboot,
168 * not when booting from ram!
172 * When booting from NAND - it has definitely been a reset, so, no need
173 * to flush caches and disable the MMU
175 #ifndef CONFIG_NAND_SPL
177 * flush v4 I/D caches
180 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
181 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
184 * disable MMU stuff and caches
186 mrc p15, 0, r0, c1, c0, 0
187 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
188 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
189 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
190 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
192 /* Prepare to disable the MMU */
193 adr r2, mmu_disable_phys
194 sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
198 /* Run in a single cache-line */
200 mcr p15, 0, r0, c1, c0, 0
206 #ifdef CONFIG_DISABLE_TCM
210 mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
216 mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
218 mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
223 #ifdef CONFIG_PERIPORT_REMAP
224 /* Peri port setup */
225 ldr r0, =CONFIG_PERIPORT_BASE
226 orr r0, r0, #CONFIG_PERIPORT_SIZE
227 mcr p15,0,r0,c15,c2,4
231 * Go setup Memory and board specific bits prior to relocation.
233 bl lowlevel_init /* go setup pll,mux,memory */
237 /*------------------------------------------------------------------------------*/
240 * void relocate_code (addr_sp, gd, addr_moni)
242 * This "function" does not return, instead it continues in RAM
243 * after relocating the monitor code.
248 mov r4, r0 /* save addr_sp */
249 mov r5, r1 /* save addr of gd */
250 mov r6, r2 /* save addr of destination */
254 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
255 beq relocate_done /* skip relocation */
256 mov r1, r6 /* r1 <- scratch for copy_loop */
257 ldr r3, _bss_start_ofs
258 add r2, r0, r3 /* r2 <- source end address */
261 ldmia r0!, {r9-r10} /* copy from source address [r0] */
262 stmia r1!, {r9-r10} /* copy to target address [r1] */
263 cmp r0, r2 /* until source end address [r2] */
266 #ifndef CONFIG_SPL_BUILD
268 * fix .rel.dyn relocations
270 ldr r0, _TEXT_BASE /* r0 <- Text base */
271 sub r9, r6, r0 /* r9 <- relocation offset */
272 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
273 add r10, r10, r0 /* r10 <- sym table in FLASH */
274 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
275 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
276 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
277 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
279 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
280 add r0, r0, r9 /* r0 <- location to fix up in RAM */
283 cmp r7, #23 /* relative fixup? */
285 cmp r7, #2 /* absolute fixup? */
287 /* ignore unknown type of fixup */
290 /* absolute fix: set location to (offset) symbol value */
291 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
292 add r1, r10, r1 /* r1 <- address of symbol in table */
293 ldr r1, [r1, #4] /* r1 <- symbol value */
294 add r1, r1, r9 /* r1 <- relocated sym addr */
297 /* relative fix: increase location by offset */
302 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
307 #ifdef CONFIG_ENABLE_MMU
309 /* enable domain access */
311 mcr p15, 0, r5, c3, c0, 0 /* load domain access register */
313 /* Set the TTB register */
314 ldr r0, _mmu_table_base
315 ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE
319 mcr p15, 0, r1, c2, c0, 0
322 mrc p15, 0, r0, c1, c0, 0
323 orr r0, r0, #1 /* Set CR_M to enable MMU */
325 /* Prepare to enable the MMU */
335 /* Run in a single cache-line */
338 mcr p15, 0, r0, c1, c0, 0
350 .word __rel_dyn_start - _start
352 .word __rel_dyn_end - _start
354 .word __dynsym_start - _start
356 #ifdef CONFIG_ENABLE_MMU
361 .globl c_runtime_cpu_setup
366 #ifndef CONFIG_NAND_SPL
368 * we assume that cache operation is done before. (eg. cleanup_before_linux())
369 * actually, we don't need to do anything about cache if not use d-cache in
370 * U-Boot. So, in this function we clean only MMU. by scsuh
372 * void theLastJump(void *kernel, int arch_num, uint boot_params);
374 #ifdef CONFIG_ENABLE_MMU
379 ldr r4, _TEXT_PHY_BASE
380 adr r5, phy_last_jump
388 mrc p15, 0, r0, c1, c0, 0
389 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
390 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
391 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
392 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
393 mcr p15, 0, r0, c1, c0, 0
395 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
403 *************************************************************************
407 *************************************************************************
412 #define S_FRAME_SIZE 72
434 #define MODE_SVC 0x13
438 * use bad_save_user_regs for abort/prefetch/undef/swi ...
441 .macro bad_save_user_regs
442 /* carve out a frame on current user stack */
443 sub sp, sp, #S_FRAME_SIZE
444 /* Save user registers (now in svc mode) r0-r12 */
447 ldr r2, IRQ_STACK_START_IN
448 /* get values for "aborted" pc and cpsr (into parm regs) */
450 /* grab pointer to old stack */
451 add r0, sp, #S_FRAME_SIZE
455 /* save sp_SVC, lr_SVC, pc, cpsr */
457 /* save current stack into r0 (param register) */
462 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
464 /* save caller lr in position 0 of saved stack */
468 /* save spsr in position 1 of saved stack */
471 /* prepare SVC-Mode */
474 /* switch modes, make sure moves will execute */
476 /* capture return pc */
478 /* jump to next instruction & switch modes. */
482 .macro get_bad_stack_swi
483 /* space on current stack for scratch reg. */
485 /* save R0's value. */
487 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
488 /* save caller lr in position 0 of saved stack */
492 /* save spsr in position 1 of saved stack */
496 /* pop stack entry */
504 undefined_instruction:
507 bl do_undefined_instruction
513 bl do_software_interrupt
544 #endif /* CONFIG_NAND_SPL */