2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 #ifdef CONFIG_PRELOADER
52 .word 0x12345678 /* now 16*4=64 */
54 ldr pc, _undefined_instruction
55 ldr pc, _software_interrupt
56 ldr pc, _prefetch_abort
62 _undefined_instruction: .word undefined_instruction
63 _software_interrupt: .word software_interrupt
64 _prefetch_abort: .word prefetch_abort
65 _data_abort: .word data_abort
66 _not_used: .word not_used
69 _pad: .word 0x12345678 /* now 16*4=64 */
70 #endif /* CONFIG_PRELOADER */
74 .balignl 16,0xdeadbeef
76 *************************************************************************
78 * Startup Code (reset vector)
80 * do important init only if we don't start from memory!
81 * setup Memory and board specific bits prior to relocation.
82 * relocate armboot to ram
85 *************************************************************************
96 * These are defined in the board-specific linker script.
106 #ifdef CONFIG_USE_IRQ
107 /* IRQ stack memory (calculated at run-time) */
108 .globl IRQ_STACK_START
112 /* IRQ stack memory (calculated at run-time) */
113 .globl FIQ_STACK_START
119 * the actual reset code
124 * set the cpu to SVC32 mode
131 #ifdef CONFIG_OMAP2420H4
132 /* Copy vectors to mask ROM indirect addr */
133 adr r0, _start /* r0 <- current position of code */
134 add r0, r0, #4 /* skip reset vector */
135 mov r2, #64 /* r2 <- size to copy */
136 add r2, r0, r2 /* r2 <- source end address */
137 mov r1, #SRAM_OFFSET0 /* build vect addr */
138 mov r3, #SRAM_OFFSET1
140 mov r3, #SRAM_OFFSET2
143 ldmia r0!, {r3-r10} /* copy from source address [r0] */
144 stmia r1!, {r3-r10} /* copy to target address [r1] */
145 cmp r0, r2 /* until source end address [r2] */
146 bne next /* loop until equal */
147 bl cpy_clk_code /* put dpll adjust code behind vectors */
149 /* the mask ROM code should have PLL and others stable */
150 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
154 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
155 relocate: /* relocate U-Boot to RAM */
156 adr r0, _start /* r0 <- current position of code */
157 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
158 cmp r0, r1 /* don't reloc during debug */
159 #ifndef CONFIG_PRELOADER
161 #endif /* CONFIG_PRELOADER */
163 ldr r2, _armboot_start
165 sub r2, r3, r2 /* r2 <- size of armboot */
166 add r2, r0, r2 /* r2 <- source end address */
169 ldmia r0!, {r3-r10} /* copy from source address [r0] */
170 stmia r1!, {r3-r10} /* copy to target address [r1] */
171 cmp r0, r2 /* until source end addreee [r2] */
173 #endif /* CONFIG_SKIP_RELOCATE_UBOOT */
175 /* Set up the stack */
177 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
178 #ifdef CONFIG_PRELOADER
179 sub sp, r0, #128 /* leave 32 words for abort-stack */
181 sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
182 sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
183 #ifdef CONFIG_USE_IRQ
184 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
186 sub sp, r0, #12 /* leave 3 words for abort-stack */
187 #endif /* CONFIG_PRELOADER */
188 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
191 ldr r0, _bss_start /* find start of bss segment */
192 ldr r1, _bss_end /* stop here */
193 mov r2, #0x00000000 /* clear */
195 #ifndef CONFIG_PRELOADER
196 clbss_l:str r2, [r0] /* clear loop... */
202 ldr pc, _start_armboot
204 #ifdef CONFIG_NAND_SPL
205 _start_armboot: .word nand_boot
207 #ifdef CONFIG_ONENAND_IPL
208 _start_armboot: .word start_oneboot
210 _start_armboot: .word start_armboot
211 #endif /* CONFIG_ONENAND_IPL */
212 #endif /* CONFIG_NAND_SPL */
215 *************************************************************************
217 * CPU_init_critical registers
219 * setup important registers
220 * setup memory timing
222 *************************************************************************
224 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
227 * flush v4 I/D caches
230 mcr p15, 0, r0, c7, c7, 0 /* Invalidate I+D+BTB caches */
231 mcr p15, 0, r0, c8, c7, 0 /* Invalidate Unified TLB */
234 * disable MMU stuff and caches
236 mrc p15, 0, r0, c1, c0, 0
237 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
238 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
239 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
240 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
241 mcr p15, 0, r0, c1, c0, 0
244 * Jump to board specific initialization... The Mask ROM will have already initialized
245 * basic memory. Go here to bump up clock rate and handle wake up conditions.
247 mov ip, lr /* persevere link reg across call */
248 bl lowlevel_init /* go setup pll,mux,memory */
249 mov lr, ip /* restore link */
250 mov pc, lr /* back to my caller */
251 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
253 #ifndef CONFIG_PRELOADER
255 *************************************************************************
259 *************************************************************************
264 #define S_FRAME_SIZE 72
286 #define MODE_SVC 0x13
290 * use bad_save_user_regs for abort/prefetch/undef/swi ...
291 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
294 .macro bad_save_user_regs
295 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
296 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
298 ldr r2, _armboot_start
299 sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
300 sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
301 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
302 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
306 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
307 mov r0, sp @ save current stack into r0 (param register)
310 .macro irq_save_user_regs
311 sub sp, sp, #S_FRAME_SIZE
312 stmia sp, {r0 - r12} @ Calling r0-r12
313 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
314 stmdb r8, {sp, lr}^ @ Calling SP, LR
315 str lr, [r8, #0] @ Save calling PC
317 str r6, [r8, #4] @ Save CPSR
318 str r0, [r8, #8] @ Save OLD_R0
322 .macro irq_restore_user_regs
323 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
325 ldr lr, [sp, #S_PC] @ Get PC
326 add sp, sp, #S_FRAME_SIZE
327 subs pc, lr, #4 @ return & move spsr_svc into cpsr
331 ldr r13, _armboot_start @ setup our mode stack (enter in banked mode)
332 sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
333 sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack
335 str lr, [r13] @ save caller lr in position 0 of saved stack
336 mrs lr, spsr @ get the spsr
337 str lr, [r13, #4] @ save spsr in position 1 of saved stack
339 mov r13, #MODE_SVC @ prepare SVC-Mode
341 msr spsr, r13 @ switch modes, make sure moves will execute
342 mov lr, pc @ capture return pc
343 movs pc, lr @ jump to next instruction & switch modes.
346 .macro get_bad_stack_swi
347 sub r13, r13, #4 @ space on current stack for scratch reg.
348 str r0, [r13] @ save R0's value.
349 ldr r0, _armboot_start @ get data regions start
350 sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
351 sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move past gbl and a couple spots for abort stack
352 str lr, [r0] @ save caller lr in position 0 of saved stack
353 mrs r0, spsr @ get the spsr
354 str lr, [r0, #4] @ save spsr in position 1 of saved stack
355 ldr r0, [r13] @ restore r0
356 add r13, r13, #4 @ pop stack entry
359 .macro get_irq_stack @ setup IRQ stack
360 ldr sp, IRQ_STACK_START
363 .macro get_fiq_stack @ setup FIQ stack
364 ldr sp, FIQ_STACK_START
366 #endif /* CONFIG_PRELOADER */
371 #ifdef CONFIG_PRELOADER
374 ldr sp, _TEXT_BASE /* use 32 words about stack */
375 bl hang /* hang and never return */
376 #else /* !CONFIG_PRELOADER */
378 undefined_instruction:
381 bl do_undefined_instruction
387 bl do_software_interrupt
407 #ifdef CONFIG_USE_IRQ
414 irq_restore_user_regs
419 /* someone ought to write a more effiction fiq_save_user_regs */
422 irq_restore_user_regs
440 .global arm1136_cache_flush
442 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
443 mov pc, lr @ back to caller
444 #endif /* CONFIG_PRELOADER */