3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/errno.h>
30 #include <asm/arch/imx-regs.h>
31 #include <asm/arch/crm_regs.h>
32 #include <asm/arch/clock.h>
33 #include <asm/arch/sys_proto.h>
34 #ifdef CONFIG_FSL_ESDHC
35 #include <fsl_esdhc.h>
39 #define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
40 #define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF)
41 #define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF)
42 #define CLK_CODE_PATH(c) ((c) & 0xFF)
44 #define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
46 #ifdef CONFIG_FSL_ESDHC
47 DECLARE_GLOBAL_DATA_PTR;
50 static int g_clk_mux_auto[8] = {
51 CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1,
52 CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1,
55 static int g_clk_mux_consumer[16] = {
56 CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1,
57 -1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0),
58 CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1,
59 -1, -1, CLK_CODE(4, 2, 0), -1,
62 static int hsp_div_table[3][16] = {
63 {4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1},
64 {-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1},
65 {3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1},
71 struct iim_regs *iim =
72 (struct iim_regs *)IIM_BASE_ADDR;
73 reg = readl(&iim->iim_srev);
75 reg = readw(ROMPATCH_REV);
81 return 0x35000 + (reg & 0xFF);
84 static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd)
87 if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
88 pclk_mux = g_clk_mux_consumer +
89 ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
90 MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
92 pclk_mux = g_clk_mux_auto +
93 ((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >>
94 MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET);
97 if ((*pclk_mux) == -1)
101 if (!CLK_CODE_PATH(*pclk_mux)) {
103 return CLK_CODE_ARM(*pclk_mux);
105 if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
113 return CLK_CODE_ARM(*pclk_mux);
116 static int get_ahb_div(u32 pdr0)
120 pclk_mux = g_clk_mux_consumer +
121 ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
122 MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
124 if ((*pclk_mux) == -1)
127 return CLK_CODE_AHB(*pclk_mux);
130 static u32 decode_pll(u32 reg, u32 infreq)
132 u32 mfi = (reg >> 10) & 0xf;
133 s32 mfn = reg & 0x3ff;
134 u32 mfd = (reg >> 16) & 0x3ff;
135 u32 pd = (reg >> 26) & 0xf;
137 mfi = mfi <= 5 ? 5 : mfi;
138 mfn = mfn >= 512 ? mfn - 1024 : mfn;
142 return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
146 static u32 get_mcu_main_clk(void)
148 u32 arm_div = 0, fi = 0, fd = 0;
149 struct ccm_regs *ccm =
150 (struct ccm_regs *)IMX_CCM_BASE;
151 arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
153 decode_pll(readl(&ccm->mpctl),
154 CONFIG_MX35_HCLK_FREQ);
155 return fi / (arm_div * fd);
158 static u32 get_ipg_clk(void)
160 u32 freq = get_mcu_main_clk();
161 struct ccm_regs *ccm =
162 (struct ccm_regs *)IMX_CCM_BASE;
163 u32 pdr0 = readl(&ccm->pdr0);
165 return freq / (get_ahb_div(pdr0) * 2);
168 static u32 get_ipg_per_clk(void)
170 u32 freq = get_mcu_main_clk();
171 struct ccm_regs *ccm =
172 (struct ccm_regs *)IMX_CCM_BASE;
173 u32 pdr0 = readl(&ccm->pdr0);
174 u32 pdr4 = readl(&ccm->pdr4);
176 if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
177 div = (CCM_GET_DIVIDER(pdr4,
178 MXC_CCM_PDR4_PER0_PRDF_MASK,
179 MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) *
180 (CCM_GET_DIVIDER(pdr4,
181 MXC_CCM_PDR4_PER0_PODF_MASK,
182 MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1);
184 div = CCM_GET_DIVIDER(pdr0,
185 MXC_CCM_PDR0_PER_PODF_MASK,
186 MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
187 freq /= get_ahb_div(pdr0);
192 u32 imx_get_uartclk(void)
195 struct ccm_regs *ccm =
196 (struct ccm_regs *)IMX_CCM_BASE;
197 u32 pdr4 = readl(&ccm->pdr4);
199 if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) {
200 freq = get_mcu_main_clk();
202 freq = decode_pll(readl(&ccm->ppctl),
203 CONFIG_MX35_HCLK_FREQ);
205 freq /= ((CCM_GET_DIVIDER(pdr4,
206 MXC_CCM_PDR4_UART_PRDF_MASK,
207 MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) *
208 (CCM_GET_DIVIDER(pdr4,
209 MXC_CCM_PDR4_UART_PODF_MASK,
210 MXC_CCM_PDR4_UART_PODF_OFFSET) + 1));
214 unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
216 u32 nfc_pdf, hsp_podf;
217 u32 pll, ret_val = 0, usb_prdf, usb_podf;
218 struct ccm_regs *ccm =
219 (struct ccm_regs *)IMX_CCM_BASE;
221 u32 reg = readl(&ccm->pdr0);
222 u32 reg4 = readl(&ccm->pdr4);
228 ret_val = get_mcu_main_clk();
231 ret_val = get_mcu_main_clk();
234 if (reg & CLKMODE_CONSUMER) {
235 hsp_podf = (reg >> 20) & 0x3;
236 pll = get_mcu_main_clk();
237 hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF];
239 ret_val = pll / hsp_podf;
241 puts("mismatch HSP with ARM clock setting\n");
245 ret_val = get_mcu_main_clk();
249 ret_val = get_ipg_clk();
252 ret_val = get_ipg_per_clk();
255 nfc_pdf = (reg4 >> 28) & 0xF;
256 pll = get_mcu_main_clk();
258 ret_val = pll / (nfc_pdf + 1);
261 usb_prdf = (reg4 >> 25) & 0x7;
262 usb_podf = (reg4 >> 22) & 0x7;
264 pll = get_mcu_main_clk();
266 pll = decode_pll(readl(&ccm->ppctl),
267 CONFIG_MX35_HCLK_FREQ);
270 ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1));
273 printf("Unknown clock: %d\n", clk);
279 unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
281 u32 ret_val = 0, pdf, pre_pdf, clk_sel;
282 struct ccm_regs *ccm =
283 (struct ccm_regs *)IMX_CCM_BASE;
284 u32 mpdr2 = readl(&ccm->pdr2);
285 u32 mpdr3 = readl(&ccm->pdr3);
286 u32 mpdr4 = readl(&ccm->pdr4);
292 clk_sel = mpdr3 & (1 << 14);
293 pre_pdf = (mpdr4 >> 13) & 0x7;
294 pdf = (mpdr4 >> 10) & 0x7;
295 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
296 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
297 ((pre_pdf + 1) * (pdf + 1));
300 pre_pdf = (mpdr2 >> 24) & 0x7;
302 clk_sel = mpdr2 & (1 << 6);
303 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
304 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
305 ((pre_pdf + 1) * (pdf + 1));
308 pre_pdf = (mpdr2 >> 27) & 0x7;
309 pdf = (mpdr2 >> 8) & 0x3F;
310 clk_sel = mpdr2 & (1 << 6);
311 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
312 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
313 ((pre_pdf + 1) * (pdf + 1));
316 clk_sel = mpdr2 & (1 << 7);
317 pre_pdf = (mpdr2 >> 16) & 0x7;
318 pdf = (mpdr2 >> 19) & 0x7;
319 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
320 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
321 ((pre_pdf + 1) * (pdf + 1));
324 pre_pdf = readl(&ccm->pdr1);
325 clk_sel = (pre_pdf & 0x80);
326 pdf = (pre_pdf >> 22) & 0x3F;
327 pre_pdf = (pre_pdf >> 28) & 0x7;
328 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
329 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
330 ((pre_pdf + 1) * (pdf + 1));
333 clk_sel = mpdr3 & 0x40;
334 pre_pdf = mpdr3 & 0x7;
335 pdf = (mpdr3>>3) & 0x7;
336 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
337 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
338 ((pre_pdf + 1) * (pdf + 1));
341 clk_sel = mpdr3 & 0x40;
342 pre_pdf = (mpdr3 >> 8) & 0x7;
343 pdf = (mpdr3 >> 11) & 0x7;
344 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
345 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
346 ((pre_pdf + 1) * (pdf + 1));
349 clk_sel = mpdr3 & 0x40;
350 pre_pdf = (mpdr3 >> 16) & 0x7;
351 pdf = (mpdr3 >> 19) & 0x7;
352 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
353 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
354 ((pre_pdf + 1) * (pdf + 1));
357 clk_sel = mpdr3 & 0x400000;
358 pre_pdf = (mpdr3 >> 29) & 0x7;
359 pdf = (mpdr3 >> 23) & 0x3F;
360 ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
361 decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
362 ((pre_pdf + 1) * (pdf + 1));
365 printf("%s(): This clock: %d not supported yet\n",
373 unsigned int mxc_get_clock(enum mxc_clock clk)
377 return get_mcu_main_clk();
381 return get_ipg_clk();
383 return get_ipg_per_clk();
385 return imx_get_uartclk();
387 return mxc_get_peri_clock(ESDHC1_CLK);
389 return mxc_get_main_clock(USB_CLK);
391 return get_ipg_clk();
393 return get_ipg_clk();
398 #ifdef CONFIG_FEC_MXC
400 * The MX35 has no fuse for MAC, return a NULL MAC
402 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
407 u32 imx_get_fecclk(void)
409 return mxc_get_clock(MXC_IPG_CLK);
413 int do_mx35_showclocks(cmd_tbl_t *cmdtp,
414 int flag, int argc, char * const argv[])
416 u32 cpufreq = get_mcu_main_clk();
417 printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000);
418 printf("ipg clock : %dHz\n", get_ipg_clk());
419 printf("ipg per clock : %dHz\n", get_ipg_per_clk());
420 printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
426 clocks, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks,
431 #if defined(CONFIG_DISPLAY_CPUINFO)
432 static char *get_reset_cause(void)
434 /* read RCSR register from CCM module */
435 struct ccm_regs *ccm =
436 (struct ccm_regs *)IMX_CCM_BASE;
438 u32 cause = readl(&ccm->rcsr) & 0x0F;
450 return "unknown reset";
454 int print_cpuinfo(void)
456 u32 srev = get_cpu_rev();
458 printf("CPU: Freescale i.MX35 rev %d.%d at %d MHz.\n",
459 (srev & 0xF0) >> 4, (srev & 0x0F),
460 get_mcu_main_clk() / 1000000);
462 printf("Reset cause: %s\n", get_reset_cause());
469 * Initializes on-chip ethernet controllers.
470 * to override, implement board_eth_init()
472 int cpu_eth_init(bd_t *bis)
476 #if defined(CONFIG_FEC_MXC)
477 rc = fecmxc_initialize(bis);
483 #ifdef CONFIG_FSL_ESDHC
485 * Initializes on-chip MMC controllers.
486 * to override, implement board_mmc_init()
488 int cpu_mmc_init(bd_t *bis)
490 return fsl_esdhc_mmc_init(bis);
496 #ifdef CONFIG_FSL_ESDHC
497 gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
502 void reset_cpu(ulong addr)
504 struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
505 writew(4, &wdog->wcr);