3 * Sascha Hauer, Pengutronix
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/clock.h>
29 static u32 mx31_decode_pll(u32 reg, u32 infreq)
31 u32 mfi = (reg >> 10) & 0xf;
32 u32 mfn = reg & 0x3ff;
33 u32 mfd = (reg >> 16) & 0x3ff;
34 u32 pd = (reg >> 26) & 0xf;
36 mfi = mfi <= 5 ? 5 : mfi;
40 return ((2 * (infreq >> 10) * (mfi * mfd + mfn)) /
44 static u32 mx31_get_mpl_dpdgck_clk(void)
48 if ((__REG(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
49 infreq = CONFIG_MX31_CLK32 * 1024;
51 infreq = CONFIG_MX31_HCLK_FREQ;
53 return mx31_decode_pll(__REG(CCM_MPCTL), infreq);
56 static u32 mx31_get_mcu_main_clk(void)
58 /* For now we assume mpl_dpdgck_clk == mcu_main_clk
59 * which should be correct for most boards
61 return mx31_get_mpl_dpdgck_clk();
64 static u32 mx31_get_ipg_clk(void)
66 u32 freq = mx31_get_mcu_main_clk();
67 u32 pdr0 = __REG(CCM_PDR0);
69 freq /= ((pdr0 >> 3) & 0x7) + 1;
70 freq /= ((pdr0 >> 6) & 0x3) + 1;
75 void mx31_dump_clocks(void)
77 u32 cpufreq = mx31_get_mcu_main_clk();
78 printf("mx31 cpu clock: %dMHz\n",cpufreq / 1000000);
79 printf("ipg clock : %dHz\n", mx31_get_ipg_clk());
82 unsigned int mxc_get_clock(enum mxc_clock clk)
86 return mx31_get_mcu_main_clk();
90 return mx31_get_ipg_clk();
95 u32 imx_get_uartclk(void)
97 return mxc_get_clock(MXC_UART_CLK);
100 void mx31_gpio_mux(unsigned long mode)
102 unsigned long reg, shift, tmp;
104 reg = IOMUXC_BASE + (mode & 0x1fc);
105 shift = (~mode & 0x3) * 8;
108 tmp &= ~(0xff << shift);
109 tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift;
113 void mx31_set_pad(enum iomux_pins pin, u32 config)
117 pin &= IOMUX_PADNUM_MASK;
118 reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4;
119 field = (pin + 2) % 3;
122 l &= ~(0x1ff << (field * 10));
123 l |= config << (field * 10);
128 struct mx3_cpu_type mx31_cpu_type[] = {
129 { .srev = 0x00, .v = 0x10 },
130 { .srev = 0x10, .v = 0x11 },
131 { .srev = 0x11, .v = 0x11 },
132 { .srev = 0x12, .v = 0x1F },
133 { .srev = 0x13, .v = 0x1F },
134 { .srev = 0x14, .v = 0x12 },
135 { .srev = 0x15, .v = 0x12 },
136 { .srev = 0x28, .v = 0x20 },
137 { .srev = 0x29, .v = 0x20 },
140 u32 get_cpu_rev(void)
144 /* read SREV register from IIM module */
145 struct iim_regs *iim = (struct iim_regs *)MX31_IIM_BASE_ADDR;
146 srev = readl(&iim->iim_srev);
148 for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
149 if (srev == mx31_cpu_type[i].srev)
150 return mx31_cpu_type[i].v;
152 return srev | 0x8000;
155 static char *get_reset_cause(void)
157 /* read RCSR register from CCM module */
158 struct clock_control_regs *ccm =
159 (struct clock_control_regs *)CCM_BASE;
161 u32 cause = readl(&ccm->rcsr) & 0x07;
173 return "unknown reset";
177 #if defined(CONFIG_DISPLAY_CPUINFO)
178 int print_cpuinfo (void)
180 u32 srev = get_cpu_rev();
182 printf("CPU: Freescale i.MX31 rev %d.%d%s at %d MHz.",
183 (srev & 0xF0) >> 4, (srev & 0x0F),
184 ((srev & 0x8000) ? " unknown" : ""),
185 mx31_get_mcu_main_clk() / 1000000);
186 printf("Reset cause: %s\n", get_reset_cause());