2 * linux/arch/arm/common/gic.c
4 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Interrupt architecture for the GIC:
12 * o There is one Interrupt Distributor, which receives interrupts
13 * from system devices and sends them to the Interrupt Controllers.
15 * o There is one CPU Interface per CPU, which sends interrupts sent
16 * by the Distributor, and interrupts generated locally, to the
17 * associated CPU. The base address of the CPU interface is usually
18 * aliased so that the same address points to different chips depending
19 * on the CPU it is accessed from.
21 * Note that IRQs 0-31 are special - they are local to each CPU.
22 * As such, the enable set/clear, pending set/clear and active bit
23 * registers are banked per-cpu for these sources.
25 #include <linux/init.h>
26 #include <linux/kernel.h>
27 #include <linux/list.h>
28 #include <linux/smp.h>
29 #include <linux/cpumask.h>
33 #include <asm/mach/irq.h>
34 #include <asm/hardware/gic.h>
36 static DEFINE_SPINLOCK(irq_controller_lock);
38 struct gic_chip_data {
39 unsigned int irq_offset;
40 void __iomem *dist_base;
41 void __iomem *cpu_base;
48 #ifdef CONFIG_USE_EXT_GIC
49 #define GIC_OFFSET_FOR_CPU1 0x8000
52 static struct gic_chip_data gic_data[MAX_GIC_NR];
54 static inline void __iomem *gic_dist_base(unsigned int irq)
56 struct gic_chip_data *gic_data = get_irq_chip_data(irq);
58 #ifdef CONFIG_USE_EXT_GIC
59 if (hard_smp_processor_id() == 1)
60 return gic_data->dist_base + GIC_OFFSET_FOR_CPU1;
62 return gic_data->dist_base;
65 static inline void __iomem *gic_cpu_base(unsigned int irq)
67 struct gic_chip_data *gic_data = get_irq_chip_data(irq);
69 #ifdef CONFIG_USE_EXT_GIC
70 if (hard_smp_processor_id() == 1)
71 return gic_data->cpu_base + GIC_OFFSET_FOR_CPU1;
73 return gic_data->cpu_base;
76 static inline unsigned int gic_irq(unsigned int irq)
78 struct gic_chip_data *gic_data = get_irq_chip_data(irq);
79 return irq - gic_data->irq_offset;
83 * Routines to acknowledge, disable and enable interrupts
85 * Linux assumes that when we're done with an interrupt we need to
86 * unmask it, in the same way we need to unmask an interrupt when
89 * The GIC has a separate notion of "end of interrupt" to re-enable
90 * an interrupt after handling, in order to support hardware
93 * We can make the GIC behave in the way that Linux expects by making
94 * our "acknowledge" routine disable the interrupt, then mark it as
97 static void gic_ack_irq(unsigned int irq)
99 u32 mask = 1 << (irq % 32);
101 spin_lock(&irq_controller_lock);
102 writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4);
103 writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI);
104 spin_unlock(&irq_controller_lock);
107 static void gic_mask_irq(unsigned int irq)
109 u32 mask = 1 << (irq % 32);
111 spin_lock(&irq_controller_lock);
112 writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4);
113 spin_unlock(&irq_controller_lock);
116 static void gic_unmask_irq(unsigned int irq)
118 u32 mask = 1 << (irq % 32);
120 spin_lock(&irq_controller_lock);
121 writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_SET + (gic_irq(irq) / 32) * 4);
122 spin_unlock(&irq_controller_lock);
125 static int gic_set_type(unsigned int irq, unsigned int type)
127 void __iomem *base = gic_dist_base(irq);
128 unsigned int gicirq = gic_irq(irq);
129 u32 enablemask = 1 << (gicirq % 32);
130 u32 enableoff = (gicirq / 32) * 4;
131 u32 confmask = 0x2 << ((gicirq % 16) * 2);
132 u32 confoff = (gicirq / 16) * 4;
133 bool enabled = false;
136 /* Interrupt configuration for SGIs can't be changed */
140 if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
143 spin_lock(&irq_controller_lock);
145 val = readl(base + GIC_DIST_CONFIG + confoff);
146 if (type == IRQ_TYPE_LEVEL_HIGH)
148 else if (type == IRQ_TYPE_EDGE_RISING)
152 * As recommended by the spec, disable the interrupt before changing
155 if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
156 writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
160 writel(val, base + GIC_DIST_CONFIG + confoff);
163 writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
165 spin_unlock(&irq_controller_lock);
171 static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)
173 void __iomem *reg = gic_dist_base(irq) + GIC_DIST_TARGET + (gic_irq(irq) & ~3);
174 unsigned int shift = (irq % 4) * 8;
175 unsigned int cpu = cpumask_first(mask_val);
176 struct irq_desc *desc;
179 desc = irq_to_desc(irq);
181 spin_lock(&irq_controller_lock);
183 val = readl(reg) & ~(0xff << shift);
184 val |= 1 << (cpu + shift);
186 spin_unlock(&irq_controller_lock);
193 static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
195 struct gic_chip_data *chip_data = get_irq_data(irq);
196 struct irq_chip *chip = get_irq_chip(irq);
197 unsigned int cascade_irq, gic_irq;
198 unsigned long status;
200 /* primary controller ack'ing */
203 spin_lock(&irq_controller_lock);
204 status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
205 spin_unlock(&irq_controller_lock);
207 gic_irq = (status & 0x3ff);
211 cascade_irq = gic_irq + chip_data->irq_offset;
212 if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
213 do_bad_IRQ(cascade_irq, desc);
215 generic_handle_irq(cascade_irq);
218 /* primary controller unmasking */
222 static struct irq_chip gic_chip = {
225 .mask = gic_mask_irq,
226 .unmask = gic_unmask_irq,
227 .set_type = gic_set_type,
229 .set_affinity = gic_set_cpu,
233 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
235 if (gic_nr >= MAX_GIC_NR)
237 if (set_irq_data(irq, &gic_data[gic_nr]) != 0)
239 set_irq_chained_handler(irq, gic_handle_cascade_irq);
242 void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
243 unsigned int irq_start)
245 unsigned int max_irq, i;
246 u32 cpumask = 1 << smp_processor_id();
248 if (gic_nr >= MAX_GIC_NR)
251 cpumask |= cpumask << 8;
252 cpumask |= cpumask << 16;
254 gic_data[gic_nr].dist_base = base;
255 gic_data[gic_nr].irq_offset = (irq_start - 1) & ~31;
257 writel(0, base + GIC_DIST_CTRL);
260 * Find out how many interrupts are supported.
262 max_irq = readl(base + GIC_DIST_CTR) & 0x1f;
263 max_irq = (max_irq + 1) * 32;
266 * The GIC only supports up to 1020 interrupt sources.
267 * Limit this to either the architected maximum, or the
270 if (max_irq > max(1020, NR_IRQS))
271 max_irq = max(1020, NR_IRQS);
274 * Set all global interrupts to be level triggered, active low.
276 for (i = 32; i < max_irq; i += 16)
277 writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);
280 * Set all global interrupts to this CPU only.
282 for (i = 32; i < max_irq; i += 4)
283 writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
286 * Set priority on all global interrupts.
288 for (i = 32; i < max_irq; i += 4)
289 writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
292 * Disable all interrupts. Leavethe PPI and SGIs alone
293 * as these enables are banked registers.
295 for (i = 32; i < max_irq; i += 32)
296 writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
299 * Setup the Linux IRQ subsystem.
301 for (i = irq_start; i < gic_data[gic_nr].irq_offset + max_irq; i++) {
302 set_irq_chip(i, &gic_chip);
303 set_irq_chip_data(i, &gic_data[gic_nr]);
304 set_irq_handler(i, handle_level_irq);
305 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
308 writel(1, base + GIC_DIST_CTRL);
311 void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)
313 void __iomem *dist_base;
316 if (gic_nr >= MAX_GIC_NR)
319 dist_base = gic_data[gic_nr].dist_base;
322 gic_data[gic_nr].cpu_base = base;
325 * Deal with the banked PPI and SGI interrupts - disable all
326 * PPI interrupts, ensure all SGI interrupts are enabled.
328 writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
329 writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
332 * Set priority on PPI and SGI interrupts
334 for (i = 0; i < 32; i += 4)
335 writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
337 #ifdef CONFIG_USE_EXT_GIC
338 if (hard_smp_processor_id() == 1) {
339 writel(0xf0, base + GIC_CPU_PRIMASK + GIC_OFFSET_FOR_CPU1);
340 writel(1, base + GIC_CPU_CTRL + GIC_OFFSET_FOR_CPU1);
344 writel(0xf0, base + GIC_CPU_PRIMASK);
345 writel(1, base + GIC_CPU_CTRL);
349 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
351 unsigned long map = *cpus_addr(*mask);
353 #ifdef CONFIG_USE_EXT_GIC
354 if (hard_smp_processor_id() == 1) {
355 writel(map << 16 | irq, gic_data[0].dist_base +
356 GIC_DIST_SOFTINT + GIC_OFFSET_FOR_CPU1);
361 /* this always happens on GIC0 */
362 writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);