arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts

   1 /*
   2  * ARM Ltd. Versatile Express
   3  *
   4  * CoreTile Express A15x2 A7x3
   5  * Cortex-A15_A7 MPCore (V2P-CA15_A7)
   6  *
   7  * HBI-0249A
   8  */
   9
  10 /dts-v1/;
  11
  12 / {
  13         model = "V2P-CA15_CA7";
  14         arm,hbi = <0x249>;
  15         arm,vexpress,site = <0xf>;
  16         compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         chosen { };
  22
  23         aliases {
  24                 serial0 = &v2m_serial0;
  25                 serial1 = &v2m_serial1;
  26                 serial2 = &v2m_serial2;
  27                 serial3 = &v2m_serial3;
  28                 i2c0 = &v2m_i2c_dvi;
  29                 i2c1 = &v2m_i2c_pcie;
  30         };
  31
  32         cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35
  36                 cpu0: cpu@0 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a15";
  39                         reg = <0>;
  40                 };
  41
  42                 cpu1: cpu@1 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a15";
  45                         reg = <1>;
  46                 };
  47
  48                 cpu2: cpu@2 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a7";
  51                         reg = <0x100>;
  52                 };
  53
  54                 cpu3: cpu@3 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a7";
  57                         reg = <0x101>;
  58                 };
  59
  60                 cpu4: cpu@4 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a7";
  63                         reg = <0x102>;
  64                 };
  65         };
  66
  67         memory@80000000 {
  68                 device_type = "memory";
  69                 reg = <0 0x80000000 0 0x40000000>;
  70         };
  71
  72         wdt@2a490000 {
  73                 compatible = "arm,sp805", "arm,primecell";
  74                 reg = <0 0x2a490000 0 0x1000>;
  75                 interrupts = <0 98 4>;
  76                 clocks = <&oscclk6a>, <&oscclk6a>;
  77                 clock-names = "wdogclk", "apb_pclk";
  78         };
  79
  80         hdlcd@2b000000 {
  81                 compatible = "arm,hdlcd";
  82                 reg = <0 0x2b000000 0 0x1000>;
  83                 interrupts = <0 85 4>;
  84                 clocks = <&oscclk5>;
  85                 clock-names = "pxlclk";
  86         };
  87
  88         memory-controller@2b0a0000 {
  89                 compatible = "arm,pl341", "arm,primecell";
  90                 reg = <0 0x2b0a0000 0 0x1000>;
  91                 clocks = <&oscclk6a>;
  92                 clock-names = "apb_pclk";
  93         };
  94
  95         gic: interrupt-controller@2c001000 {
  96                 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  97                 #interrupt-cells = <3>;
  98                 #address-cells = <0>;
  99                 interrupt-controller;
 100                 reg = <0 0x2c001000 0 0x1000>,
 101                       <0 0x2c002000 0 0x1000>,
 102                       <0 0x2c004000 0 0x2000>,
 103                       <0 0x2c006000 0 0x2000>;
 104                 interrupts = <1 9 0xf04>;
 105         };
 106
 107         memory-controller@7ffd0000 {
 108                 compatible = "arm,pl354", "arm,primecell";
 109                 reg = <0 0x7ffd0000 0 0x1000>;
 110                 interrupts = <0 86 4>,
 111                              <0 87 4>;
 112                 clocks = <&oscclk6a>;
 113                 clock-names = "apb_pclk";
 114         };
 115
 116         dma@7ff00000 {
 117                 compatible = "arm,pl330", "arm,primecell";
 118                 reg = <0 0x7ff00000 0 0x1000>;
 119                 interrupts = <0 92 4>,
 120                              <0 88 4>,
 121                              <0 89 4>,
 122                              <0 90 4>,
 123                              <0 91 4>;
 124                 clocks = <&oscclk6a>;
 125                 clock-names = "apb_pclk";
 126         };
 127
 128         scc@7fff0000 {
 129                 compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
 130                 reg = <0 0x7fff0000 0 0x1000>;
 131                 interrupts = <0 95 4>;
 132         };
 133
 134         timer {
 135                 compatible = "arm,armv7-timer";
 136                 interrupts = <1 13 0xf08>,
 137                              <1 14 0xf08>,
 138                              <1 11 0xf08>,
 139                              <1 10 0xf08>;
 140         };
 141
 142         pmu {
 143                 compatible = "arm,cortex-a15-pmu";
 144                 interrupts = <0 68 4>,
 145                              <0 69 4>;
 146         };
 147
 148         oscclk6a: oscclk6a {
 149                 /* Reference 24MHz clock */
 150                 compatible = "fixed-clock";
 151                 #clock-cells = <0>;
 152                 clock-frequency = <24000000>;
 153                 clock-output-names = "oscclk6a";
 154         };
 155
 156         dcc {
 157                 compatible = "arm,vexpress,config-bus";
 158                 arm,vexpress,config-bridge = <&v2m_sysreg>;
 159
 160                 osc@0 {
 161                         /* A15 PLL 0 reference clock */
 162                         compatible = "arm,vexpress-osc";
 163                         arm,vexpress-sysreg,func = <1 0>;
 164                         freq-range = <17000000 50000000>;
 165                         #clock-cells = <0>;
 166                         clock-output-names = "oscclk0";
 167                 };
 168
 169                 osc@1 {
 170                         /* A15 PLL 1 reference clock */
 171                         compatible = "arm,vexpress-osc";
 172                         arm,vexpress-sysreg,func = <1 1>;
 173                         freq-range = <17000000 50000000>;
 174                         #clock-cells = <0>;
 175                         clock-output-names = "oscclk1";
 176                 };
 177
 178                 osc@2 {
 179                         /* A7 PLL 0 reference clock */
 180                         compatible = "arm,vexpress-osc";
 181                         arm,vexpress-sysreg,func = <1 2>;
 182                         freq-range = <17000000 50000000>;
 183                         #clock-cells = <0>;
 184                         clock-output-names = "oscclk2";
 185                 };
 186
 187                 osc@3 {
 188                         /* A7 PLL 1 reference clock */
 189                         compatible = "arm,vexpress-osc";
 190                         arm,vexpress-sysreg,func = <1 3>;
 191                         freq-range = <17000000 50000000>;
 192                         #clock-cells = <0>;
 193                         clock-output-names = "oscclk3";
 194                 };
 195
 196                 osc@4 {
 197                         /* External AXI master clock */
 198                         compatible = "arm,vexpress-osc";
 199                         arm,vexpress-sysreg,func = <1 4>;
 200                         freq-range = <20000000 40000000>;
 201                         #clock-cells = <0>;
 202                         clock-output-names = "oscclk4";
 203                 };
 204
 205                 oscclk5: osc@5 {
 206                         /* HDLCD PLL reference clock */
 207                         compatible = "arm,vexpress-osc";
 208                         arm,vexpress-sysreg,func = <1 5>;
 209                         freq-range = <23750000 165000000>;
 210                         #clock-cells = <0>;
 211                         clock-output-names = "oscclk5";
 212                 };
 213
 214                 smbclk: osc@6 {
 215                         /* Static memory controller clock */
 216                         compatible = "arm,vexpress-osc";
 217                         arm,vexpress-sysreg,func = <1 6>;
 218                         freq-range = <20000000 40000000>;
 219                         #clock-cells = <0>;
 220                         clock-output-names = "oscclk6";
 221                 };
 222
 223                 osc@7 {
 224                         /* SYS PLL reference clock */
 225                         compatible = "arm,vexpress-osc";
 226                         arm,vexpress-sysreg,func = <1 7>;
 227                         freq-range = <17000000 50000000>;
 228                         #clock-cells = <0>;
 229                         clock-output-names = "oscclk7";
 230                 };
 231
 232                 osc@8 {
 233                         /* DDR2 PLL reference clock */
 234                         compatible = "arm,vexpress-osc";
 235                         arm,vexpress-sysreg,func = <1 8>;
 236                         freq-range = <20000000 50000000>;
 237                         #clock-cells = <0>;
 238                         clock-output-names = "oscclk8";
 239                 };
 240
 241                 volt@0 {
 242                         /* A15 CPU core voltage */
 243                         compatible = "arm,vexpress-volt";
 244                         arm,vexpress-sysreg,func = <2 0>;
 245                         regulator-name = "A15 Vcore";
 246                         regulator-min-microvolt = <800000>;
 247                         regulator-max-microvolt = <1050000>;
 248                         regulator-always-on;
 249                         label = "A15 Vcore";
 250                 };
 251
 252                 volt@1 {
 253                         /* A7 CPU core voltage */
 254                         compatible = "arm,vexpress-volt";
 255                         arm,vexpress-sysreg,func = <2 1>;
 256                         regulator-name = "A7 Vcore";
 257                         regulator-min-microvolt = <800000>;
 258                         regulator-max-microvolt = <1050000>;
 259                         regulator-always-on;
 260                         label = "A7 Vcore";
 261                 };
 262
 263                 amp@0 {
 264                         /* Total current for the two A15 cores */
 265                         compatible = "arm,vexpress-amp";
 266                         arm,vexpress-sysreg,func = <3 0>;
 267                         label = "A15 Icore";
 268                 };
 269
 270                 amp@1 {
 271                         /* Total current for the three A7 cores */
 272                         compatible = "arm,vexpress-amp";
 273                         arm,vexpress-sysreg,func = <3 1>;
 274                         label = "A7 Icore";
 275                 };
 276
 277                 temp@0 {
 278                         /* DCC internal temperature */
 279                         compatible = "arm,vexpress-temp";
 280                         arm,vexpress-sysreg,func = <4 0>;
 281                         label = "DCC";
 282                 };
 283
 284                 power@0 {
 285                         /* Total power for the two A15 cores */
 286                         compatible = "arm,vexpress-power";
 287                         arm,vexpress-sysreg,func = <12 0>;
 288                         label = "A15 Pcore";
 289                 };
 290                 power@1 {
 291                         /* Total power for the three A7 cores */
 292                         compatible = "arm,vexpress-power";
 293                         arm,vexpress-sysreg,func = <12 1>;
 294                         label = "A7 Pcore";
 295                 };
 296
 297                 energy@0 {
 298                         /* Total energy for the two A15 cores */
 299                         compatible = "arm,vexpress-energy";
 300                         arm,vexpress-sysreg,func = <13 0>;
 301                         label = "A15 Jcore";
 302                 };
 303
 304                 energy@2 {
 305                         /* Total energy for the three A7 cores */
 306                         compatible = "arm,vexpress-energy";
 307                         arm,vexpress-sysreg,func = <13 2>;
 308                         label = "A7 Jcore";
 309                 };
 310         };
 311
 312         smb {
 313                 compatible = "simple-bus";
 314
 315                 #address-cells = <2>;
 316                 #size-cells = <1>;
 317                 ranges = <0 0 0 0x08000000 0x04000000>,
 318                          <1 0 0 0x14000000 0x04000000>,
 319                          <2 0 0 0x18000000 0x04000000>,
 320                          <3 0 0 0x1c000000 0x04000000>,
 321                          <4 0 0 0x0c000000 0x04000000>,
 322                          <5 0 0 0x10000000 0x04000000>;
 323
 324                 #interrupt-cells = <1>;
 325                 interrupt-map-mask = <0 0 63>;
 326                 interrupt-map = <0 0  0 &gic 0  0 4>,
 327                                 <0 0  1 &gic 0  1 4>,
 328                                 <0 0  2 &gic 0  2 4>,
 329                                 <0 0  3 &gic 0  3 4>,
 330                                 <0 0  4 &gic 0  4 4>,
 331                                 <0 0  5 &gic 0  5 4>,
 332                                 <0 0  6 &gic 0  6 4>,
 333                                 <0 0  7 &gic 0  7 4>,
 334                                 <0 0  8 &gic 0  8 4>,
 335                                 <0 0  9 &gic 0  9 4>,
 336                                 <0 0 10 &gic 0 10 4>,
 337                                 <0 0 11 &gic 0 11 4>,
 338                                 <0 0 12 &gic 0 12 4>,
 339                                 <0 0 13 &gic 0 13 4>,
 340                                 <0 0 14 &gic 0 14 4>,
 341                                 <0 0 15 &gic 0 15 4>,
 342                                 <0 0 16 &gic 0 16 4>,
 343                                 <0 0 17 &gic 0 17 4>,
 344                                 <0 0 18 &gic 0 18 4>,
 345                                 <0 0 19 &gic 0 19 4>,
 346                                 <0 0 20 &gic 0 20 4>,
 347                                 <0 0 21 &gic 0 21 4>,
 348                                 <0 0 22 &gic 0 22 4>,
 349                                 <0 0 23 &gic 0 23 4>,
 350                                 <0 0 24 &gic 0 24 4>,
 351                                 <0 0 25 &gic 0 25 4>,
 352                                 <0 0 26 &gic 0 26 4>,
 353                                 <0 0 27 &gic 0 27 4>,
 354                                 <0 0 28 &gic 0 28 4>,
 355                                 <0 0 29 &gic 0 29 4>,
 356                                 <0 0 30 &gic 0 30 4>,
 357                                 <0 0 31 &gic 0 31 4>,
 358                                 <0 0 32 &gic 0 32 4>,
 359                                 <0 0 33 &gic 0 33 4>,
 360                                 <0 0 34 &gic 0 34 4>,
 361                                 <0 0 35 &gic 0 35 4>,
 362                                 <0 0 36 &gic 0 36 4>,
 363                                 <0 0 37 &gic 0 37 4>,
 364                                 <0 0 38 &gic 0 38 4>,
 365                                 <0 0 39 &gic 0 39 4>,
 366                                 <0 0 40 &gic 0 40 4>,
 367                                 <0 0 41 &gic 0 41 4>,
 368                                 <0 0 42 &gic 0 42 4>;
 369
 370                 /include/ "vexpress-v2m-rs1.dtsi"
 371         };
 372 };