arch/arm/boot/dts/vexpress-v2m.dtsi

   1 /*
   2  * ARM Ltd. Versatile Express
   3  *
   4  * Motherboard Express uATX
   5  * V2M-P1
   6  *
   7  * HBI-0190D
   8  *
   9  * Original memory map ("Legacy memory map" in the board's
  10  * Technical Reference Manual)
  11  *
  12  * WARNING! The hardware described in this file is independent from the
  13  * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
  14  * correspondence between the two configurations.
  15  *
  16  * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
  17  * CHANGES TO vexpress-v2m-rs1.dtsi!
  18  */
  19
  20 / {
  21         aliases {
  22                 arm,v2m_timer = &v2m_timer01;
  23         };
  24
  25         motherboard {
  26                 compatible = "simple-bus";
  27                 arm,vexpress,site = <0>;
  28                 #address-cells = <2>; /* SMB chipselect number and offset */
  29                 #size-cells = <1>;
  30                 #interrupt-cells = <1>;
  31
  32                 flash@0,00000000 {
  33                         compatible = "arm,vexpress-flash", "cfi-flash";
  34                         reg = <0 0x00000000 0x04000000>,
  35                               <1 0x00000000 0x04000000>;
  36                         bank-width = <4>;
  37                 };
  38
  39                 psram@2,00000000 {
  40                         compatible = "arm,vexpress-psram", "mtd-ram";
  41                         reg = <2 0x00000000 0x02000000>;
  42                         bank-width = <4>;
  43                 };
  44
  45                 vram@3,00000000 {
  46                         compatible = "arm,vexpress-vram";
  47                         reg = <3 0x00000000 0x00800000>;
  48                 };
  49
  50                 ethernet@3,02000000 {
  51                         compatible = "smsc,lan9118", "smsc,lan9115";
  52                         reg = <3 0x02000000 0x10000>;
  53                         interrupts = <15>;
  54                         phy-mode = "mii";
  55                         reg-io-width = <4>;
  56                         smsc,irq-active-high;
  57                         smsc,irq-push-pull;
  58                         vdd33a-supply = <&v2m_fixed_3v3>;
  59                         vddvario-supply = <&v2m_fixed_3v3>;
  60                 };
  61
  62                 usb@3,03000000 {
  63                         compatible = "nxp,usb-isp1761";
  64                         reg = <3 0x03000000 0x20000>;
  65                         interrupts = <16>;
  66                         port1-otg;
  67                 };
  68
  69                 iofpga@7,00000000 {
  70                         compatible = "arm,amba-bus", "simple-bus";
  71                         #address-cells = <1>;
  72                         #size-cells = <1>;
  73                         ranges = <0 7 0 0x20000>;
  74
  75                         v2m_sysreg: sysreg@00000 {
  76                                 compatible = "arm,vexpress-sysreg";
  77                                 reg = <0x00000 0x1000>;
  78                                 gpio-controller;
  79                                 #gpio-cells = <2>;
  80                         };
  81
  82                         v2m_sysctl: sysctl@01000 {
  83                                 compatible = "arm,sp810", "arm,primecell";
  84                                 reg = <0x01000 0x1000>;
  85                                 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
  86                                 clock-names = "refclk", "timclk", "apb_pclk";
  87                                 #clock-cells = <1>;
  88                                 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
  89                         };
  90
  91                         /* PCI-E I2C bus */
  92                         v2m_i2c_pcie: i2c@02000 {
  93                                 compatible = "arm,versatile-i2c";
  94                                 reg = <0x02000 0x1000>;
  95
  96                                 #address-cells = <1>;
  97                                 #size-cells = <0>;
  98
  99                                 pcie-switch@60 {
 100                                         compatible = "idt,89hpes32h8";
 101                                         reg = <0x60>;
 102                                 };
 103                         };
 104
 105                         aaci@04000 {
 106                                 compatible = "arm,pl041", "arm,primecell";
 107                                 reg = <0x04000 0x1000>;
 108                                 interrupts = <11>;
 109                                 clocks = <&smbclk>;
 110                                 clock-names = "apb_pclk";
 111                         };
 112
 113                         mmci@05000 {
 114                                 compatible = "arm,pl180", "arm,primecell";
 115                                 reg = <0x05000 0x1000>;
 116                                 interrupts = <9 10>;
 117                                 cd-gpios = <&v2m_sysreg 0 0>;
 118                                 wp-gpios = <&v2m_sysreg 1 0>;
 119                                 max-frequency = <12000000>;
 120                                 vmmc-supply = <&v2m_fixed_3v3>;
 121                                 clocks = <&v2m_clk24mhz>, <&smbclk>;
 122                                 clock-names = "mclk", "apb_pclk";
 123                         };
 124
 125                         kmi@06000 {
 126                                 compatible = "arm,pl050", "arm,primecell";
 127                                 reg = <0x06000 0x1000>;
 128                                 interrupts = <12>;
 129                                 clocks = <&v2m_clk24mhz>, <&smbclk>;
 130                                 clock-names = "KMIREFCLK", "apb_pclk";
 131                         };
 132
 133                         kmi@07000 {
 134                                 compatible = "arm,pl050", "arm,primecell";
 135                                 reg = <0x07000 0x1000>;
 136                                 interrupts = <13>;
 137                                 clocks = <&v2m_clk24mhz>, <&smbclk>;
 138                                 clock-names = "KMIREFCLK", "apb_pclk";
 139                         };
 140
 141                         v2m_serial0: uart@09000 {
 142                                 compatible = "arm,pl011", "arm,primecell";
 143                                 reg = <0x09000 0x1000>;
 144                                 interrupts = <5>;
 145                                 clocks = <&v2m_oscclk2>, <&smbclk>;
 146                                 clock-names = "uartclk", "apb_pclk";
 147                         };
 148
 149                         v2m_serial1: uart@0a000 {
 150                                 compatible = "arm,pl011", "arm,primecell";
 151                                 reg = <0x0a000 0x1000>;
 152                                 interrupts = <6>;
 153                                 clocks = <&v2m_oscclk2>, <&smbclk>;
 154                                 clock-names = "uartclk", "apb_pclk";
 155                         };
 156
 157                         v2m_serial2: uart@0b000 {
 158                                 compatible = "arm,pl011", "arm,primecell";
 159                                 reg = <0x0b000 0x1000>;
 160                                 interrupts = <7>;
 161                                 clocks = <&v2m_oscclk2>, <&smbclk>;
 162                                 clock-names = "uartclk", "apb_pclk";
 163                         };
 164
 165                         v2m_serial3: uart@0c000 {
 166                                 compatible = "arm,pl011", "arm,primecell";
 167                                 reg = <0x0c000 0x1000>;
 168                                 interrupts = <8>;
 169                                 clocks = <&v2m_oscclk2>, <&smbclk>;
 170                                 clock-names = "uartclk", "apb_pclk";
 171                         };
 172
 173                         wdt@0f000 {
 174                                 compatible = "arm,sp805", "arm,primecell";
 175                                 reg = <0x0f000 0x1000>;
 176                                 interrupts = <0>;
 177                                 clocks = <&v2m_refclk32khz>, <&smbclk>;
 178                                 clock-names = "wdogclk", "apb_pclk";
 179                         };
 180
 181                         v2m_timer01: timer@11000 {
 182                                 compatible = "arm,sp804", "arm,primecell";
 183                                 reg = <0x11000 0x1000>;
 184                                 interrupts = <2>;
 185                                 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
 186                                 clock-names = "timclken1", "timclken2", "apb_pclk";
 187                         };
 188
 189                         v2m_timer23: timer@12000 {
 190                                 compatible = "arm,sp804", "arm,primecell";
 191                                 reg = <0x12000 0x1000>;
 192                                 interrupts = <3>;
 193                                 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
 194                                 clock-names = "timclken1", "timclken2", "apb_pclk";
 195                         };
 196
 197                         /* DVI I2C bus */
 198                         v2m_i2c_dvi: i2c@16000 {
 199                                 compatible = "arm,versatile-i2c";
 200                                 reg = <0x16000 0x1000>;
 201
 202                                 #address-cells = <1>;
 203                                 #size-cells = <0>;
 204
 205                                 dvi-transmitter@39 {
 206                                         compatible = "sil,sii9022-tpi", "sil,sii9022";
 207                                         reg = <0x39>;
 208                                 };
 209
 210                                 dvi-transmitter@60 {
 211                                         compatible = "sil,sii9022-cpi", "sil,sii9022";
 212                                         reg = <0x60>;
 213                                 };
 214                         };
 215
 216                         rtc@17000 {
 217                                 compatible = "arm,pl031", "arm,primecell";
 218                                 reg = <0x17000 0x1000>;
 219                                 interrupts = <4>;
 220                                 clocks = <&smbclk>;
 221                                 clock-names = "apb_pclk";
 222                         };
 223
 224                         compact-flash@1a000 {
 225                                 compatible = "arm,vexpress-cf", "ata-generic";
 226                                 reg = <0x1a000 0x100
 227                                        0x1a100 0xf00>;
 228                                 reg-shift = <2>;
 229                         };
 230
 231                         clcd@1f000 {
 232                                 compatible = "arm,pl111", "arm,primecell";
 233                                 reg = <0x1f000 0x1000>;
 234                                 interrupts = <14>;
 235                                 clocks = <&v2m_oscclk1>, <&smbclk>;
 236                                 clock-names = "clcdclk", "apb_pclk";
 237                         };
 238                 };
 239
 240                 v2m_fixed_3v3: fixedregulator@0 {
 241                         compatible = "regulator-fixed";
 242                         regulator-name = "3V3";
 243                         regulator-min-microvolt = <3300000>;
 244                         regulator-max-microvolt = <3300000>;
 245                         regulator-always-on;
 246                 };
 247
 248                 v2m_clk24mhz: clk24mhz {
 249                         compatible = "fixed-clock";
 250                         #clock-cells = <0>;
 251                         clock-frequency = <24000000>;
 252                         clock-output-names = "v2m:clk24mhz";
 253                 };
 254
 255                 v2m_refclk1mhz: refclk1mhz {
 256                         compatible = "fixed-clock";
 257                         #clock-cells = <0>;
 258                         clock-frequency = <1000000>;
 259                         clock-output-names = "v2m:refclk1mhz";
 260                 };
 261
 262                 v2m_refclk32khz: refclk32khz {
 263                         compatible = "fixed-clock";
 264                         #clock-cells = <0>;
 265                         clock-frequency = <32768>;
 266                         clock-output-names = "v2m:refclk32khz";
 267                 };
 268
 269                 mcc {
 270                         compatible = "arm,vexpress,config-bus";
 271                         arm,vexpress,config-bridge = <&v2m_sysreg>;
 272
 273                         osc@0 {
 274                                 /* MCC static memory clock */
 275                                 compatible = "arm,vexpress-osc";
 276                                 arm,vexpress-sysreg,func = <1 0>;
 277                                 freq-range = <25000000 60000000>;
 278                                 #clock-cells = <0>;
 279                                 clock-output-names = "v2m:oscclk0";
 280                         };
 281
 282                         v2m_oscclk1: osc@1 {
 283                                 /* CLCD clock */
 284                                 compatible = "arm,vexpress-osc";
 285                                 arm,vexpress-sysreg,func = <1 1>;
 286                                 freq-range = <23750000 63500000>;
 287                                 #clock-cells = <0>;
 288                                 clock-output-names = "v2m:oscclk1";
 289                         };
 290
 291                         v2m_oscclk2: osc@2 {
 292                                 /* IO FPGA peripheral clock */
 293                                 compatible = "arm,vexpress-osc";
 294                                 arm,vexpress-sysreg,func = <1 2>;
 295                                 freq-range = <24000000 24000000>;
 296                                 #clock-cells = <0>;
 297                                 clock-output-names = "v2m:oscclk2";
 298                         };
 299
 300                         volt@0 {
 301                                 /* Logic level voltage */
 302                                 compatible = "arm,vexpress-volt";
 303                                 arm,vexpress-sysreg,func = <2 0>;
 304                                 regulator-name = "VIO";
 305                                 regulator-always-on;
 306                                 label = "VIO";
 307                         };
 308
 309                         temp@0 {
 310                                 /* MCC internal operating temperature */
 311                                 compatible = "arm,vexpress-temp";
 312                                 arm,vexpress-sysreg,func = <4 0>;
 313                                 label = "MCC";
 314                         };
 315
 316                         reset@0 {
 317                                 compatible = "arm,vexpress-reset";
 318                                 arm,vexpress-sysreg,func = <5 0>;
 319                         };
 320
 321                         muxfpga@0 {
 322                                 compatible = "arm,vexpress-muxfpga";
 323                                 arm,vexpress-sysreg,func = <7 0>;
 324                         };
 325
 326                         shutdown@0 {
 327                                 compatible = "arm,vexpress-shutdown";
 328                                 arm,vexpress-sysreg,func = <8 0>;
 329                         };
 330
 331                         reboot@0 {
 332                                 compatible = "arm,vexpress-reboot";
 333                                 arm,vexpress-sysreg,func = <9 0>;
 334                         };
 335
 336                         dvimode@0 {
 337                                 compatible = "arm,vexpress-dvimode";
 338                                 arm,vexpress-sysreg,func = <11 0>;
 339                         };
 340                 };
 341         };
 342 };