1 /include/ "skeleton.dtsi"
4 compatible = "nvidia,tegra30";
5 interrupt-parent = <&intc>;
7 cache-controller@50043000 {
8 compatible = "arm,pl310-cache";
9 reg = <0x50043000 0x1000>;
10 arm,data-latency = <6 6 2>;
11 arm,tag-latency = <5 5 2>;
16 intc: interrupt-controller {
17 compatible = "arm,cortex-a9-gic";
18 reg = <0x50041000 0x1000
21 #interrupt-cells = <3>;
25 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
26 reg = <0x6000a000 0x1400>;
27 interrupts = <0 104 0x04
62 compatible = "nvidia,tegra30-ahb";
63 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
67 compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
68 reg = <0x6000d000 0x1000>;
69 interrupts = <0 32 0x04
79 #interrupt-cells = <2>;
84 compatible = "nvidia,tegra30-pinmux";
85 reg = <0x70000868 0xd4 /* Pad control registers */
86 0x70003000 0x3e4>; /* Mux registers */
90 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
91 reg = <0x70006000 0x40>;
93 interrupts = <0 36 0x04>;
98 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
99 reg = <0x70006040 0x40>;
101 interrupts = <0 37 0x04>;
106 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
107 reg = <0x70006200 0x100>;
109 interrupts = <0 46 0x04>;
114 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
115 reg = <0x70006300 0x100>;
117 interrupts = <0 90 0x04>;
122 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
123 reg = <0x70006400 0x100>;
125 interrupts = <0 91 0x04>;
130 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
131 reg = <0x7000a000 0x100>;
136 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
137 reg = <0x7000c000 0x100>;
138 interrupts = <0 38 0x04>;
139 #address-cells = <1>;
145 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
146 reg = <0x7000c400 0x100>;
147 interrupts = <0 84 0x04>;
148 #address-cells = <1>;
154 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
155 reg = <0x7000c500 0x100>;
156 interrupts = <0 92 0x04>;
157 #address-cells = <1>;
163 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
164 reg = <0x7000c700 0x100>;
165 interrupts = <0 120 0x04>;
166 #address-cells = <1>;
172 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
173 reg = <0x7000d000 0x100>;
174 interrupts = <0 53 0x04>;
175 #address-cells = <1>;
181 compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
182 reg = <0x7000e400 0x400>;
186 compatible = "nvidia,tegra30-mc";
187 reg = <0x7000f000 0x010
191 interrupts = <0 77 0x04>;
195 compatible = "nvidia,tegra30-smmu";
196 reg = <0x7000f010 0x02c
199 nvidia,#asids = <4>; /* # of ASIDs */
200 dma-window = <0 0x40000000>; /* IOVA start & length */
205 compatible = "nvidia,tegra30-ahub";
206 reg = <0x70080000 0x200
208 interrupts = <0 103 0x04>;
209 nvidia,dma-request-selector = <&apbdma 1>;
212 #address-cells = <1>;
215 tegra_i2s0: i2s@70080300 {
216 compatible = "nvidia,tegra30-i2s";
217 reg = <0x70080300 0x100>;
218 nvidia,ahub-cif-ids = <4 4>;
222 tegra_i2s1: i2s@70080400 {
223 compatible = "nvidia,tegra30-i2s";
224 reg = <0x70080400 0x100>;
225 nvidia,ahub-cif-ids = <5 5>;
229 tegra_i2s2: i2s@70080500 {
230 compatible = "nvidia,tegra30-i2s";
231 reg = <0x70080500 0x100>;
232 nvidia,ahub-cif-ids = <6 6>;
236 tegra_i2s3: i2s@70080600 {
237 compatible = "nvidia,tegra30-i2s";
238 reg = <0x70080600 0x100>;
239 nvidia,ahub-cif-ids = <7 7>;
243 tegra_i2s4: i2s@70080700 {
244 compatible = "nvidia,tegra30-i2s";
245 reg = <0x70080700 0x100>;
246 nvidia,ahub-cif-ids = <8 8>;
252 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
253 reg = <0x78000000 0x200>;
254 interrupts = <0 14 0x04>;
259 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
260 reg = <0x78000200 0x200>;
261 interrupts = <0 15 0x04>;
266 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
267 reg = <0x78000400 0x200>;
268 interrupts = <0 19 0x04>;
273 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
274 reg = <0x78000600 0x200>;
275 interrupts = <0 31 0x04>;
280 compatible = "arm,cortex-a9-pmu";
281 interrupts = <0 144 0x04