arch/arm/boot/dts/tegra20-colibri.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include "tegra20.dtsi"
   3
   4 / {
   5         model = "Toradex Colibri T20 256/512 MB";
   6         compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
   7
   8         aliases {
   9                 rtc0 = "/i2c@7000d000/tps6586x@34";
  10                 rtc1 = "/rtc@7000e000";
  11         };
  12
  13         memory@0 {
  14                 /*
  15                  * Set memory to 256 MB to be safe as this could be used on
  16                  * 256 or 512 MB module. It is expected from bootloader
  17                  * to fix this up for 512 MB version.
  18                  */
  19                 reg = <0x00000000 0x10000000>;
  20         };
  21
  22         host1x@50000000 {
  23                 hdmi@54280000 {
  24                         vdd-supply = <&hdmi_vdd_reg>;
  25                         pll-supply = <&hdmi_pll_reg>;
  26
  27                         nvidia,ddc-i2c-bus = <&i2c_ddc>;
  28                         nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  29                                 GPIO_ACTIVE_HIGH>;
  30                 };
  31         };
  32
  33         pinmux@70000014 {
  34                 pinctrl-names = "default";
  35                 pinctrl-0 = <&state_default>;
  36
  37                 state_default: pinmux {
  38                         audio_refclk {
  39                                 nvidia,pins = "cdev1";
  40                                 nvidia,function = "plla_out";
  41                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  42                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  43                         };
  44                         crt {
  45                                 nvidia,pins = "crtp";
  46                                 nvidia,function = "crt";
  47                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  48                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  49                         };
  50                         dap3 {
  51                                 nvidia,pins = "dap3";
  52                                 nvidia,function = "dap3";
  53                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  54                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  55                         };
  56                         displaya {
  57                                 nvidia,pins = "ld0", "ld1", "ld2", "ld3",
  58                                         "ld4", "ld5", "ld6", "ld7", "ld8",
  59                                         "ld9", "ld10", "ld11", "ld12", "ld13",
  60                                         "ld14", "ld15", "ld16", "ld17",
  61                                         "lhs", "lpw0", "lpw2", "lsc0",
  62                                         "lsc1", "lsck", "lsda", "lspi", "lvs";
  63                                 nvidia,function = "displaya";
  64                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  65                         };
  66                         gpio_dte {
  67                                 nvidia,pins = "dte";
  68                                 nvidia,function = "rsvd1";
  69                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  70                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  71                         };
  72                         gpio_gmi {
  73                                 nvidia,pins = "ata", "atc", "atd", "ate",
  74                                         "dap1", "dap2", "dap4", "gpu", "irrx",
  75                                         "irtx", "spia", "spib", "spic";
  76                                 nvidia,function = "gmi";
  77                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  78                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  79                         };
  80                         gpio_pta {
  81                                 nvidia,pins = "pta";
  82                                 nvidia,function = "rsvd4";
  83                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  84                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  85                         };
  86                         gpio_uac {
  87                                 nvidia,pins = "uac";
  88                                 nvidia,function = "rsvd2";
  89                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  90                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
  91                         };
  92                         hdint {
  93                                 nvidia,pins = "hdint";
  94                                 nvidia,function = "hdmi";
  95                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
  96                         };
  97                         i2c1 {
  98                                 nvidia,pins = "rm";
  99                                 nvidia,function = "i2c1";
 100                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 101                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 102                         };
 103                         i2c3 {
 104                                 nvidia,pins = "dtf";
 105                                 nvidia,function = "i2c3";
 106                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 107                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 108                         };
 109                         i2cddc {
 110                                 nvidia,pins = "ddc";
 111                                 nvidia,function = "i2c2";
 112                                 nvidia,pull = <TEGRA_PIN_PULL_UP>;
 113                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 114                         };
 115                         i2cp {
 116                                 nvidia,pins = "i2cp";
 117                                 nvidia,function = "i2cp";
 118                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 119                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 120                         };
 121                         irda {
 122                                 nvidia,pins = "uad";
 123                                 nvidia,function = "irda";
 124                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 125                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 126                         };
 127                         nand {
 128                                 nvidia,pins = "kbca", "kbcc", "kbcd",
 129                                         "kbce", "kbcf";
 130                                 nvidia,function = "nand";
 131                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 132                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 133                         };
 134                         owc {
 135                                 nvidia,pins = "owc";
 136                                 nvidia,function = "owr";
 137                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 138                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 139                         };
 140                         pmc {
 141                                 nvidia,pins = "pmc";
 142                                 nvidia,function = "pwr_on";
 143                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 144                         };
 145                         pwm {
 146                                 nvidia,pins = "sdb", "sdc", "sdd";
 147                                 nvidia,function = "pwm";
 148                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 149                         };
 150                         sdio4 {
 151                                 nvidia,pins = "atb", "gma", "gme";
 152                                 nvidia,function = "sdio4";
 153                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 154                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 155                         };
 156                         spi1 {
 157                                 nvidia,pins = "spid", "spie", "spif";
 158                                 nvidia,function = "spi1";
 159                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 160                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 161                         };
 162                         spi4 {
 163                                 nvidia,pins = "slxa", "slxc", "slxd", "slxk";
 164                                 nvidia,function = "spi4";
 165                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 166                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 167                         };
 168                         uarta {
 169                                 nvidia,pins = "sdio1";
 170                                 nvidia,function = "uarta";
 171                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 172                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 173                         };
 174                         uartd {
 175                                 nvidia,pins = "gmc";
 176                                 nvidia,function = "uartd";
 177                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 178                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 179                         };
 180                         ulpi {
 181                                 nvidia,pins = "uaa", "uab", "uda";
 182                                 nvidia,function = "ulpi";
 183                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 184                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 185                         };
 186                         ulpi_refclk {
 187                                 nvidia,pins = "cdev2";
 188                                 nvidia,function = "pllp_out4";
 189                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 190                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 191                         };
 192                         usb_gpio {
 193                                 nvidia,pins = "spig", "spih";
 194                                 nvidia,function = "spi2_alt";
 195                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 196                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
 197                         };
 198                         vi {
 199                                 nvidia,pins = "dta", "dtb", "dtc", "dtd";
 200                                 nvidia,function = "vi";
 201                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 202                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 203                         };
 204                         vi_sc {
 205                                 nvidia,pins = "csus";
 206                                 nvidia,function = "vi_sensor_clk";
 207                                 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 208                                 nvidia,tristate = <TEGRA_PIN_ENABLE>;
 209                         };
 210                 };
 211         };
 212
 213         ac97: ac97@70002000 {
 214                 status = "okay";
 215                 nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
 216                         GPIO_ACTIVE_HIGH>;
 217                 nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
 218                         GPIO_ACTIVE_HIGH>;
 219         };
 220
 221         /*
 222          * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
 223          * board)
 224          */
 225         i2c@7000c000 {
 226                 clock-frequency = <400000>;
 227         };
 228
 229         /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */
 230         i2c_ddc: i2c@7000c400 {
 231                 clock-frequency = <10000>;
 232         };
 233
 234         /* GEN2_I2C: unused */
 235
 236         /* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */
 237
 238         /* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */
 239         i2c@7000d000 {
 240                 status = "okay";
 241                 clock-frequency = <100000>;
 242
 243                 pmic: tps6586x@34 {
 244                         compatible = "ti,tps6586x";
 245                         reg = <0x34>;
 246                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 247
 248                         ti,system-power-controller;
 249
 250                         #gpio-cells = <2>;
 251                         gpio-controller;
 252
 253                         sys-supply = <&vdd_3v3_reg>;
 254                         vin-sm0-supply = <&sys_reg>;
 255                         vin-sm1-supply = <&sys_reg>;
 256                         vin-sm2-supply = <&sys_reg>;
 257                         vinldo01-supply = <&sm2_reg>;
 258                         vinldo23-supply = <&vdd_3v3_reg>;
 259                         vinldo4-supply = <&vdd_3v3_reg>;
 260                         vinldo678-supply = <&vdd_3v3_reg>;
 261                         vinldo9-supply = <&vdd_3v3_reg>;
 262
 263                         regulators {
 264                                 #address-cells = <1>;
 265                                 #size-cells = <0>;
 266
 267                                 sys_reg: regulator@0 {
 268                                         reg = <0>;
 269                                         regulator-compatible = "sys";
 270                                         regulator-name = "vdd_sys";
 271                                         regulator-always-on;
 272                                 };
 273
 274                                 regulator@1 {
 275                                         reg = <1>;
 276                                         regulator-compatible = "sm0";
 277                                         regulator-name = "vdd_sm0,vdd_core";
 278                                         regulator-min-microvolt = <1200000>;
 279                                         regulator-max-microvolt = <1200000>;
 280                                         regulator-always-on;
 281                                 };
 282
 283                                 regulator@2 {
 284                                         reg = <2>;
 285                                         regulator-compatible = "sm1";
 286                                         regulator-name = "vdd_sm1,vdd_cpu";
 287                                         regulator-min-microvolt = <1000000>;
 288                                         regulator-max-microvolt = <1000000>;
 289                                         regulator-always-on;
 290                                 };
 291
 292                                 sm2_reg: regulator@3 {
 293                                         reg = <3>;
 294                                         regulator-compatible = "sm2";
 295                                         regulator-name = "vdd_sm2,vin_ldo*";
 296                                         regulator-min-microvolt = <1800000>;
 297                                         regulator-max-microvolt = <1800000>;
 298                                         regulator-always-on;
 299                                 };
 300
 301                                 /* LDO0 is not connected to anything */
 302
 303                                 regulator@5 {
 304                                         reg = <5>;
 305                                         regulator-compatible = "ldo1";
 306                                         regulator-name = "vdd_ldo1,avdd_pll*";
 307                                         regulator-min-microvolt = <1100000>;
 308                                         regulator-max-microvolt = <1100000>;
 309                                         regulator-always-on;
 310                                 };
 311
 312                                 regulator@6 {
 313                                         reg = <6>;
 314                                         regulator-compatible = "ldo2";
 315                                         regulator-name = "vdd_ldo2,vdd_rtc";
 316                                         regulator-min-microvolt = <1200000>;
 317                                         regulator-max-microvolt = <1200000>;
 318                                 };
 319
 320                                 /* LDO3 is not connected to anything */
 321
 322                                 regulator@8 {
 323                                         reg = <8>;
 324                                         regulator-compatible = "ldo4";
 325                                         regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
 326                                         regulator-min-microvolt = <1800000>;
 327                                         regulator-max-microvolt = <1800000>;
 328                                         regulator-always-on;
 329                                 };
 330
 331                                 ldo5_reg: regulator@9 {
 332                                         reg = <9>;
 333                                         regulator-compatible = "ldo5";
 334                                         regulator-name = "vdd_ldo5,vdd_fuse";
 335                                         regulator-min-microvolt = <3300000>;
 336                                         regulator-max-microvolt = <3300000>;
 337                                         regulator-always-on;
 338                                 };
 339
 340                                 regulator@10 {
 341                                         reg = <10>;
 342                                         regulator-compatible = "ldo6";
 343                                         regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
 344                                         regulator-min-microvolt = <2850000>;
 345                                         regulator-max-microvolt = <2850000>;
 346                                 };
 347
 348                                 hdmi_vdd_reg: regulator@11 {
 349                                         reg = <11>;
 350                                         regulator-compatible = "ldo7";
 351                                         regulator-name = "vdd_ldo7,avdd_hdmi";
 352                                         regulator-min-microvolt = <3300000>;
 353                                         regulator-max-microvolt = <3300000>;
 354                                 };
 355
 356                                 hdmi_pll_reg: regulator@12 {
 357                                         reg = <12>;
 358                                         regulator-compatible = "ldo8";
 359                                         regulator-name = "vdd_ldo8,avdd_hdmi_pll";
 360                                         regulator-min-microvolt = <1800000>;
 361                                         regulator-max-microvolt = <1800000>;
 362                                 };
 363
 364                                 regulator@13 {
 365                                         reg = <13>;
 366                                         regulator-compatible = "ldo9";
 367                                         regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
 368                                         regulator-min-microvolt = <2850000>;
 369                                         regulator-max-microvolt = <2850000>;
 370                                         regulator-always-on;
 371                                 };
 372
 373                                 regulator@14 {
 374                                         reg = <14>;
 375                                         regulator-compatible = "ldo_rtc";
 376                                         regulator-name = "vdd_rtc_out,vdd_cell";
 377                                         regulator-min-microvolt = <3300000>;
 378                                         regulator-max-microvolt = <3300000>;
 379                                         regulator-always-on;
 380                                 };
 381                         };
 382                 };
 383
 384                 temperature-sensor@4c {
 385                         compatible = "national,lm95245";
 386                         reg = <0x4c>;
 387                 };
 388         };
 389
 390         pmc@7000e400 {
 391                 nvidia,suspend-mode = <1>;
 392                 nvidia,cpu-pwr-good-time = <5000>;
 393                 nvidia,cpu-pwr-off-time = <5000>;
 394                 nvidia,core-pwr-good-time = <3845 3845>;
 395                 nvidia,core-pwr-off-time = <3875>;
 396                 nvidia,sys-clock-req-active-high;
 397         };
 398
 399         memory-controller@7000f400 {
 400                 emc-table@83250 {
 401                         reg = <83250>;
 402                         compatible = "nvidia,tegra20-emc-table";
 403                         clock-frequency = <83250>;
 404                         nvidia,emc-registers =   <0x00000005 0x00000011
 405                                 0x00000004 0x00000002 0x00000004 0x00000004
 406                                 0x00000001 0x0000000a 0x00000002 0x00000002
 407                                 0x00000001 0x00000001 0x00000003 0x00000004
 408                                 0x00000003 0x00000009 0x0000000c 0x0000025f
 409                                 0x00000000 0x00000003 0x00000003 0x00000002
 410                                 0x00000002 0x00000001 0x00000008 0x000000c8
 411                                 0x00000003 0x00000005 0x00000003 0x0000000c
 412                                 0x00000002 0x00000000 0x00000000 0x00000002
 413                                 0x00000000 0x00000000 0x00000083 0x00520006
 414                                 0x00000010 0x00000008 0x00000000 0x00000000
 415                                 0x00000000 0x00000000 0x00000000 0x00000000>;
 416                 };
 417                 emc-table@133200 {
 418                         reg = <133200>;
 419                         compatible = "nvidia,tegra20-emc-table";
 420                         clock-frequency = <133200>;
 421                         nvidia,emc-registers =   <0x00000008 0x00000019
 422                                 0x00000006 0x00000002 0x00000004 0x00000004
 423                                 0x00000001 0x0000000a 0x00000002 0x00000002
 424                                 0x00000002 0x00000001 0x00000003 0x00000004
 425                                 0x00000003 0x00000009 0x0000000c 0x0000039f
 426                                 0x00000000 0x00000003 0x00000003 0x00000002
 427                                 0x00000002 0x00000001 0x00000008 0x000000c8
 428                                 0x00000003 0x00000007 0x00000003 0x0000000c
 429                                 0x00000002 0x00000000 0x00000000 0x00000002
 430                                 0x00000000 0x00000000 0x00000083 0x00510006
 431                                 0x00000010 0x00000008 0x00000000 0x00000000
 432                                 0x00000000 0x00000000 0x00000000 0x00000000>;
 433                 };
 434                 emc-table@166500 {
 435                         reg = <166500>;
 436                         compatible = "nvidia,tegra20-emc-table";
 437                         clock-frequency = <166500>;
 438                         nvidia,emc-registers =   <0x0000000a 0x00000021
 439                                 0x00000008 0x00000003 0x00000004 0x00000004
 440                                 0x00000002 0x0000000a 0x00000003 0x00000003
 441                                 0x00000002 0x00000001 0x00000003 0x00000004
 442                                 0x00000003 0x00000009 0x0000000c 0x000004df
 443                                 0x00000000 0x00000003 0x00000003 0x00000003
 444                                 0x00000003 0x00000001 0x00000009 0x000000c8
 445                                 0x00000003 0x00000009 0x00000004 0x0000000c
 446                                 0x00000002 0x00000000 0x00000000 0x00000002
 447                                 0x00000000 0x00000000 0x00000083 0x004f0006
 448                                 0x00000010 0x00000008 0x00000000 0x00000000
 449                                 0x00000000 0x00000000 0x00000000 0x00000000>;
 450                 };
 451                 emc-table@333000 {
 452                         reg = <333000>;
 453                         compatible = "nvidia,tegra20-emc-table";
 454                         clock-frequency = <333000>;
 455                         nvidia,emc-registers =   <0x00000014 0x00000041
 456                                 0x0000000f 0x00000005 0x00000004 0x00000005
 457                                 0x00000003 0x0000000a 0x00000005 0x00000005
 458                                 0x00000004 0x00000001 0x00000003 0x00000004
 459                                 0x00000003 0x00000009 0x0000000c 0x000009ff
 460                                 0x00000000 0x00000003 0x00000003 0x00000005
 461                                 0x00000005 0x00000001 0x0000000e 0x000000c8
 462                                 0x00000003 0x00000011 0x00000006 0x0000000c
 463                                 0x00000002 0x00000000 0x00000000 0x00000002
 464                                 0x00000000 0x00000000 0x00000083 0x00380006
 465                                 0x00000010 0x00000008 0x00000000 0x00000000
 466                                 0x00000000 0x00000000 0x00000000 0x00000000>;
 467                 };
 468         };
 469
 470         usb@c5004000 {
 471                 status = "okay";
 472                 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
 473                         GPIO_ACTIVE_LOW>;
 474         };
 475
 476         usb-phy@c5004000 {
 477                 status = "okay";
 478                 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
 479                         GPIO_ACTIVE_LOW>;
 480         };
 481
 482         sdhci@c8000600 {
 483                 cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
 484         };
 485
 486         clocks {
 487                 compatible = "simple-bus";
 488                 #address-cells = <1>;
 489                 #size-cells = <0>;
 490
 491                 clk32k_in: clock@0 {
 492                         compatible = "fixed-clock";
 493                         reg = <0>;
 494                         #clock-cells = <0>;
 495                         clock-frequency = <32768>;
 496                 };
 497         };
 498
 499         regulators {
 500                 compatible = "simple-bus";
 501                 #address-cells = <1>;
 502                 #size-cells = <0>;
 503
 504                 vdd_3v3_reg: regulator@100 {
 505                         compatible = "regulator-fixed";
 506                         reg = <100>;
 507                         regulator-name = "vdd_3v3";
 508                         regulator-min-microvolt = <3300000>;
 509                         regulator-max-microvolt = <3300000>;
 510                         regulator-always-on;
 511                 };
 512
 513                 regulator@101 {
 514                         compatible = "regulator-fixed";
 515                         reg = <101>;
 516                         regulator-name = "internal_usb";
 517                         regulator-min-microvolt = <5000000>;
 518                         regulator-max-microvolt = <5000000>;
 519                         enable-active-high;
 520                         regulator-boot-on;
 521                         regulator-always-on;
 522                         gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
 523                 };
 524         };
 525
 526         sound {
 527                 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
 528                                  "nvidia,tegra-audio-wm9712";
 529                 nvidia,model = "Colibri T20 AC97 Audio";
 530
 531                 nvidia,audio-routing =
 532                         "Headphone", "HPOUTL",
 533                         "Headphone", "HPOUTR",
 534                         "LineIn", "LINEINL",
 535                         "LineIn", "LINEINR",
 536                         "Mic", "MIC1";
 537
 538                 nvidia,ac97-controller = <&ac97>;
 539
 540                 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
 541                          <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
 542                          <&tegra_car TEGRA20_CLK_CDEV1>;
 543                 clock-names = "pll_a", "pll_a_out0", "mclk";
 544         };
 545 };