arch/arm/boot/dts/tegra124.dtsi

   1 #include <dt-bindings/clock/tegra124-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5
   6 #include "skeleton.dtsi"
   7
   8 / {
   9         compatible = "nvidia,tegra124";
  10         interrupt-parent = <&gic>;
  11
  12         gic: interrupt-controller@50041000 {
  13                 compatible = "arm,cortex-a15-gic";
  14                 #interrupt-cells = <3>;
  15                 interrupt-controller;
  16                 reg = <0x50041000 0x1000>,
  17                       <0x50042000 0x1000>,
  18                       <0x50044000 0x2000>,
  19                       <0x50046000 0x2000>;
  20                 interrupts = <GIC_PPI 9
  21                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  22         };
  23
  24         timer@60005000 {
  25                 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
  26                 reg = <0x60005000 0x400>;
  27                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  28                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  29                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
  30                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
  31                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
  32                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
  33                 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
  34         };
  35
  36         tegra_car: clock@60006000 {
  37                 compatible = "nvidia,tegra124-car";
  38                 reg = <0x60006000 0x1000>;
  39                 #clock-cells = <1>;
  40                 #reset-cells = <1>;
  41         };
  42
  43         gpio: gpio@6000d000 {
  44                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
  45                 reg = <0x6000d000 0x1000>;
  46                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
  47                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
  48                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
  49                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
  50                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
  51                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
  52                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
  53                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
  54                 #gpio-cells = <2>;
  55                 gpio-controller;
  56                 #interrupt-cells = <2>;
  57                 interrupt-controller;
  58         };
  59
  60         apbdma: dma@60020000 {
  61                 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
  62                 reg = <0x60020000 0x1400>;
  63                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
  64                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
  65                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
  66                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
  67                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
  68                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
  69                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
  70                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
  71                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
  72                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
  73                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
  74                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
  75                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
  76                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
  77                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
  78                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
  79                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
  80                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
  82                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  83                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
  84                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
  85                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
  86                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
  87                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
  88                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
  89                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
  90                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
  91                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
  92                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
  93                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
  94                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
  95                 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
  96                 resets = <&tegra_car 34>;
  97                 reset-names = "dma";
  98                 #dma-cells = <1>;
  99         };
 100
 101         pinmux: pinmux@70000868 {
 102                 compatible = "nvidia,tegra124-pinmux";
 103                 reg = <0x70000868 0x164>,       /* Pad control registers */
 104                       <0x70003000 0x434>;       /* Mux registers */
 105         };
 106
 107         /*
 108          * There are two serial driver i.e. 8250 based simple serial
 109          * driver and APB DMA based serial driver for higher baudrate
 110          * and performace. To enable the 8250 based driver, the compatible
 111          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
 112          * the APB DMA based serial driver, the comptible is
 113          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
 114          */
 115         serial@70006000 {
 116                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 117                 reg = <0x70006000 0x40>;
 118                 reg-shift = <2>;
 119                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 120                 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
 121                 resets = <&tegra_car 6>;
 122                 reset-names = "serial";
 123                 dmas = <&apbdma 8>, <&apbdma 8>;
 124                 dma-names = "rx", "tx";
 125                 status = "disabled";
 126         };
 127
 128         serial@70006040 {
 129                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 130                 reg = <0x70006040 0x40>;
 131                 reg-shift = <2>;
 132                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 133                 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
 134                 resets = <&tegra_car 7>;
 135                 reset-names = "serial";
 136                 dmas = <&apbdma 9>, <&apbdma 9>;
 137                 dma-names = "rx", "tx";
 138                 status = "disabled";
 139         };
 140
 141         serial@70006200 {
 142                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 143                 reg = <0x70006200 0x40>;
 144                 reg-shift = <2>;
 145                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 146                 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
 147                 resets = <&tegra_car 55>;
 148                 reset-names = "serial";
 149                 dmas = <&apbdma 10>, <&apbdma 10>;
 150                 dma-names = "rx", "tx";
 151                 status = "disabled";
 152         };
 153
 154         serial@70006300 {
 155                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
 156                 reg = <0x70006300 0x40>;
 157                 reg-shift = <2>;
 158                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 159                 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
 160                 resets = <&tegra_car 65>;
 161                 reset-names = "serial";
 162                 dmas = <&apbdma 19>, <&apbdma 19>;
 163                 dma-names = "rx", "tx";
 164                 status = "disabled";
 165         };
 166
 167         pwm@7000a000 {
 168                 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
 169                 reg = <0x7000a000 0x100>;
 170                 #pwm-cells = <2>;
 171                 clocks = <&tegra_car TEGRA124_CLK_PWM>;
 172                 resets = <&tegra_car 17>;
 173                 reset-names = "pwm";
 174                 status = "disabled";
 175         };
 176
 177         i2c@7000c000 {
 178                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 179                 reg = <0x7000c000 0x100>;
 180                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 181                 #address-cells = <1>;
 182                 #size-cells = <0>;
 183                 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
 184                 clock-names = "div-clk";
 185                 resets = <&tegra_car 12>;
 186                 reset-names = "i2c";
 187                 dmas = <&apbdma 21>, <&apbdma 21>;
 188                 dma-names = "rx", "tx";
 189                 status = "disabled";
 190         };
 191
 192         i2c@7000c400 {
 193                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 194                 reg = <0x7000c400 0x100>;
 195                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 196                 #address-cells = <1>;
 197                 #size-cells = <0>;
 198                 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
 199                 clock-names = "div-clk";
 200                 resets = <&tegra_car 54>;
 201                 reset-names = "i2c";
 202                 dmas = <&apbdma 22>, <&apbdma 22>;
 203                 dma-names = "rx", "tx";
 204                 status = "disabled";
 205         };
 206
 207         i2c@7000c500 {
 208                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 209                 reg = <0x7000c500 0x100>;
 210                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 211                 #address-cells = <1>;
 212                 #size-cells = <0>;
 213                 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
 214                 clock-names = "div-clk";
 215                 resets = <&tegra_car 67>;
 216                 reset-names = "i2c";
 217                 dmas = <&apbdma 23>, <&apbdma 23>;
 218                 dma-names = "rx", "tx";
 219                 status = "disabled";
 220         };
 221
 222         i2c@7000c700 {
 223                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 224                 reg = <0x7000c700 0x100>;
 225                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 226                 #address-cells = <1>;
 227                 #size-cells = <0>;
 228                 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
 229                 clock-names = "div-clk";
 230                 resets = <&tegra_car 103>;
 231                 reset-names = "i2c";
 232                 dmas = <&apbdma 26>, <&apbdma 26>;
 233                 dma-names = "rx", "tx";
 234                 status = "disabled";
 235         };
 236
 237         i2c@7000d000 {
 238                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 239                 reg = <0x7000d000 0x100>;
 240                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 241                 #address-cells = <1>;
 242                 #size-cells = <0>;
 243                 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
 244                 clock-names = "div-clk";
 245                 resets = <&tegra_car 47>;
 246                 reset-names = "i2c";
 247                 dmas = <&apbdma 24>, <&apbdma 24>;
 248                 dma-names = "rx", "tx";
 249                 status = "disabled";
 250         };
 251
 252         i2c@7000d100 {
 253                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
 254                 reg = <0x7000d100 0x100>;
 255                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 256                 #address-cells = <1>;
 257                 #size-cells = <0>;
 258                 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
 259                 clock-names = "div-clk";
 260                 resets = <&tegra_car 166>;
 261                 reset-names = "i2c";
 262                 dmas = <&apbdma 30>, <&apbdma 30>;
 263                 dma-names = "rx", "tx";
 264                 status = "disabled";
 265         };
 266
 267         spi@7000d400 {
 268                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 269                 reg = <0x7000d400 0x200>;
 270                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 271                 #address-cells = <1>;
 272                 #size-cells = <0>;
 273                 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
 274                 clock-names = "spi";
 275                 resets = <&tegra_car 41>;
 276                 reset-names = "spi";
 277                 dmas = <&apbdma 15>, <&apbdma 15>;
 278                 dma-names = "rx", "tx";
 279                 status = "disabled";
 280         };
 281
 282         spi@7000d600 {
 283                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 284                 reg = <0x7000d600 0x200>;
 285                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 286                 #address-cells = <1>;
 287                 #size-cells = <0>;
 288                 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
 289                 clock-names = "spi";
 290                 resets = <&tegra_car 44>;
 291                 reset-names = "spi";
 292                 dmas = <&apbdma 16>, <&apbdma 16>;
 293                 dma-names = "rx", "tx";
 294                 status = "disabled";
 295         };
 296
 297         spi@7000d800 {
 298                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 299                 reg = <0x7000d800 0x200>;
 300                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 301                 #address-cells = <1>;
 302                 #size-cells = <0>;
 303                 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
 304                 clock-names = "spi";
 305                 resets = <&tegra_car 46>;
 306                 reset-names = "spi";
 307                 dmas = <&apbdma 17>, <&apbdma 17>;
 308                 dma-names = "rx", "tx";
 309                 status = "disabled";
 310         };
 311
 312         spi@7000da00 {
 313                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 314                 reg = <0x7000da00 0x200>;
 315                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 316                 #address-cells = <1>;
 317                 #size-cells = <0>;
 318                 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
 319                 clock-names = "spi";
 320                 resets = <&tegra_car 68>;
 321                 reset-names = "spi";
 322                 dmas = <&apbdma 18>, <&apbdma 18>;
 323                 dma-names = "rx", "tx";
 324                 status = "disabled";
 325         };
 326
 327         spi@7000dc00 {
 328                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 329                 reg = <0x7000dc00 0x200>;
 330                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 331                 #address-cells = <1>;
 332                 #size-cells = <0>;
 333                 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
 334                 clock-names = "spi";
 335                 resets = <&tegra_car 104>;
 336                 reset-names = "spi";
 337                 dmas = <&apbdma 27>, <&apbdma 27>;
 338                 dma-names = "rx", "tx";
 339                 status = "disabled";
 340         };
 341
 342         spi@7000de00 {
 343                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
 344                 reg = <0x7000de00 0x200>;
 345                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 346                 #address-cells = <1>;
 347                 #size-cells = <0>;
 348                 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
 349                 clock-names = "spi";
 350                 resets = <&tegra_car 105>;
 351                 reset-names = "spi";
 352                 dmas = <&apbdma 28>, <&apbdma 28>;
 353                 dma-names = "rx", "tx";
 354                 status = "disabled";
 355         };
 356
 357         rtc@7000e000 {
 358                 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
 359                 reg = <0x7000e000 0x100>;
 360                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 361                 clocks = <&tegra_car TEGRA124_CLK_RTC>;
 362         };
 363
 364         pmc@7000e400 {
 365                 compatible = "nvidia,tegra124-pmc";
 366                 reg = <0x7000e400 0x400>;
 367                 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
 368                 clock-names = "pclk", "clk32k_in";
 369         };
 370
 371         sdhci@700b0000 {
 372                 compatible = "nvidia,tegra124-sdhci";
 373                 reg = <0x700b0000 0x200>;
 374                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 375                 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
 376                 resets = <&tegra_car 14>;
 377                 reset-names = "sdhci";
 378                 status = "disable";
 379         };
 380
 381         sdhci@700b0200 {
 382                 compatible = "nvidia,tegra124-sdhci";
 383                 reg = <0x700b0200 0x200>;
 384                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 385                 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
 386                 resets = <&tegra_car 9>;
 387                 reset-names = "sdhci";
 388                 status = "disable";
 389         };
 390
 391         sdhci@700b0400 {
 392                 compatible = "nvidia,tegra124-sdhci";
 393                 reg = <0x700b0400 0x200>;
 394                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 395                 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
 396                 resets = <&tegra_car 69>;
 397                 reset-names = "sdhci";
 398                 status = "disable";
 399         };
 400
 401         sdhci@700b0600 {
 402                 compatible = "nvidia,tegra124-sdhci";
 403                 reg = <0x700b0600 0x200>;
 404                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 405                 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
 406                 resets = <&tegra_car 15>;
 407                 reset-names = "sdhci";
 408                 status = "disable";
 409         };
 410
 411         ahub@70300000 {
 412                 compatible = "nvidia,tegra124-ahub";
 413                 reg = <0x70300000 0x200>,
 414                       <0x70300800 0x800>,
 415                       <0x70300200 0x600>;
 416                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 417                 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
 418                          <&tegra_car TEGRA124_CLK_APBIF>;
 419                 clock-names = "d_audio", "apbif";
 420                 resets = <&tegra_car 106>, /* d_audio */
 421                          <&tegra_car 107>, /* apbif */
 422                          <&tegra_car 30>,  /* i2s0 */
 423                          <&tegra_car 11>,  /* i2s1 */
 424                          <&tegra_car 18>,  /* i2s2 */
 425                          <&tegra_car 101>, /* i2s3 */
 426                          <&tegra_car 102>, /* i2s4 */
 427                          <&tegra_car 108>, /* dam0 */
 428                          <&tegra_car 109>, /* dam1 */
 429                          <&tegra_car 110>, /* dam2 */
 430                          <&tegra_car 10>,  /* spdif */
 431                          <&tegra_car 153>, /* amx */
 432                          <&tegra_car 185>, /* amx1 */
 433                          <&tegra_car 154>, /* adx */
 434                          <&tegra_car 180>, /* adx1 */
 435                          <&tegra_car 186>, /* afc0 */
 436                          <&tegra_car 187>, /* afc1 */
 437                          <&tegra_car 188>, /* afc2 */
 438                          <&tegra_car 189>, /* afc3 */
 439                          <&tegra_car 190>, /* afc4 */
 440                          <&tegra_car 191>; /* afc5 */
 441                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 442                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 443                               "spdif", "amx", "amx1", "adx", "adx1",
 444                               "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
 445                 dmas = <&apbdma 1>, <&apbdma 1>,
 446                        <&apbdma 2>, <&apbdma 2>,
 447                        <&apbdma 3>, <&apbdma 3>,
 448                        <&apbdma 4>, <&apbdma 4>,
 449                        <&apbdma 6>, <&apbdma 6>,
 450                        <&apbdma 7>, <&apbdma 7>,
 451                        <&apbdma 12>, <&apbdma 12>,
 452                        <&apbdma 13>, <&apbdma 13>,
 453                        <&apbdma 14>, <&apbdma 14>,
 454                        <&apbdma 29>, <&apbdma 29>;
 455                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 456                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 457                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 458                             "rx9", "tx9";
 459                 ranges;
 460                 #address-cells = <1>;
 461                 #size-cells = <1>;
 462
 463                 tegra_i2s0: i2s@70301000 {
 464                         compatible = "nvidia,tegra124-i2s";
 465                         reg = <0x70301000 0x100>;
 466                         nvidia,ahub-cif-ids = <4 4>;
 467                         clocks = <&tegra_car TEGRA124_CLK_I2S0>;
 468                         resets = <&tegra_car 30>;
 469                         reset-names = "i2s";
 470                         status = "disabled";
 471                 };
 472
 473                 tegra_i2s1: i2s@70301100 {
 474                         compatible = "nvidia,tegra124-i2s";
 475                         reg = <0x70301100 0x100>;
 476                         nvidia,ahub-cif-ids = <5 5>;
 477                         clocks = <&tegra_car TEGRA124_CLK_I2S1>;
 478                         resets = <&tegra_car 11>;
 479                         reset-names = "i2s";
 480                         status = "disabled";
 481                 };
 482
 483                 tegra_i2s2: i2s@70301200 {
 484                         compatible = "nvidia,tegra124-i2s";
 485                         reg = <0x70301200 0x100>;
 486                         nvidia,ahub-cif-ids = <6 6>;
 487                         clocks = <&tegra_car TEGRA124_CLK_I2S2>;
 488                         resets = <&tegra_car 18>;
 489                         reset-names = "i2s";
 490                         status = "disabled";
 491                 };
 492
 493                 tegra_i2s3: i2s@70301300 {
 494                         compatible = "nvidia,tegra124-i2s";
 495                         reg = <0x70301300 0x100>;
 496                         nvidia,ahub-cif-ids = <7 7>;
 497                         clocks = <&tegra_car TEGRA124_CLK_I2S3>;
 498                         resets = <&tegra_car 101>;
 499                         reset-names = "i2s";
 500                         status = "disabled";
 501                 };
 502
 503                 tegra_i2s4: i2s@70301400 {
 504                         compatible = "nvidia,tegra124-i2s";
 505                         reg = <0x70301400 0x100>;
 506                         nvidia,ahub-cif-ids = <8 8>;
 507                         clocks = <&tegra_car TEGRA124_CLK_I2S4>;
 508                         resets = <&tegra_car 102>;
 509                         reset-names = "i2s";
 510                         status = "disabled";
 511                 };
 512         };
 513
 514         cpus {
 515                 #address-cells = <1>;
 516                 #size-cells = <0>;
 517
 518                 cpu@0 {
 519                         device_type = "cpu";
 520                         compatible = "arm,cortex-a15";
 521                         reg = <0>;
 522                 };
 523
 524                 cpu@1 {
 525                         device_type = "cpu";
 526                         compatible = "arm,cortex-a15";
 527                         reg = <1>;
 528                 };
 529
 530                 cpu@2 {
 531                         device_type = "cpu";
 532                         compatible = "arm,cortex-a15";
 533                         reg = <2>;
 534                 };
 535
 536                 cpu@3 {
 537                         device_type = "cpu";
 538                         compatible = "arm,cortex-a15";
 539                         reg = <3>;
 540                 };
 541         };
 542
 543         timer {
 544                 compatible = "arm,armv7-timer";
 545                 interrupts = <GIC_PPI 13
 546                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 547                              <GIC_PPI 14
 548                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 549                              <GIC_PPI 11
 550                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 551                              <GIC_PPI 10
 552                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 553         };
 554 };