arch/arm/boot/dts/tegra114.dtsi

   1 /include/ "skeleton.dtsi"
   2
   3 / {
   4         compatible = "nvidia,tegra114";
   5         interrupt-parent = <&gic>;
   6
   7         gic: interrupt-controller {
   8                 compatible = "arm,cortex-a15-gic";
   9                 #interrupt-cells = <3>;
  10                 interrupt-controller;
  11                 reg = <0x50041000 0x1000>,
  12                       <0x50042000 0x1000>,
  13                       <0x50044000 0x2000>,
  14                       <0x50046000 0x2000>;
  15                 interrupts = <1 9 0xf04>;
  16         };
  17
  18         timer@60005000 {
  19                 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
  20                 reg = <0x60005000 0x400>;
  21                 interrupts = <0 0 0x04
  22                               0 1 0x04
  23                               0 41 0x04
  24                               0 42 0x04
  25                               0 121 0x04
  26                               0 122 0x04>;
  27         };
  28
  29         tegra_car: clock {
  30                 compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
  31                 reg = <0x60006000 0x1000>;
  32                 #clock-cells = <1>;
  33         };
  34
  35         serial@70006000 {
  36                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
  37                 reg = <0x70006000 0x40>;
  38                 reg-shift = <2>;
  39                 interrupts = <0 36 0x04>;
  40                 status = "disabled";
  41         };
  42
  43         serial@70006040 {
  44                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
  45                 reg = <0x70006040 0x40>;
  46                 reg-shift = <2>;
  47                 interrupts = <0 37 0x04>;
  48                 status = "disabled";
  49         };
  50
  51         serial@70006200 {
  52                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
  53                 reg = <0x70006200 0x100>;
  54                 reg-shift = <2>;
  55                 interrupts = <0 46 0x04>;
  56                 status = "disabled";
  57         };
  58
  59         serial@70006300 {
  60                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
  61                 reg = <0x70006300 0x100>;
  62                 reg-shift = <2>;
  63                 interrupts = <0 90 0x04>;
  64                 status = "disabled";
  65         };
  66
  67         rtc {
  68                 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
  69                 reg = <0x7000e000 0x100>;
  70                 interrupts = <0 2 0x04>;
  71         };
  72
  73         pmc {
  74                 compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc";
  75                 reg = <0x7000e400 0x400>;
  76         };
  77
  78         cpus {
  79                 #address-cells = <1>;
  80                 #size-cells = <0>;
  81
  82                 cpu@0 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a15";
  85                         reg = <0>;
  86                 };
  87
  88                 cpu@1 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a15";
  91                         reg = <1>;
  92                 };
  93
  94                 cpu@2 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a15";
  97                         reg = <2>;
  98                 };
  99
 100                 cpu@3 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a15";
 103                         reg = <3>;
 104                 };
 105         };
 106
 107         timer {
 108                 compatible = "arm,armv7-timer";
 109                 interrupts = <1 13 0xf08>,
 110                              <1 14 0xf08>,
 111                              <1 11 0xf08>,
 112                              <1 10 0xf08>;
 113         };
 114 };