arch/arm/boot/dts/tegra114.dtsi

   1 #include <dt-bindings/clock/tegra114-car.h>
   2 #include <dt-bindings/gpio/tegra-gpio.h>
   3 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5
   6 #include "skeleton.dtsi"
   7
   8 / {
   9         compatible = "nvidia,tegra114";
  10         interrupt-parent = <&gic>;
  11
  12         aliases {
  13                 serial0 = &uarta;
  14                 serial1 = &uartb;
  15                 serial2 = &uartc;
  16                 serial3 = &uartd;
  17         };
  18
  19         host1x@50000000 {
  20                 compatible = "nvidia,tegra114-host1x", "simple-bus";
  21                 reg = <0x50000000 0x00028000>;
  22                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  23                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  24                 clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
  25                 resets = <&tegra_car 28>;
  26                 reset-names = "host1x";
  27
  28                 #address-cells = <1>;
  29                 #size-cells = <1>;
  30
  31                 ranges = <0x54000000 0x54000000 0x01000000>;
  32
  33                 dc@54200000 {
  34                         compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
  35                         reg = <0x54200000 0x00040000>;
  36                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  37                         clocks = <&tegra_car TEGRA114_CLK_DISP1>,
  38                                  <&tegra_car TEGRA114_CLK_PLL_P>;
  39                         clock-names = "dc", "parent";
  40                         resets = <&tegra_car 27>;
  41                         reset-names = "dc";
  42
  43                         rgb {
  44                                 status = "disabled";
  45                         };
  46                 };
  47
  48                 dc@54240000 {
  49                         compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
  50                         reg = <0x54240000 0x00040000>;
  51                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  52                         clocks = <&tegra_car TEGRA114_CLK_DISP2>,
  53                                  <&tegra_car TEGRA114_CLK_PLL_P>;
  54                         clock-names = "dc", "parent";
  55                         resets = <&tegra_car 26>;
  56                         reset-names = "dc";
  57
  58                         rgb {
  59                                 status = "disabled";
  60                         };
  61                 };
  62
  63                 hdmi@54280000 {
  64                         compatible = "nvidia,tegra114-hdmi";
  65                         reg = <0x54280000 0x00040000>;
  66                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  67                         clocks = <&tegra_car TEGRA114_CLK_HDMI>,
  68                                  <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
  69                         clock-names = "hdmi", "parent";
  70                         resets = <&tegra_car 51>;
  71                         reset-names = "hdmi";
  72                         status = "disabled";
  73                 };
  74
  75                 dsi@54300000 {
  76                         compatible = "nvidia,tegra114-dsi";
  77                         reg = <0x54300000 0x00040000>;
  78                         clocks = <&tegra_car TEGRA114_CLK_DSIA>,
  79                                  <&tegra_car TEGRA114_CLK_DSIALP>,
  80                                  <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
  81                         clock-names = "dsi", "lp", "parent";
  82                         resets = <&tegra_car 48>;
  83                         reset-names = "dsi";
  84                         nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
  85                         status = "disabled";
  86
  87                         #address-cells = <1>;
  88                         #size-cells = <0>;
  89                 };
  90
  91                 dsi@54400000 {
  92                         compatible = "nvidia,tegra114-dsi";
  93                         reg = <0x54400000 0x00040000>;
  94                         clocks = <&tegra_car TEGRA114_CLK_DSIB>,
  95                                  <&tegra_car TEGRA114_CLK_DSIBLP>,
  96                                  <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
  97                         clock-names = "dsi", "lp", "parent";
  98                         resets = <&tegra_car 82>;
  99                         reset-names = "dsi";
 100                         nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
 101                         status = "disabled";
 102
 103                         #address-cells = <1>;
 104                         #size-cells = <0>;
 105                 };
 106         };
 107
 108         gic: interrupt-controller@50041000 {
 109                 compatible = "arm,cortex-a15-gic";
 110                 #interrupt-cells = <3>;
 111                 interrupt-controller;
 112                 reg = <0x50041000 0x1000>,
 113                       <0x50042000 0x1000>,
 114                       <0x50044000 0x2000>,
 115                       <0x50046000 0x2000>;
 116                 interrupts = <GIC_PPI 9
 117                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 118         };
 119
 120         timer@60005000 {
 121                 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
 122                 reg = <0x60005000 0x400>;
 123                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 124                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 125                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 126                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 127                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 128                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 129                 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
 130         };
 131
 132         tegra_car: clock@60006000 {
 133                 compatible = "nvidia,tegra114-car";
 134                 reg = <0x60006000 0x1000>;
 135                 #clock-cells = <1>;
 136                 #reset-cells = <1>;
 137         };
 138
 139         apbdma: dma@6000a000 {
 140                 compatible = "nvidia,tegra114-apbdma";
 141                 reg = <0x6000a000 0x1400>;
 142                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 143                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 144                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 145                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 146                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 147                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 149                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 150                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 151                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 152                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 153                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 154                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 155                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 156                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 157                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 158                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 159                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 160                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 161                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 162                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 163                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 164                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 165                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 166                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 167                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 168                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 169                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 170                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 171                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 172                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 173                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 174                 clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
 175                 resets = <&tegra_car 34>;
 176                 reset-names = "dma";
 177                 #dma-cells = <1>;
 178         };
 179
 180         ahb: ahb@6000c004 {
 181                 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
 182                 reg = <0x6000c004 0x14c>;
 183         };
 184
 185         gpio: gpio@6000d000 {
 186                 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
 187                 reg = <0x6000d000 0x1000>;
 188                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 189                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 190                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 191                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 195                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 196                 #gpio-cells = <2>;
 197                 gpio-controller;
 198                 #interrupt-cells = <2>;
 199                 interrupt-controller;
 200         };
 201
 202         pinmux: pinmux@70000868 {
 203                 compatible = "nvidia,tegra114-pinmux";
 204                 reg = <0x70000868 0x148         /* Pad control registers */
 205                        0x70003000 0x40c>;       /* Mux registers */
 206         };
 207
 208         /*
 209          * There are two serial driver i.e. 8250 based simple serial
 210          * driver and APB DMA based serial driver for higher baudrate
 211          * and performace. To enable the 8250 based driver, the compatible
 212          * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
 213          * the APB DMA based serial driver, the comptible is
 214          * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
 215          */
 216         uarta: serial@70006000 {
 217                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 218                 reg = <0x70006000 0x40>;
 219                 reg-shift = <2>;
 220                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 221                 clocks = <&tegra_car TEGRA114_CLK_UARTA>;
 222                 resets = <&tegra_car 6>;
 223                 reset-names = "serial";
 224                 dmas = <&apbdma 8>, <&apbdma 8>;
 225                 dma-names = "rx", "tx";
 226                 status = "disabled";
 227         };
 228
 229         uartb: serial@70006040 {
 230                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 231                 reg = <0x70006040 0x40>;
 232                 reg-shift = <2>;
 233                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 234                 clocks = <&tegra_car TEGRA114_CLK_UARTB>;
 235                 resets = <&tegra_car 7>;
 236                 reset-names = "serial";
 237                 dmas = <&apbdma 9>, <&apbdma 9>;
 238                 dma-names = "rx", "tx";
 239                 status = "disabled";
 240         };
 241
 242         uartc: serial@70006200 {
 243                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 244                 reg = <0x70006200 0x100>;
 245                 reg-shift = <2>;
 246                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 247                 clocks = <&tegra_car TEGRA114_CLK_UARTC>;
 248                 resets = <&tegra_car 55>;
 249                 reset-names = "serial";
 250                 dmas = <&apbdma 10>, <&apbdma 10>;
 251                 dma-names = "rx", "tx";
 252                 status = "disabled";
 253         };
 254
 255         uartd: serial@70006300 {
 256                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 257                 reg = <0x70006300 0x100>;
 258                 reg-shift = <2>;
 259                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 260                 clocks = <&tegra_car TEGRA114_CLK_UARTD>;
 261                 resets = <&tegra_car 65>;
 262                 reset-names = "serial";
 263                 dmas = <&apbdma 19>, <&apbdma 19>;
 264                 dma-names = "rx", "tx";
 265                 status = "disabled";
 266         };
 267
 268         pwm: pwm@7000a000 {
 269                 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
 270                 reg = <0x7000a000 0x100>;
 271                 #pwm-cells = <2>;
 272                 clocks = <&tegra_car TEGRA114_CLK_PWM>;
 273                 resets = <&tegra_car 17>;
 274                 reset-names = "pwm";
 275                 status = "disabled";
 276         };
 277
 278         i2c@7000c000 {
 279                 compatible = "nvidia,tegra114-i2c";
 280                 reg = <0x7000c000 0x100>;
 281                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 282                 #address-cells = <1>;
 283                 #size-cells = <0>;
 284                 clocks = <&tegra_car TEGRA114_CLK_I2C1>;
 285                 clock-names = "div-clk";
 286                 resets = <&tegra_car 12>;
 287                 reset-names = "i2c";
 288                 dmas = <&apbdma 21>, <&apbdma 21>;
 289                 dma-names = "rx", "tx";
 290                 status = "disabled";
 291         };
 292
 293         i2c@7000c400 {
 294                 compatible = "nvidia,tegra114-i2c";
 295                 reg = <0x7000c400 0x100>;
 296                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 297                 #address-cells = <1>;
 298                 #size-cells = <0>;
 299                 clocks = <&tegra_car TEGRA114_CLK_I2C2>;
 300                 clock-names = "div-clk";
 301                 resets = <&tegra_car 54>;
 302                 reset-names = "i2c";
 303                 dmas = <&apbdma 22>, <&apbdma 22>;
 304                 dma-names = "rx", "tx";
 305                 status = "disabled";
 306         };
 307
 308         i2c@7000c500 {
 309                 compatible = "nvidia,tegra114-i2c";
 310                 reg = <0x7000c500 0x100>;
 311                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 312                 #address-cells = <1>;
 313                 #size-cells = <0>;
 314                 clocks = <&tegra_car TEGRA114_CLK_I2C3>;
 315                 clock-names = "div-clk";
 316                 resets = <&tegra_car 67>;
 317                 reset-names = "i2c";
 318                 dmas = <&apbdma 23>, <&apbdma 23>;
 319                 dma-names = "rx", "tx";
 320                 status = "disabled";
 321         };
 322
 323         i2c@7000c700 {
 324                 compatible = "nvidia,tegra114-i2c";
 325                 reg = <0x7000c700 0x100>;
 326                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 327                 #address-cells = <1>;
 328                 #size-cells = <0>;
 329                 clocks = <&tegra_car TEGRA114_CLK_I2C4>;
 330                 clock-names = "div-clk";
 331                 resets = <&tegra_car 103>;
 332                 reset-names = "i2c";
 333                 dmas = <&apbdma 26>, <&apbdma 26>;
 334                 dma-names = "rx", "tx";
 335                 status = "disabled";
 336         };
 337
 338         i2c@7000d000 {
 339                 compatible = "nvidia,tegra114-i2c";
 340                 reg = <0x7000d000 0x100>;
 341                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 342                 #address-cells = <1>;
 343                 #size-cells = <0>;
 344                 clocks = <&tegra_car TEGRA114_CLK_I2C5>;
 345                 clock-names = "div-clk";
 346                 resets = <&tegra_car 47>;
 347                 reset-names = "i2c";
 348                 dmas = <&apbdma 24>, <&apbdma 24>;
 349                 dma-names = "rx", "tx";
 350                 status = "disabled";
 351         };
 352
 353         spi@7000d400 {
 354                 compatible = "nvidia,tegra114-spi";
 355                 reg = <0x7000d400 0x200>;
 356                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 357                 #address-cells = <1>;
 358                 #size-cells = <0>;
 359                 clocks = <&tegra_car TEGRA114_CLK_SBC1>;
 360                 clock-names = "spi";
 361                 resets = <&tegra_car 41>;
 362                 reset-names = "spi";
 363                 dmas = <&apbdma 15>, <&apbdma 15>;
 364                 dma-names = "rx", "tx";
 365                 status = "disabled";
 366         };
 367
 368         spi@7000d600 {
 369                 compatible = "nvidia,tegra114-spi";
 370                 reg = <0x7000d600 0x200>;
 371                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 372                 #address-cells = <1>;
 373                 #size-cells = <0>;
 374                 clocks = <&tegra_car TEGRA114_CLK_SBC2>;
 375                 clock-names = "spi";
 376                 resets = <&tegra_car 44>;
 377                 reset-names = "spi";
 378                 dmas = <&apbdma 16>, <&apbdma 16>;
 379                 dma-names = "rx", "tx";
 380                 status = "disabled";
 381         };
 382
 383         spi@7000d800 {
 384                 compatible = "nvidia,tegra114-spi";
 385                 reg = <0x7000d800 0x200>;
 386                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 387                 #address-cells = <1>;
 388                 #size-cells = <0>;
 389                 clocks = <&tegra_car TEGRA114_CLK_SBC3>;
 390                 clock-names = "spi";
 391                 resets = <&tegra_car 46>;
 392                 reset-names = "spi";
 393                 dmas = <&apbdma 17>, <&apbdma 17>;
 394                 dma-names = "rx", "tx";
 395                 status = "disabled";
 396         };
 397
 398         spi@7000da00 {
 399                 compatible = "nvidia,tegra114-spi";
 400                 reg = <0x7000da00 0x200>;
 401                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 402                 #address-cells = <1>;
 403                 #size-cells = <0>;
 404                 clocks = <&tegra_car TEGRA114_CLK_SBC4>;
 405                 clock-names = "spi";
 406                 resets = <&tegra_car 68>;
 407                 reset-names = "spi";
 408                 dmas = <&apbdma 18>, <&apbdma 18>;
 409                 dma-names = "rx", "tx";
 410                 status = "disabled";
 411         };
 412
 413         spi@7000dc00 {
 414                 compatible = "nvidia,tegra114-spi";
 415                 reg = <0x7000dc00 0x200>;
 416                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 417                 #address-cells = <1>;
 418                 #size-cells = <0>;
 419                 clocks = <&tegra_car TEGRA114_CLK_SBC5>;
 420                 clock-names = "spi";
 421                 resets = <&tegra_car 104>;
 422                 reset-names = "spi";
 423                 dmas = <&apbdma 27>, <&apbdma 27>;
 424                 dma-names = "rx", "tx";
 425                 status = "disabled";
 426         };
 427
 428         spi@7000de00 {
 429                 compatible = "nvidia,tegra114-spi";
 430                 reg = <0x7000de00 0x200>;
 431                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 432                 #address-cells = <1>;
 433                 #size-cells = <0>;
 434                 clocks = <&tegra_car TEGRA114_CLK_SBC6>;
 435                 clock-names = "spi";
 436                 resets = <&tegra_car 105>;
 437                 reset-names = "spi";
 438                 dmas = <&apbdma 28>, <&apbdma 28>;
 439                 dma-names = "rx", "tx";
 440                 status = "disabled";
 441         };
 442
 443         rtc@7000e000 {
 444                 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
 445                 reg = <0x7000e000 0x100>;
 446                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 447                 clocks = <&tegra_car TEGRA114_CLK_RTC>;
 448         };
 449
 450         kbc@7000e200 {
 451                 compatible = "nvidia,tegra114-kbc";
 452                 reg = <0x7000e200 0x100>;
 453                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 454                 clocks = <&tegra_car TEGRA114_CLK_KBC>;
 455                 resets = <&tegra_car 36>;
 456                 reset-names = "kbc";
 457                 status = "disabled";
 458         };
 459
 460         pmc@7000e400 {
 461                 compatible = "nvidia,tegra114-pmc";
 462                 reg = <0x7000e400 0x400>;
 463                 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
 464                 clock-names = "pclk", "clk32k_in";
 465         };
 466
 467         iommu@70019010 {
 468                 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
 469                 reg = <0x70019010 0x02c
 470                        0x700191f0 0x010
 471                        0x70019228 0x074>;
 472                 nvidia,#asids = <4>;
 473                 dma-window = <0 0x40000000>;
 474                 nvidia,swgroups = <0x18659fe>;
 475                 nvidia,ahb = <&ahb>;
 476         };
 477
 478         ahub@70080000 {
 479                 compatible = "nvidia,tegra114-ahub";
 480                 reg = <0x70080000 0x200>,
 481                       <0x70080200 0x100>,
 482                       <0x70081000 0x200>;
 483                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 484                 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
 485                          <&tegra_car TEGRA114_CLK_APBIF>;
 486                 clock-names = "d_audio", "apbif";
 487                 resets = <&tegra_car 106>, /* d_audio */
 488                          <&tegra_car 107>, /* apbif */
 489                          <&tegra_car 30>,  /* i2s0 */
 490                          <&tegra_car 11>,  /* i2s1 */
 491                          <&tegra_car 18>,  /* i2s2 */
 492                          <&tegra_car 101>, /* i2s3 */
 493                          <&tegra_car 102>, /* i2s4 */
 494                          <&tegra_car 108>, /* dam0 */
 495                          <&tegra_car 109>, /* dam1 */
 496                          <&tegra_car 110>, /* dam2 */
 497                          <&tegra_car 10>,  /* spdif */
 498                          <&tegra_car 153>, /* amx */
 499                          <&tegra_car 154>; /* adx */
 500                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 501                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 502                               "spdif", "amx", "adx";
 503                 dmas = <&apbdma 1>, <&apbdma 1>,
 504                        <&apbdma 2>, <&apbdma 2>,
 505                        <&apbdma 3>, <&apbdma 3>,
 506                        <&apbdma 4>, <&apbdma 4>,
 507                        <&apbdma 6>, <&apbdma 6>,
 508                        <&apbdma 7>, <&apbdma 7>,
 509                        <&apbdma 12>, <&apbdma 12>,
 510                        <&apbdma 13>, <&apbdma 13>,
 511                        <&apbdma 14>, <&apbdma 14>,
 512                        <&apbdma 29>, <&apbdma 29>;
 513                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 514                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 515                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 516                             "rx9", "tx9";
 517                 ranges;
 518                 #address-cells = <1>;
 519                 #size-cells = <1>;
 520
 521                 tegra_i2s0: i2s@70080300 {
 522                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 523                         reg = <0x70080300 0x100>;
 524                         nvidia,ahub-cif-ids = <4 4>;
 525                         clocks = <&tegra_car TEGRA114_CLK_I2S0>;
 526                         resets = <&tegra_car 30>;
 527                         reset-names = "i2s";
 528                         status = "disabled";
 529                 };
 530
 531                 tegra_i2s1: i2s@70080400 {
 532                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 533                         reg = <0x70080400 0x100>;
 534                         nvidia,ahub-cif-ids = <5 5>;
 535                         clocks = <&tegra_car TEGRA114_CLK_I2S1>;
 536                         resets = <&tegra_car 11>;
 537                         reset-names = "i2s";
 538                         status = "disabled";
 539                 };
 540
 541                 tegra_i2s2: i2s@70080500 {
 542                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 543                         reg = <0x70080500 0x100>;
 544                         nvidia,ahub-cif-ids = <6 6>;
 545                         clocks = <&tegra_car TEGRA114_CLK_I2S2>;
 546                         resets = <&tegra_car 18>;
 547                         reset-names = "i2s";
 548                         status = "disabled";
 549                 };
 550
 551                 tegra_i2s3: i2s@70080600 {
 552                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 553                         reg = <0x70080600 0x100>;
 554                         nvidia,ahub-cif-ids = <7 7>;
 555                         clocks = <&tegra_car TEGRA114_CLK_I2S3>;
 556                         resets = <&tegra_car 101>;
 557                         reset-names = "i2s";
 558                         status = "disabled";
 559                 };
 560
 561                 tegra_i2s4: i2s@70080700 {
 562                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 563                         reg = <0x70080700 0x100>;
 564                         nvidia,ahub-cif-ids = <8 8>;
 565                         clocks = <&tegra_car TEGRA114_CLK_I2S4>;
 566                         resets = <&tegra_car 102>;
 567                         reset-names = "i2s";
 568                         status = "disabled";
 569                 };
 570         };
 571
 572         mipi: mipi@700e3000 {
 573                 compatible = "nvidia,tegra114-mipi";
 574                 reg = <0x700e3000 0x100>;
 575                 clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
 576                 #nvidia,mipi-calibrate-cells = <1>;
 577         };
 578
 579         sdhci@78000000 {
 580                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 581                 reg = <0x78000000 0x200>;
 582                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 583                 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
 584                 resets = <&tegra_car 14>;
 585                 reset-names = "sdhci";
 586                 status = "disable";
 587         };
 588
 589         sdhci@78000200 {
 590                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 591                 reg = <0x78000200 0x200>;
 592                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 593                 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
 594                 resets = <&tegra_car 9>;
 595                 reset-names = "sdhci";
 596                 status = "disable";
 597         };
 598
 599         sdhci@78000400 {
 600                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 601                 reg = <0x78000400 0x200>;
 602                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 603                 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
 604                 resets = <&tegra_car 69>;
 605                 reset-names = "sdhci";
 606                 status = "disable";
 607         };
 608
 609         sdhci@78000600 {
 610                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 611                 reg = <0x78000600 0x200>;
 612                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 613                 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
 614                 resets = <&tegra_car 15>;
 615                 reset-names = "sdhci";
 616                 status = "disable";
 617         };
 618
 619         usb@7d000000 {
 620                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 621                 reg = <0x7d000000 0x4000>;
 622                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 623                 phy_type = "utmi";
 624                 clocks = <&tegra_car TEGRA114_CLK_USBD>;
 625                 resets = <&tegra_car 22>;
 626                 reset-names = "usb";
 627                 nvidia,phy = <&phy1>;
 628                 status = "disabled";
 629         };
 630
 631         phy1: usb-phy@7d000000 {
 632                 compatible = "nvidia,tegra30-usb-phy";
 633                 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
 634                 phy_type = "utmi";
 635                 clocks = <&tegra_car TEGRA114_CLK_USBD>,
 636                          <&tegra_car TEGRA114_CLK_PLL_U>,
 637                          <&tegra_car TEGRA114_CLK_USBD>;
 638                 clock-names = "reg", "pll_u", "utmi-pads";
 639                 nvidia,hssync-start-delay = <0>;
 640                 nvidia,idle-wait-delay = <17>;
 641                 nvidia,elastic-limit = <16>;
 642                 nvidia,term-range-adj = <6>;
 643                 nvidia,xcvr-setup = <9>;
 644                 nvidia,xcvr-lsfslew = <0>;
 645                 nvidia,xcvr-lsrslew = <3>;
 646                 nvidia,hssquelch-level = <2>;
 647                 nvidia,hsdiscon-level = <5>;
 648                 nvidia,xcvr-hsslew = <12>;
 649                 status = "disabled";
 650         };
 651
 652         usb@7d008000 {
 653                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 654                 reg = <0x7d008000 0x4000>;
 655                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 656                 phy_type = "utmi";
 657                 clocks = <&tegra_car TEGRA114_CLK_USB3>;
 658                 resets = <&tegra_car 59>;
 659                 reset-names = "usb";
 660                 nvidia,phy = <&phy3>;
 661                 status = "disabled";
 662         };
 663
 664         phy3: usb-phy@7d008000 {
 665                 compatible = "nvidia,tegra30-usb-phy";
 666                 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
 667                 phy_type = "utmi";
 668                 clocks = <&tegra_car TEGRA114_CLK_USB3>,
 669                          <&tegra_car TEGRA114_CLK_PLL_U>,
 670                          <&tegra_car TEGRA114_CLK_USBD>;
 671                 clock-names = "reg", "pll_u", "utmi-pads";
 672                 nvidia,hssync-start-delay = <0>;
 673                 nvidia,idle-wait-delay = <17>;
 674                 nvidia,elastic-limit = <16>;
 675                 nvidia,term-range-adj = <6>;
 676                 nvidia,xcvr-setup = <9>;
 677                 nvidia,xcvr-lsfslew = <0>;
 678                 nvidia,xcvr-lsrslew = <3>;
 679                 nvidia,hssquelch-level = <2>;
 680                 nvidia,hsdiscon-level = <5>;
 681                 nvidia,xcvr-hsslew = <12>;
 682                 status = "disabled";
 683         };
 684
 685         cpus {
 686                 #address-cells = <1>;
 687                 #size-cells = <0>;
 688
 689                 cpu@0 {
 690                         device_type = "cpu";
 691                         compatible = "arm,cortex-a15";
 692                         reg = <0>;
 693                 };
 694
 695                 cpu@1 {
 696                         device_type = "cpu";
 697                         compatible = "arm,cortex-a15";
 698                         reg = <1>;
 699                 };
 700
 701                 cpu@2 {
 702                         device_type = "cpu";
 703                         compatible = "arm,cortex-a15";
 704                         reg = <2>;
 705                 };
 706
 707                 cpu@3 {
 708                         device_type = "cpu";
 709                         compatible = "arm,cortex-a15";
 710                         reg = <3>;
 711                 };
 712         };
 713
 714         timer {
 715                 compatible = "arm,armv7-timer";
 716                 interrupts =
 717                         <GIC_PPI 13
 718                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 719                         <GIC_PPI 14
 720                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 721                         <GIC_PPI 11
 722                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 723                         <GIC_PPI 10
 724                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 725         };
 726 };