arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
   4  * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
   5  */
   6
   7 /dts-v1/;
   8
   9 #include "stm32mp157c-ev1.dts"
  10 #include "stm32mp15-scmi.dtsi"
  11
  12 / {
  13         model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother";
  14         compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1",
  15                      "st,stm32mp157";
  16
  17         reserved-memory {
  18                 optee@fe000000 {
  19                         reg = <0xfe000000 0x2000000>;
  20                         no-map;
  21                 };
  22         };
  23 };
  24
  25 &cpu0 {
  26         clocks = <&scmi_clk CK_SCMI_MPU>;
  27 };
  28
  29 &cpu1 {
  30         clocks = <&scmi_clk CK_SCMI_MPU>;
  31 };
  32
  33 &cryp1 {
  34         clocks = <&scmi_clk CK_SCMI_CRYP1>;
  35         resets = <&scmi_reset RST_SCMI_CRYP1>;
  36 };
  37
  38 &dsi {
  39         clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
  40 };
  41
  42 &gpioz {
  43         clocks = <&scmi_clk CK_SCMI_GPIOZ>;
  44 };
  45
  46 &hash1 {
  47         clocks = <&scmi_clk CK_SCMI_HASH1>;
  48         resets = <&scmi_reset RST_SCMI_HASH1>;
  49 };
  50
  51 &i2c4 {
  52         clocks = <&scmi_clk CK_SCMI_I2C4>;
  53         resets = <&scmi_reset RST_SCMI_I2C4>;
  54 };
  55
  56 &iwdg2 {
  57         clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
  58 };
  59
  60 &m_can1 {
  61         clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
  62 };
  63
  64 &mdma1 {
  65         resets = <&scmi_reset RST_SCMI_MDMA>;
  66 };
  67
  68 &mlahb {
  69         resets = <&scmi_reset RST_SCMI_MCU>;
  70 };
  71
  72 &rcc {
  73         compatible = "st,stm32mp1-rcc-secure", "syscon";
  74         clock-names = "hse", "hsi", "csi", "lse", "lsi";
  75         clocks = <&scmi_clk CK_SCMI_HSE>,
  76                  <&scmi_clk CK_SCMI_HSI>,
  77                  <&scmi_clk CK_SCMI_CSI>,
  78                  <&scmi_clk CK_SCMI_LSE>,
  79                  <&scmi_clk CK_SCMI_LSI>;
  80 };
  81
  82 &rng1 {
  83         clocks = <&scmi_clk CK_SCMI_RNG1>;
  84         resets = <&scmi_reset RST_SCMI_RNG1>;
  85 };
  86
  87 &rtc {
  88         clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
  89 };