arch/arm/boot/dts/sprd-scx35_sp8730sea.dts

   1 /*
   2 * Copyright (C) 2013 Spreadtrum Communication Incorporated
   3 *               http://www.spreadtrum.com/
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License version 2 as
   7 * published by the Free Software Foundation.
   8 */
   9 /dts-v1/;
  10
  11 /* memory reserved for SMEM */
  12 /memreserve/ 0x87800000 0x200000; /* 2MK */
  13
  14 /* memory reserved for CPW modem */
  15 /memreserve/ 0x88000000 0x1b00000; /* 27M */
  16
  17 /* memory reserved for CPWCN modem */
  18 /memreserve/ 0x8a800000 0x201000;/*Offset:168M, SIZE:2M+4k*/
  19
  20 /* memory reserved for fb */
  21 /memreserve/ 0x9F311000 0x5EF000; /* 540*960*4*3, 4K alignment */
  22
  23 /* memory reserved for ION */
  24 /memreserve/ 0x9f900000 0x700000; /* 7MK */
  25
  26 /include/ "skeleton.dtsi"
  27 /include/ "scx30g-clocks.dtsi"
  28 /include/ "sc2723-regulators.dtsi"
  29 /include/ "sprd-sound.dtsi"
  30 /include/ "sprd-battery.dtsi"
  31
  32 / {
  33         model = "Spreadtrum SP8835EB board";
  34         compatible = "sprd,sp8835eb";
  35         sprd,sc-id = <8830 1 0x20000>;
  36         #address-cells = <1>;
  37         #size-cells = <1>;
  38         interrupt-parent = <&gic>;
  39
  40         chosen {
  41                 bootargs = "loglevel=1 console=ttyS1,115200n8 init=/init root=/dev/ram0 rw";
  42                 linux,initrd-start = <0x85500000>;
  43                 linux,initrd-end   = <0x855a3212>;
  44         };
  45
  46         memory {
  47                 device_type = "memory";
  48                 reg = <0x80000000 0x20000000>;
  49         };
  50
  51         aliases {
  52                 serial0 = &uart0;
  53                 serial1 = &uart1;
  54                 serial2 = &uart2;
  55                 serial3 = &uart3;
  56                 i2c0 = &i2c0;
  57                 i2c1 = &i2c1;
  58                 i2c2 = &i2c2;
  59                 i2c3 = &i2c3;
  60                 lcd0 = &fb0;
  61                 spi0 = &spi0;
  62                 spi1 = &spi1;
  63                 spi2 = &spi2;
  64                 hwspinlock0 = &hwspinlock0;
  65                 hwspinlock1 = &hwspinlock1;
  66         };
  67
  68         cpus {
  69                 #address-cells = <1>;
  70                 #size-cells = <0>;
  71
  72                 cpu@f00 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a7";
  75                         reg = <0xf00>;
  76                 };
  77
  78                 cpu@f01 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a7";
  81                         reg = <0xf01>;
  82                 };
  83
  84                 cpu@f02 {
  85                         device_type = "cpu";
  86                         compatible = "arm,cortex-a7";
  87                         reg = <0xf02>;
  88                 };
  89
  90                 cpu@f03 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a7";
  93                         reg = <0xf03>;
  94                 };
  95         };
  96
  97     gic: interrupt-controller@12001000 {
  98         compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  99         #interrupt-cells = <3>;
 100         #address-cells = <0>;
 101         interrupt-controller;
 102         reg = <0x12001000 0x1000>,
 103               <0x12002000 0x1000>;
 104     };
 105
 106          uart0: uart@f5360000{
 107                  compatible  = "sprd,serial";
 108                  interrupts = <0 2 0x0>;
 109                  reg = <0xf5360000 0x1000>;
 110                  clock-names = "clk_uart0";
 111                  clocks = <&clock 60>;
 112                  sprdclk = <48000000>;
 113                  sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP";
 114          };
 115          uart1: uart@f5362000{
 116                  compatible  = "sprd,serial";
 117                  interrupts = <0 3 0x0>;
 118                  reg = <0xf5362000 0x1000>;
 119                  clock-names = "clk_uart1";
 120                  clocks = <&clock 61>;
 121                  sprdclk = <26000000>;
 122                  sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP";
 123          };
 124          uart2: uart@f5364000{
 125                  compatible  = "sprd,serial";
 126                  interrupts = <0 4 0x0>;
 127                  reg = <0xf5364000 0x1000>;
 128                  clock-names = "clk_uart2";
 129                  clocks = <&clock 62>;
 130                  sprdclk = <26000000>;
 131                  sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP";
 132          };
 133          uart3: uart@f5366000{
 134                  compatible  = "sprd,serial";
 135                  interrupts = <0 5 0x0>;
 136                  reg = <0xf5366000 0x1000>;
 137                  clock-names = "clk_uart3";
 138                  clocks = <&clock 63>;
 139                  sprdclk = <26000000>;
 140                  sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP";
 141          };
 142
 143          timer{
 144                  compatible  = "sprd,scx35-timer";
 145                  reg = <0xf5204000 0x1000>,
 146                          <0xf51f4000 0x1000>,
 147                          <0xf5202000 0x1000>,
 148                          <0xf5292000 0x1000>,
 149                          <0xf5294000 0x1000>;
 150                  interrupts = <0 118 0x0>,
 151                                         <0 28 0x0>,
 152                                         <0 29 0x0>,
 153                                         <0 119 0x0>,
 154                                         <0 121 0x0>;
 155          };
 156          clock: clockdevice{
 157                  compatible = "sprd,scx35-clock";
 158                 #clock-cells = <1>;
 159          };
 160          d_eic_gpio: gpio@f5200000{
 161                  compatible = "sprd,d-eic-gpio";
 162                  reg = <0Xf5200000 0x1000>;
 163                  gpio-controller;
 164                  interrupt-controller;
 165                  #interrupt-cells = <2>;
 166                  #gpio-cells = <2>;
 167                  gpiobase = <288>;
 168                  ngpios = <16>;
 169                  interrupts = <0 37 0x0>;
 170          };
 171          d_gpio_gpio: gpio@f5220000{
 172                  compatible = "sprd,d-gpio-gpio";
 173                  reg = <0Xf5220000 0x1000>;
 174                  gpio-controller;
 175                  interrupt-controller;
 176                  #interrupt-cells = <2>;
 177                  #gpio-cells = <2>;
 178                  gpiobase = <0>;
 179                  ngpios = <256>;
 180                  interrupts = <0 35 0x0>;
 181          };
 182         pinctrl{
 183                 compatible = "sprd,pinctrl";
 184                 reg = <0xf5224000 0x1000>;
 185                 pwr_domain = "vdd28",
 186                                          "vdd28",
 187                                          "vddsim0",
 188                                          "vddsim1",
 189                                          "vddsim2",
 190                                          "vddsdio",
 191                                          "vdd18";
 192                 ctrl_desc = <0x10 0 1
 193                                     0x10 1 1
 194                                     0x10 2 1
 195                                     0x10 3 1
 196                                     0x10 4 1
 197                                     0x10 5 1
 198                                     0x10 6 1>;
 199         };
 200
 201         sdios{
 202                 #address-cells = <2>;
 203                 #size-cells = <2>;
 204                 ranges;
 205                 sdio3: sdio@20600000{
 206                         compatible  = "sprd,sdhost-3.0";
 207                         reg = <0 0x20600000 0 0x1000>;
 208                         interrupts = <0 60 0x0>;
 209                         sprd,name = "sdio_emmc";
 210                         /*detect_gpio = <-1>; */
 211                         SD_Pwr_Name = "vddemmccore";
 212                         _1_8V_signal_Name = "vddgen0";
 213                         signal_default_Voltage = <1800000>;
 214                         ocr_avail = <0x00040000>;
 215                         clocks = <&clk_emmc>, <&clk_384m>;
 216                         base_clk = <384000000>;
 217                         caps = <0xC00F8D47>;
 218                         caps2 = <0x202>;
 219                         pm_caps = <0x4>;
 220                         writeDelay = <0x4>;
 221                         readPosDelay = <0x4>;
 222                         readNegDelay = <0x4>;
 223                 };
 224
 225                 sdio0: sdio@20300000{
 226                         compatible  = "sprd,sdhost-3.0";
 227                         reg = <0 0x20300000 0 0x1000>;
 228                         interrupts = <0 57 0x0>;
 229                         sprd,name = "sdio_sd";
 230                         /* detect_gpio = <71>; */
 231                         SD_Pwr_Name = "vddsdcore";
 232                         _1_8V_signal_Name = "vddsdio";
 233                         signal_default_Voltage = <3000000>;
 234                         ocr_avail = <0x00040000>;
 235                         clocks = <&clk_sdio0>, <&clk_384m>;
 236                         base_clk = <384000000>;
 237                         caps = <0x40038507>;
 238                         caps2 = <0x200>;
 239                         pm_caps = <0x4>;
 240                         writeDelay = <0x3>;
 241                         readPosDelay = <0x3>;
 242                         readNegDelay = <0x3>;
 243                 };
 244
 245
 246                 sdio1: sdio@20400000{
 247                         compatible  = "sprd,sdhost-3.0";
 248                         reg = <0 0x20400000 0 0x1000>;
 249                         interrupts = <0 58 0x0>;
 250                         sprd,name = "sdio_wifi";
 251                         /* detect_gpio = <-1>; */
 252                         /* SD_Pwr_Name = "vddsdcore"; */
 253                         /* _1_8V_signal_Name = "vddsdio";*/
 254                         /* signal_default_Voltage = <3000000>; */
 255                         ocr_avail = <0x00360080>;
 256                         clocks = <&clk_sdio1>, <&clk_76m8>;
 257                         base_clk = <96000000>;
 258                         caps = <0xC00FA407>;
 259                         caps2 = <0x0>;
 260                         pm_caps = <0x5>;
 261                         writeDelay = <0x03>;
 262                         readPosDelay = <0x03>;
 263                         readNegDelay = <0x03>;
 264                 };
 265         };
 266         adic:adic{
 267                 compatible = "sprd,adic";
 268                 reg = <0Xf53f0000 0x1000>;
 269         };
 270          adi: adi_bus{
 271                  compatible = "sprd,adi-bus";
 272                  interrupts = <0 38 0x0>;
 273                  reg = <0Xf53f8000 0x1000>;
 274                  interrupt-controller;
 275                  sprd,irqnums = <11>;
 276                  #interrupt-cells = <2>;
 277                  #address-cells = <1>;
 278                  #size-cells = <1>;
 279                  ranges = <0X40 0Xf53f8040 0x40>,
 280                                   <0X80 0Xf53f8080 0x80>,
 281                                   <0X100 0Xf53f8100 0x80>;
 282                  sprd_backlight {
 283                         compatible = "sprd,sprd_backlight";
 284                         start = <3>;
 285                         end = <3>;
 286                         flags = <0x100>;
 287                  };
 288                  headset_detect {
 289                         compatible = "sprd,headset-detect";
 290                         gpio_switch = <0>;
 291                         gpio_detect = <312>;
 292                         gpio_button = <307>;
 293                         irq_trigger_level_detect = <1>;
 294                         irq_trigger_level_button = <1>;
 295                         adc_threshold_3pole_detect = <100>;
 296                         adc_threshold_4pole_detect = <3100>;
 297                         irq_threshold_buttont = <1>;
 298                         voltage_headmicbias = <3000000>;
 299                         nbuttons = <1>;
 300                         headset_buttons {
 301                                 adc_min = <0>;
 302                                 adc_max = <170>;
 303                                 code = <226>;
 304                                 type = <0>;
 305                         };
 306                  };
 307                  headset_sprd_sc2723 {
 308                         compatible = "sprd,headset_sprd_sc2723";
 309                         gpio_switch = <0>;
 310                         gpio_detect = <312>;
 311                         gpio_button = <307>;
 312                         irq_trigger_level_detect = <1>;
 313                         irq_trigger_level_button = <1>;
 314                         adc_threshold_3pole_detect = <100>;
 315                         adc_threshold_4pole_detect = <3100>;
 316                         irq_threshold_buttont = <1>;
 317                         voltage_headmicbias = <3000000>;
 318                         nbuttons = <1>;
 319                         headset_buttons {
 320                                 adc_min = <0>;
 321                                 adc_max = <170>;
 322                                 code = <226>;
 323                                 type = <0>;
 324                         };
 325                  };
 326                  keyboard_backlight {
 327                         compatible = "sprd,keyboard-backlight";
 328                  };
 329                                 sprd_kpled_2723 {
 330                                         compatible = "sprd,sprd-kpled-2723";
 331                                         brightness_max = <255>;
 332                                         brightness_min = <0>;
 333                                         run_mode = <0>;
 334                                 };
 335                  watchdog@40{
 336                         compatible = "sprd,watchdog";
 337                         reg = <0X40 0x40>;
 338                         interrupts = <3 0x0>;
 339                  };
 340                  rtc@80{
 341                         compatible = "sprd,rtc";
 342                         reg = <0X80 0x80>;
 343                         interrupts = <2 0x0>;
 344                 };
 345                  a_eic_gpio: gpio@100{
 346                          compatible = "sprd,a-eic-gpio";
 347                          reg = <0X100 0x80>; /* adi reg */
 348                          gpio-controller;
 349                          interrupt-controller;
 350                          #interrupt-cells = <2>;
 351                          #gpio-cells = <2>;
 352                          gpiobase = <304>;
 353                          ngpios = <16>;
 354                          interrupt-parent = <&adi>;
 355                          interrupts = <5 0x0>; /* ext irq 5 */
 356                  };
 357          };
 358         sprd_pwm_bl {
 359                 compatible = "sprd,sprd_pwm_bl";
 360                 brightness_max = <255>;
 361                 brightness_min = <0>;
 362                 pwm_index = <3>;
 363                 gpio_ctrl_pin = <0>;
 364                 gpio_active_level = <0>;
 365         };
 366          keypad@f5208000{
 367                  compatible = "sprd,sci-keypad";
 368                  reg = <0Xf5208000 0x1000>;
 369                  gpios = <&a_eic_gpio 2 0>;
 370                  interrupts = <0 36 0x0>;
 371                  sprd,keypad-num-rows = <2>;
 372                  sprd,keypad-num-columns = <2>;
 373                  sprd,keypad-rows-choose-hw = <0x30000>;
 374                  sprd,keypad-cols-choose-hw = <0x300>;
 375                  sprd,debounce_time = <5000>;
 376                  linux,keypad-no-autorepeat;
 377                  sprd,support_long_key;
 378
 379                  key_volume_down {
 380                          keypad,row = <0>;
 381                          keypad,column = <0>;
 382                          linux,code = <114>;
 383                  };
 384                  key_volume_up {
 385                          keypad,row = <1>;
 386                          keypad,column = <0>;
 387                          linux,code = <115>;
 388                  };
 389                  key_home {
 390                          keypad,row = <0>;
 391                          keypad,column = <1>;
 392                          linux,code = <102>;
 393                  };
 394          };
 395          sprd_vsp@f5300000{
 396                  compatible = "sprd,sprd_vsp";
 397                  reg = <0Xf5300000 0xc000>;
 398                  interrupts = <0 43 0x0>;
 399                  clock-names = "clk_mm_i", "clk_vsp", "clk_mm_axi";
 400                  clocks = <&clk_mm>, <&clk_vsp>, <&clk_mm_axi>;
 401                  version = <0>;
 402          };
 403         sprd_jpg {
 404                  compatible  = "sprd,sprd_jpg";
 405                  reg = <0Xf5320000 0x8000>;
 406                  interrupts = <0 42 0x0>;
 407                  clock-names = "clk_mm_i","clk_jpg";
 408                  clocks = <&clk_mm>, <&clk_jpg>;
 409          };
 410
 411
 412          i2c0: i2c@f536a000{
 413                  compatible  = "sprd,i2c";
 414                  interrupts = <0 11 0x0>;
 415                  reg = <0xf536a000 0x1000>;
 416                  #address-cells = <1>;
 417                  #size-cells = <0>;
 418                  sensor_main@0x3c{
 419                         compatible = "sprd,sensor_main";
 420                         reg = <0x3c>;
 421                  };
 422                  sensor_sub@0x21{
 423                         compatible = "sprd,sensor_sub";
 424                         reg = <0x21>;
 425                  };
 426          };
 427          i2c1: i2c@f536c000{
 428                  compatible  = "sprd,i2c";
 429                  interrupts = <0 12 0x0>;
 430                  reg = <0xf536c000 0x1000>;
 431                  #address-cells = <1>;
 432                  #size-cells = <0>;
 433                 focaltech_ts@38{
 434                         compatible = "focaltech,focaltech_ts";
 435                         reg = <0x38>;
 436                         gpios = <&d_gpio_gpio 81 0
 437                                 &d_gpio_gpio 82 0>;
 438                         vdd_name = "vdd28";
 439                         virtualkeys = <100 1020 80 65
 440                                  280 1020 80 65
 441                                  470 1020 80 65>;
 442                         TP_MAX_X = <720>;
 443                         TP_MAX_Y = <1280>;
 444                 };
 445          };
 446          i2c2: i2c@f5370000{
 447                  compatible  = "sprd,i2c";
 448                  interrupts = <0 13 0x0>;
 449                  reg = <0xf5370000 0x1000>;
 450                  #address-cells = <1>;
 451                  #size-cells = <0>;
 452                 lis3dh_acc@18{
 453                         compatible = "ST,lis3dh_acc";
 454                         reg = <0x18>;
 455                         poll_interval = <10>;
 456                         min_interval = <10>;
 457                         g_range = <0>;
 458                         axis_map_x = <1>;
 459                         axis_map_y = <0>;
 460                         axis_map_z = <2>;
 461                         negate_x = <0>;
 462                         negate_y = <1>;
 463                         negate_z = <0>;
 464                 };
 465                 ltr_558als@23{
 466                         compatible = "LITEON,ltr_558als";
 467                         reg = <0x23>;
 468                         gpios = <&d_gpio_gpio 216 0>;
 469                 };
 470          };
 471          i2c3: i2c@f5372000{
 472                  compatible  = "sprd,i2c";
 473                  interrupts = <0 14 0x0>;
 474                  reg = <0xf5372000 0x1000>;
 475                  #address-cells = <1>;
 476                  #size-cells = <0>;
 477                 fairchild_fan5405@6a{
 478                         compatible = "fairchild,fairchild_fan5405";
 479                         reg = <0x6a>;
 480                 };
 481          };
 482          sprd_dcam{
 483                  compatible  = "sprd,sprd_dcam";
 484                  interrupts = <0 45 0>;
 485                  reg = <0xf52f0000 0x100000>;
 486                  clock-names = "clk_mm_i","clk_dcam";
 487                  clocks = <&clk_mm>, <&clk_dcam>;
 488          };
 489          sprd_scale {
 490                  compatible  = "sprd,sprd_scale";
 491          };
 492          sprd_rotation {
 493                  compatible  = "sprd,sprd_rotation";
 494          };
 495          sprd_sensor {
 496                  compatible  = "sprd,sprd_sensor";
 497                  gpios = <&d_gpio_gpio 186 0   /*main reset*/
 498                         &d_gpio_gpio 187 0     /*main power down*/
 499                         &d_gpio_gpio 186 0    /*sub reset*/
 500                         &d_gpio_gpio 188 0    /*sub power down*/
 501                         &d_gpio_gpio 0 0      /*main core voltage*/
 502                         &d_gpio_gpio 0 0
 503                         &d_gpio_gpio 0 0
 504                         &d_gpio_gpio 0 0>;
 505                  clock-names ="clk_mm_i","clk_sensor","clk_ccir","clk_dcam","clk_dcam_mipi";
 506                  clocks = <&clk_mm>, <&clk_sensor>,<&clk_ccir>, <&clk_dcam>, <&clk_dcam_mipi>;
 507                  };
 508          sprd_isp {
 509                  compatible  = "sprd,sprd_isp";
 510                  clock-names = "clk_mm_i","clk_isp";
 511                  clocks = <&clk_mm>, <&clk_isp>;
 512          };
 513          sprd_dma_copy {
 514                  compatible  = "sprd,sprd_dma_copy";
 515          };
 516         fb0: fb@20800000 {
 517                 compatible = "sprd,sprdfb";
 518                 reg = <0xf5122000 0x1000>,<0xf5146000 0x1000>;
 519                 interrupts = <0 46 0x0>,<0 48 0x0>, <0 49 0x0>;
 520                 clock-names = "dispc_clk_parent", "dispc_dbi_clk_parent", "dispc_dpi_clk_parent", "dispc_emc_clk_parent", "dispc_clk", "dispc_dbi_clk", "dispc_dpi_clk", "dispc_emc_clk", "fb_spi_clock", "fb_spi_clock_parent";
 521                 clocks = <&clk_256m>, <&clk_256m>, <&clk_384m>, <&clk_aon_apb>, <&clk_dispc0>, <&clk_dispc0_dbi>, <&clk_dispc0_dpi>, <&clk_disp_emc>, <&clk_spi2>, <&ext_26m>;
 522                 clock-src = <256000000 256000000 384000000>;
 523                 dpi_clk_div = <7>;
 524                 sprd,fb_use_reservemem;
 525                 sprd,fb_mem = <0x9F311000 0x5EF000>;
 526         };
 527         gsp:gsp@20a00000 {
 528                 compatible = "sprd,gsp";
 529                 reg = <0xf5126000 0x1000>;
 530                 interrupts = <0 51 0x0>;
 531                 clock-names = "clk_gsp", "clk_gsp_emc", "clk_gsp_parent", "clk_aon_apb";
 532                 clocks = <&clk_gsp>, <&clk_gsp_emc>, <&clk_256m>, <&clk_aon_apb>;
 533                 gsp_mmu_ctrl_base = <0xf5418000>;
 534         };
 535
 536         sprd_fm: sprd_fm@40270000{
 537                 compatible  = "sprd,sprd_fm";
 538                 reg = <0xf5210000 0x1000>,
 539                                 <0xf5250000 0x10000>,
 540                 <0xf5230000 0x10000>,
 541                 <0xf5242000 0x10000>;
 542         };
 543
 544         /* sipc initializer */
 545
 546         sipc: sipc@0x87800000 {
 547                 compatible = "sprd,sipc";
 548                 reg = <0x87800000 0x200000>; /* <SMEM SIZE>*/
 549                 //#interrupt-cells = <2>;
 550                 #address-cells = <1>;
 551                 #size-cells = <1>;
 552                 ranges = <0x8000000 0x88000000 0x1b00000>,
 553                                 <0x07800000 0x87800000 0x140000>,
 554                                 <0x9aff000 0x89aff000 0x1000>,
 555                                 <0x0a800000 0x8a800000 0x201000>,/*WCN MEMORY:OFFSET ADDRESS SIZE*/
 556                                 <0x07940000 0x87940000 0xc0000>,
 557                                 <0x0aa00000 0x8aa00000 0x1000>;/*WCN SIPC-RING:OFFSET ADDRESS SIZE*/
 558                 sipc_cpw@0x8000000 {
 559                         sprd,name = "sipc-w";
 560                         sprd,dst = <2>;
 561                         sprd,ap2cp = <0xf5240000>; /* base on ipi reggister */
 562                         sprd,cp2ap = <0xf5240004>;
 563                         sprd,trig = <0x01>; /* trigger bit */
 564                         sprd,clr = <0x01>; /* clear bit */
 565                         interrupts = <0 68 0x0>;
 566                         reg = <0x8000000 0x1b00000> , /* <CP_start_addr size> */
 567                                 <0x07800000 0x140000>, /* <SMEM_phy_addr total_size> */
 568                                 <0x9aff000 0x1000>; /* smsg ring buffer <base size> */
 569                 };
 570                 sipc_wcn@0x0a800000 {
 571                         sprd,name = "sipc-wcn";
 572                         sprd,dst = <3>;
 573                         sprd,ap2cp = <0xf5240000>; /* base on ipi reggister */
 574                         sprd,cp2ap = <0xf5240004>;
 575                         sprd,trig = <0x100>; /* trigger bit */
 576                         sprd,clr = <0x100>; /* clear bit */
 577                         interrupts = <0 73 0x0>;
 578                         reg = <0x0a800000 0x201000> , /* <CP_start_addr size> */
 579                                 <0x07940000 0xc0000>, /* <SMEM_phy_addr total_size> */
 580                                 <0x0aa00000 0x1000>; /* smsg ring buffer <base size> */
 581                 };
 582
 583         };
 584
 585
 586         /* cpw virtual devices */
 587
 588         spipe-cpw {
 589                 compatible = "sprd,spipe";
 590                 sprd,name = "spipe_w";
 591                 sprd,dst = <2>;
 592                 sprd,channel = <4>;
 593                 sprd,ringnr = <9>;
 594                 sprd,size-rxbuf = <0x1000>; /* 4*1024 */
 595                 sprd,size-txbuf = <0x1000>; /* 4*1024 */
 596         };
 597
 598         slog-cpw {
 599                 compatible = "sprd,spipe";
 600                 sprd,name = "slog_w";
 601                 sprd,dst = <2>;
 602                 sprd,channel = <5>;
 603                 sprd,ringnr = <1>;
 604                 sprd,size-rxbuf = <0x40000>; /* 256*1024*/
 605                 sprd,size-txbuf = <0x8000>; /* 32*1024 */
 606         };
 607
 608         stty-cpw {
 609                 compatible = "sprd,spipe";
 610                 sprd,name = "stty_w";
 611                 sprd,dst = <2>;
 612                 sprd,channel = <6>;
 613                 sprd,ringnr = <32>;
 614                 sprd,size-rxbuf = <0x0800>; /* 2*1024*/
 615                 sprd,size-txbuf = <0x0800>; /* 2*1024 */
 616         };
 617
 618         seth0-cpw {
 619                 compatible = "sprd,seth";
 620                 sprd,name = "seth_w0";
 621                 sprd,dst = <2>;
 622                 sprd,channel = <7>;
 623                 sprd,blknum = <64>;
 624         };
 625
 626         seth1-cpw {
 627                 compatible = "sprd,seth";
 628                 sprd,name = "seth_w1";
 629                 sprd,dst = <2>;
 630                 sprd,channel = <8>;
 631                 sprd,blknum = <64>;
 632         };
 633
 634         seth2-cpw {
 635                 compatible = "sprd,seth";
 636                 sprd,name = "seth_w2";
 637                 sprd,dst = <2>;
 638                 sprd,channel = <9>;
 639                 sprd,blknum = <64>;
 640         };
 641
 642         scproc_cpw: scproc@0x88000000 {
 643                 compatible = "sprd,scproc";
 644                 sprd,name = "cpw";
 645                 sprd,ctrl-reg = <0x44 0x44 0xb0 0xbc>; /* <shut_down deep_sleep reset get_status> */
 646                 sprd,ctrl-mask = <0x02000000 0x10000000 0x01 0xf0000>; /* masks <> */
 647                 sprd,iram-data = <0xe59f0000 0xe12fff10 0x88300000>; /* 3rd param equals modem_addr*/
 648                 reg = <0x88000000 0x1b00000>, /* <CP_start_addr total_size> = <+128M 26M> */
 649                         <0xf53d4000 0x0c>, /* <iram1_base size> */
 650                         <0xf5230000 0x10000>; /* <pmu_base size> */
 651                 interrupts = <0 84 0x0>; /* cp1_wdg_int */
 652                 #address-cells = <1>;
 653                 #size-cells = <1>;
 654                 /* segnr=2 */
 655                 ranges = <0x300000 0x88300000 0x00800000>,
 656                                 <0x20000 0x88020000 0x00220000>;
 657                 modem@0x300000 {
 658                         cproc,name = "modem";
 659                         reg = <0x300000 0x00800000>; /* <modem_addr size> */
 660                 };
 661                 dsp@0x20000 {
 662                         cproc,name = "dsp";
 663                         reg = <0x20000 0x00220000>; /* <dsp_addr size>*/
 664                 };
 665         };
 666
 667         saudio_w{
 668                 compatible = "sprd,saudio";
 669                 sprd,saudio-dst-id = <2>;
 670                 sprd,saudio-names = "saudio_w";
 671         };
 672         saudio_voip{
 673                 compatible = "sprd,saudio";
 674                 sprd,saudio-dst-id = <2>;
 675                 sprd,saudio-names = "saudio_voip";
 676         };
 677
 678         /* cpwcn virtual devices */
 679
 680         spipe_cpwcn {
 681                 compatible = "sprd,spipe";
 682                 sprd,name = "spipe_wcn";
 683                 sprd,dst = <3>;
 684                 sprd,channel = <4>;
 685                 sprd,ringnr = <12>;
 686                 sprd,size-rxbuf = <0x1000>; /* 4*1024 */
 687                 sprd,size-txbuf = <0x1000>; /* 4*1024 */
 688         };
 689
 690         slog_cpwcn {
 691                 compatible = "sprd,spipe";
 692                 sprd,name = "slog_wcn";
 693                 sprd,dst = <3>;
 694                 sprd,channel = <5>;
 695                 sprd,ringnr = <1>;
 696                 sprd,size-rxbuf = <0x40000>; /* 256*1024*/
 697                 sprd,size-txbuf = <0x8000>; /* 32*1024 */
 698         };
 699
 700         stty4bt_cpwcn {
 701                 compatible = "sprd,stty4bt";
 702                 sprd,name = "sttybt";
 703                 sprd,dst = <3>;
 704                 sprd,channel = <4>;
 705                 sprd,bufid = <10>;
 706         };
 707
 708         scproc_cpwcn: scproc@0x8a800000 {
 709                 compatible = "sprd,scproc";
 710                 sprd,name = "cpwcn";
 711                 sprd,ctrl-reg = <0x68 0x68 0xb0 0xb0>; /* <shut_down deep_sleep reset get_status> */
 712                 sprd,ctrl-mask = <0x02000000 0x10000000 0x04 0x04>; /* masks <> */
 713                 sprd,iram-data = <0xe59f0000 0xe12fff10 0x8a808000>; /* 3rd param equals modem_addr*/
 714                 reg = <0x8a800000 0x201000>, /* <CP_start_addr total_size> = <+168M 2M+4k> */
 715                         <0x50003000 0x1000>, /* <iram1_phys size> use iram1 phys because of cp2 iram not maped */
 716                         <0xf5230000 0x10000>; /* <pmu_base size> */
 717                 interrupts = <0 85 0x0>; /* cp2_wdg_int */
 718                 #address-cells = <1>;
 719                 #size-cells = <1>;
 720                 /* segnr=1 */
 721                 ranges = <0x8000 0x8a808000 0x201000>;
 722                 modem@0x8000 {
 723                         cproc,name = "modem";
 724                         reg = <0x8000 0x201000>; /* <modem_addr size> */
 725                 };
 726         };
 727
 728         sprd_wlan{
 729                 compatible = "sprd,sprd_wlan";
 730         };
 731
 732
 733          usb: usb@f5116000{
 734                  compatible  = "sprd,usb";
 735                  interrupts = <0 55 0x0>;
 736                 ngpios = <2>;
 737                 gpios = <&a_eic_gpio 0 0>,<&d_gpio_gpio 72 0>;
 738                  reg = <0xf5116000 0x1000>;
 739                  usb-supply = <&vddusb>;
 740                  #address-cells = <1>;
 741                  #size-cells = <0>;
 742          };
 743         sprd_thermal {
 744                 compatible = "sprd,sprd-thermal";
 745                 id = <0>;
 746                 interrupts = <0 26 0x0>;
 747                 reg = <0x402f0000 0x1000>;
 748                 trip_points_active = <65 69 95 110>;
 749                 trip_points_lowoff = <0 57 61 80>;
 750                 trip_points_critical = <110>;
 751                 trip_num = <5>;
 752         };
 753         sprd_thermal1 {
 754                 compatible = "sprd,sprd-thermal";
 755                 id = <1>;
 756                 interrupt-parent = <&adi>;
 757                 interrupts = <9 0x0>;
 758                 reg = <0xf53f8280 0x1000>;
 759                 trip_points_active = <90>;
 760                 trip_points_critical = <114>;
 761                 trip_num = <2>;
 762         };
 763         sprd_cpu_cooling{
 764                 compatible = "sprd,sprd-cpu-cooling";
 765                 id = <0>;
 766                 max_freq = <1300000 1200000 1000000 768000>;
 767                 max_core = <4 4 4 1>;
 768                 state_num = <4>;
 769         };
 770          spi0: spi@70a00000{
 771                  compatible  = "sprd,sprd-spi";
 772                  interrupts = <0 7 0x0>;
 773                  reg = <0xf5376000 0x1000>;
 774                  clock-names = "clk_spi0";
 775                  #address-cells = <1>;
 776                  #size-cells = <0>;
 777          };
 778          spi1: spi@70b00000{
 779                  compatible  = "sprd,sprd-spi";
 780                  interrupts = <0 8 0x0>;
 781                  reg = <0xf5378000 0x1000>;
 782                  clock-names = "clk_spi1";
 783                  #address-cells = <1>;
 784                  #size-cells = <0>;
 785          };
 786          spi2: spi@70c00000{
 787                  compatible  = "sprd,sprd-spi";
 788                  interrupts = <0 9 0x0>;
 789                  reg = <0xf537a000 0x1000>;
 790                  clock-names = "clk_spi2";
 791                  #address-cells = <1>;
 792                  #size-cells = <0>;
 793          };
 794          dmac: dmac@20100000{
 795                  compatible  = "sprd,sprd-dma";
 796                  interrupts = <0 50 0x0>;
 797                  reg = <0xf5112000 0x4000>;
 798          };
 799          adc: adc@40038300{
 800                  compatible  = "sprd,sprd-adc";
 801                  reg = <0xf53f8300 0x400>;
 802          };
 803          hwspinlock0: hwspinlock0@20c00000{
 804                  compatible  = "sprd,sprd-hwspinlock";
 805                  reg = <0xf512a000 0x1000>;
 806          };
 807          hwspinlock1: hwspinlock1@40060000{
 808                  compatible  = "sprd,sprd-hwspinlock";
 809                  reg = <0xf51f6000 0x1000>;
 810          };
 811          gpu {
 812                  compatible  = "sprd,mali-utgard";
 813                  mali_pp_core_number = <4>;
 814                  interrupt-names =     "mali_gp_irq",
 815                                        "mali_gp_mmu_irq",
 816                                        "mali_pp0_irq",
 817                                        "mali_pp0_mmu_irq",
 818                                        "mali_pp1_irq",
 819                                        "mali_pp1_mmu_irq";
 820                  reg-names       =     "mali_l2",
 821                                        "mali_gp",
 822                                        "mali_gp_mmu",
 823                                        "mali_pp0",
 824                                        "mali_pp0_mmu",
 825                                        "mali_pp1",
 826                                        "mali_pp1_mmu",
 827                                        "mali_pmu";
 828                  interrupts =  <0 39 0x0>,  //  MALI_GP_IRQ,
 829                        <0 39 0x0>,  //  MALI_GP_MMU_IRQ,
 830                        <0 39 0x0>,  //  MALI_PP0_IRQ,
 831                        <0 39 0x0>,  //  MALI_PP0_MMU_IRQ,
 832                        <0 39 0x0>,  //  MALI_PP1_IRQ,
 833                        <0 39 0x0>;  //  MALI_PP1_MMU_IRQ,
 834                  reg = <0x60001000 0x200>,//  MALI_L2,MALI_GPU_RESOURCE_L2(base_addr + 0x1000)
 835                        <0x60000000 0x100>,//  MALI_GP,
 836                        <0x60003000 0x100>,//  MALI_GP_MMU,
 837                        <0x60008000 0x1100>,//  MALI_PP0,
 838                        <0x60004000 0x100>,//  MALI_PP0_MMU,
 839                        <0x6000A000 0x1100>,//  MALI_PP1,
 840                        <0x60005000 0x100>,//  MALI_PP1_MMU,
 841                        <0x60002000 0x100>;//  MALI_PMU,
 842                  clock-names = "clk_gpu_axi","clk_gpu","clk_153m6","clk_208m","clk_256m","clk_312m","clk_384m","clk_460m8";
 843                  clocks = <&clk_gpu_axi>,<&clk_gpu>,<&clk_153m6>,<&clk_208m>,<&clk_256m>,<&clk_312m>,<&clk_384m>,<&clk_460m8>;
 844          };
 845          ion {
 846                  compatible = "sprd,ion-sprd";
 847                  #address-cells = <1>;
 848                  #size-cells = <0>;
 849
 850                  sprd,ion-heap@1 {
 851                        reg = <1>;                      /* SYSTEM */
 852                        reg-names = "ion_heap_system";
 853                        sprd,ion-heap-type = <0>;       /* SYSTEM */
 854                        sprd,ion-heap-mem = <0x0 0x0>;
 855                  };
 856
 857                  sprd,ion-heap@2 {
 858                        reg = <2>;                      /* MM */
 859                        reg-names = "ion_heap_carveout_mm";
 860                        sprd,ion-heap-type = <0>;       /* carveout mm */
 861                        sprd,ion-heap-mem = <0x98800000 0x7100000>;
 862                  };
 863
 864                  sprd,ion-heap@3 {
 865                        reg = <3>;                      /* OVERLAY */
 866                        reg-names = "ion_heap_carveout_overlay";
 867                        sprd,ion-heap-type = <2>;       /* CARVEOUT */
 868                        sprd,ion-heap-mem = <0x9f900000 0x700000>;      /* 7M */
 869                  };
 870          };
 871          sprd_iommu0:sprd_iommu@F5410000 {
 872                  compatible  = "sprd,sprd_iommu";//gsp
 873                  func-name = "sprd_iommu_gsp";
 874                  reg = <0x10000000 0x2000000>, //iova
 875                        <0xF5410000 0x8000>,  //pgt
 876                        <0xF5418000 0x8000>;  //ctrl_reg
 877                  reg_name = "iova","pgt","ctrl_reg";
 878                  clock-names = "clk_gsp_emc","clk_153m6","clk_gsp";
 879                  clocks = <&clk_gsp_emc>, <&clk_153m6>,<&clk_gsp>;
 880                  status = "ok";
 881          };
 882          sprd_iommu1:sprd_iommu@F5430000 {
 883                  compatible  = "sprd,sprd_iommu";//mm
 884                  func-name = "sprd_iommu_mm";
 885                  reg = <0x20000000 0x8000000>,   //iova
 886                        <0xF5430000 0x20000>,     //pgt
 887                        <0xF5450000 0x2000>;      //ctrl_reg
 888                  reg_name = "iova","pgt","ctrl_reg";
 889                  clock-names = "clk_mmu","clk_mm_i","clk_mm_axi";
 890                  clocks = <&clk_mmu>,<&clk_mm>,<&clk_mm_axi>;
 891                  status = "ok";
 892          };
 893          sprd_rf2351: sprd_rf2351@40070000{
 894                 compatible  = "sprd,sprd_rf2351";
 895                 reg = <0xf51f8000 0x1000>,              /*RFSPI*/
 896                         <0xf5250000 0x10000>;           /*APB_EB0*/
 897                 clock-names = "clk_cpll";
 898                 clocks = <&clk_cpll>;
 899          };
 900          gps_2351: gps_2351@21c00000{
 901                 compatible  = "sprd,gps_2351";
 902                 interrupts = <0 52 0x0>;
 903                 gpios = <&d_gpio_gpio 50 0>;
 904                 reg = <0xf5150000 0x1000>,              /*GPS CORE BASE*/
 905                         <0xf5130000 0x10000>,           /*AHB_ADDR*/
 906                         <0xf5230000 0x10000>;           /*PMU BASE*/
 907          };
 908 };
 909
 910 &vbc_r2p0 {
 911         status = "okay";
 912 };
 913
 914 &sprd_codec {
 915         status = "okay";
 916         sprd,audio_power_ver = <4>;
 917 };
 918
 919 &i2s0 {
 920         status = "okay";
 921 };
 922
 923 &i2s1 {
 924         status = "okay";
 925 };
 926
 927 &i2s2 {
 928         status = "okay";
 929 };
 930
 931 &i2s3 {
 932         status = "okay";
 933 };
 934
 935 &i2s_sound {
 936         sprd,i2s = <&i2s0>, <&i2s1>, <&i2s2>, <&i2s3>;
 937 };