arch/arm/boot/dts/sprd-scx35_sp7731gga_lc.dts

   1 /*
   2 * Copyright (C) 2013 Spreadtrum Communication Incorporated
   3 *               http://www.spreadtrum.com/
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License version 2 as
   7 * published by the Free Software Foundation.
   8 */
   9 /dts-v1/;
  10
  11 /* memory reserved for SMEM */
  12 /memreserve/ 0x87800000 0x200000; /* 2MK */
  13
  14 /* memory reserved for CPW modem */
  15 /memreserve/ 0x88000000 0x1b00000; /* 27M */
  16
  17 /* memory reserved for CPWCN modem */
  18 /memreserve/ 0x8a800000 0x201000;/*Offset:168M, SIZE:2M+4k*/
  19
  20 /* memory reserved for fb */
  21 /memreserve/ 0x8F8DF000 0x321000; /* 480*854*4*2, 4K alignment */
  22
  23 /* memory reserved for ION */
  24 /memreserve/ 0x8fc00000 0x0; /* 0MK */
  25
  26 /include/ "skeleton.dtsi"
  27 /include/ "scx30g-clocks.dtsi"
  28 /include/ "scx30g-regulators.dtsi"
  29 /include/ "sprd-sound.dtsi"
  30 /include/ "sprd-battery.dtsi"
  31
  32 / {
  33         model = "Spreadtrum SP8835EB board";
  34         compatible = "sprd,sp8835eb";
  35         sprd,sc-id = <8830 1 0x20000>;
  36         #address-cells = <1>;
  37         #size-cells = <1>;
  38         interrupt-parent = <&gic>;
  39
  40         chosen {
  41                 bootargs = "loglevel=1 console=ttyS1,115200n8 init=/init root=/dev/ram0 rw vmalloc=756M";
  42                 linux,initrd-start = <0x85500000>;
  43                 linux,initrd-end   = <0x855a3212>;
  44         };
  45
  46         memory {
  47                 device_type = "memory";
  48                 reg = <0x80000000 0x10000000>;
  49         };
  50
  51         aliases {
  52                 serial0 = &uart0;
  53                 serial1 = &uart1;
  54                 serial2 = &uart2;
  55                 serial3 = &uart3;
  56                 i2c0 = &i2c0;
  57                 i2c1 = &i2c1;
  58                 i2c2 = &i2c2;
  59                 i2c3 = &i2c3;
  60                 lcd0 = &fb0;
  61                 spi0 = &spi0;
  62                 spi1 = &spi1;
  63                 spi2 = &spi2;
  64                 hwspinlock0 = &hwspinlock0;
  65                 hwspinlock1 = &hwspinlock1;
  66         };
  67
  68         cpus {
  69                 #address-cells = <1>;
  70                 #size-cells = <0>;
  71
  72                 cpu@f00 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a7";
  75                         reg = <0xf00>;
  76                 };
  77
  78                 cpu@f01 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a7";
  81                         reg = <0xf01>;
  82                 };
  83
  84                 cpu@f02 {
  85                         device_type = "cpu";
  86                         compatible = "arm,cortex-a7";
  87                         reg = <0xf02>;
  88                 };
  89
  90                 cpu@f03 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a7";
  93                         reg = <0xf03>;
  94                 };
  95         };
  96         pmu {
  97                 compatible = "arm,cortex-a7-pmu";
  98                 interrupts = <0 92 0x400>,
  99                                 <0 93 0x400>,
 100                                 <0 94 0x400>,
 101                                 <0 95 0x400>;
 102         };
 103
 104     gic: interrupt-controller@12001000 {
 105         compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
 106         #interrupt-cells = <3>;
 107         #address-cells = <0>;
 108         interrupt-controller;
 109         reg = <0x12001000 0x1000>,
 110               <0x12002000 0x1000>;
 111     };
 112
 113          uart0: uart@f5360000{
 114                  compatible  = "sprd,serial";
 115                  interrupts = <0 2 0x0>;
 116                  reg = <0xf5360000 0x1000>;
 117                  clock-names = "clk_uart0";
 118                  clocks = <&clock 60>;
 119                  sprdclk = <48000000>;
 120                  sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP";
 121          };
 122          uart1: uart@f5362000{
 123                  compatible  = "sprd,serial";
 124                  interrupts = <0 3 0x0>;
 125                  reg = <0xf5362000 0x1000>;
 126                  clock-names = "clk_uart1";
 127                  clocks = <&clock 61>;
 128                  sprdclk = <26000000>;
 129                  sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP";
 130          };
 131          uart2: uart@f5364000{
 132                  compatible  = "sprd,serial";
 133                  interrupts = <0 4 0x0>;
 134                  reg = <0xf5364000 0x1000>;
 135                  clock-names = "clk_uart2";
 136                  clocks = <&clock 62>;
 137                  sprdclk = <26000000>;
 138                  sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP";
 139          };
 140          uart3: uart@f5366000{
 141                  compatible  = "sprd,serial";
 142                  interrupts = <0 5 0x0>;
 143                  reg = <0xf5366000 0x1000>;
 144                  clock-names = "clk_uart3";
 145                  clocks = <&clock 63>;
 146                  sprdclk = <26000000>;
 147                  sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP";
 148          };
 149
 150          timer{
 151                  compatible  = "sprd,scx35-timer";
 152                  reg = <0xf5204000 0x1000>,
 153                          <0xf51f4000 0x1000>,
 154                          <0xf5202000 0x1000>,
 155                          <0xf5292000 0x1000>,
 156                          <0xf5294000 0x1000>;
 157                  interrupts = <0 118 0x0>,
 158                                         <0 28 0x0>,
 159                                         <0 29 0x0>,
 160                                         <0 119 0x0>,
 161                                         <0 121 0x0>;
 162          };
 163          clock: clockdevice{
 164                  compatible = "sprd,scx35-clock";
 165                 #clock-cells = <1>;
 166          };
 167          d_eic_gpio: gpio@f5200000{
 168                  compatible = "sprd,d-eic-gpio";
 169                  reg = <0Xf5200000 0x1000>;
 170                  gpio-controller;
 171                  interrupt-controller;
 172                  #interrupt-cells = <2>;
 173                  #gpio-cells = <2>;
 174                  gpiobase = <288>;
 175                  ngpios = <16>;
 176                  interrupts = <0 37 0x0>;
 177          };
 178          d_gpio_gpio: gpio@f5220000{
 179                  compatible = "sprd,d-gpio-gpio";
 180                  reg = <0Xf5220000 0x1000>;
 181                  gpio-controller;
 182                  interrupt-controller;
 183                  #interrupt-cells = <2>;
 184                  #gpio-cells = <2>;
 185                  gpiobase = <0>;
 186                  ngpios = <256>;
 187                  interrupts = <0 35 0x0>;
 188          };
 189         pinctrl{
 190                 compatible = "sprd,pinctrl";
 191                 reg = <0xf5224000 0x1000>;
 192                 pwr_domain = "vdd28",
 193                                          "vdd28",
 194                                          "vddsim0",
 195                                          "vddsim1",
 196                                          "vddsim2",
 197                                          "vddsd",
 198                                          "vdd18";
 199                 ctrl_desc = <0x10 0 1
 200                                     0x10 1 1
 201                                     0x10 2 1
 202                                     0x10 3 1
 203                                     0x10 4 1
 204                                     0x10 5 1
 205                                     0x10 6 1>;
 206         };
 207         adic:adic{
 208                 compatible = "sprd,adic";
 209                 reg = <0Xf53f0000 0x1000>;
 210         };
 211          adi: adi_bus{
 212                  compatible = "sprd,adi-bus";
 213                  interrupts = <0 38 0x0>;
 214                  reg = <0Xf53f8000 0x1000>;
 215                  interrupt-controller;
 216                  sprd,irqnums = <11>;
 217                  #interrupt-cells = <2>;
 218                  #address-cells = <1>;
 219                  #size-cells = <1>;
 220                  ranges = <0X40 0Xf53f8040 0x40>,
 221                                   <0X80 0Xf53f8080 0x80>,
 222                                   <0X100 0Xf53f8100 0x80>,
 223                                   <0X480 0Xf53f8480 0x80>;
 224                  sprd_backlight {
 225                         compatible = "sprd,sprd_backlight";
 226                         start = <3>;
 227                         end = <3>;
 228                         flags = <0x100>;
 229                  };
 230                  headset_detect {
 231                         compatible = "sprd,headset-detect";
 232                         gpio_switch = <0>;
 233                         gpio_detect = <309>;
 234                         gpio_button = <307>;
 235                         irq_trigger_level_detect = <1>;
 236                         irq_trigger_level_button = <1>;
 237                         adc_threshold_3pole_detect = <100>;
 238                         adc_threshold_4pole_detect = <3100>;
 239                         irq_threshold_buttont = <1>;
 240                         voltage_headmicbias = <3000000>;
 241                         nbuttons = <1>;
 242                         headset_buttons {
 243                                 adc_min = <0>;
 244                                 adc_max = <170>;
 245                                 code = <226>;
 246                                 type = <0>;
 247                         };
 248                  };
 249                  keyboard_backlight {
 250                         compatible = "sprd,keyboard-backlight";
 251                  };
 252                  watchdog@40{
 253                         compatible = "sprd,watchdog";
 254                         reg = <0X40 0x40>;
 255                         interrupts = <3 0x0>;
 256                  };
 257                  rtc@80{
 258                         compatible = "sprd,rtc";
 259                         reg = <0X80 0x80>;
 260                         interrupts = <2 0x0>;
 261                 };
 262                  a_eic_gpio: gpio@100{
 263                          compatible = "sprd,a-eic-gpio";
 264                          reg = <0X100 0x80>; /* adi reg */
 265                          gpio-controller;
 266                          interrupt-controller;
 267                          #interrupt-cells = <2>;
 268                          #gpio-cells = <2>;
 269                          gpiobase = <304>;
 270                          ngpios = <16>;
 271                          interrupt-parent = <&adi>;
 272                          interrupts = <5 0x0>; /* ext irq 5 */
 273                  };
 274                  a_gpio_gpio: gpio@480{
 275                          compatible = "sprd,a-gpio-gpio";
 276                          reg = <0X480 0x80>; /* adi reg */
 277                          gpio-controller;
 278                          interrupt-controller;
 279                          #interrupt-cells = <2>;
 280                          #gpio-cells = <2>;
 281                          gpiobase = <256>;
 282                          ngpios = <32>;
 283                          interrupt-parent = <&adi>;
 284                          interrupts = <1 0x0>; /* ext irq 1 */
 285                  };
 286          };
 287          keypad@f5208000{
 288                  compatible = "sprd,sci-keypad";
 289                  reg = <0Xf5208000 0x1000>;
 290                  gpios = <&a_eic_gpio 2 0>;
 291                  interrupts = <0 36 0x0>;
 292                  sprd,keypad-num-rows = <2>;
 293                  sprd,keypad-num-columns = <2>;
 294                  sprd,keypad-rows-choose-hw = <0x30000>;
 295                  sprd,keypad-cols-choose-hw = <0x300>;
 296                  sprd,debounce_time = <5000>;
 297                  linux,keypad-no-autorepeat;
 298                  sprd,support_long_key;
 299
 300                  key_volume_down {
 301                          keypad,row = <0>;
 302                          keypad,column = <0>;
 303                          linux,code = <114>;
 304                  };
 305                  key_volume_up {
 306                          keypad,row = <1>;
 307                          keypad,column = <0>;
 308                          linux,code = <115>;
 309                  };
 310                  key_home {
 311                          keypad,row = <0>;
 312                          keypad,column = <1>;
 313                          linux,code = <102>;
 314                  };
 315          };
 316          sprd_vsp@f5300000{
 317                  compatible = "sprd,sprd_vsp";
 318                  reg = <0Xf5300000 0xc000>;
 319                  interrupts = <0 43 0x0>;
 320                  clock-names = "clk_mm_i", "clk_vsp";
 321                  clocks = <&clk_mm>, <&clk_vsp>;
 322                  version = <2>;
 323          };
 324         sprd_jpg {
 325                  compatible  = "sprd,sprd_jpg";
 326                  reg = <0Xf5320000 0x8000>;
 327                  interrupts = <0 42 0x0>;
 328                  clock-names = "clk_mm_i","clk_jpg";
 329                  clocks = <&clk_mm>, <&clk_jpg>;
 330          };
 331
 332
 333          i2c0: i2c@f536a000{
 334                  compatible  = "sprd,i2c";
 335                  interrupts = <0 11 0x0>;
 336                  reg = <0xf536a000 0x1000>;
 337                  #address-cells = <1>;
 338                  #size-cells = <0>;
 339                  sensor_main@0x3c{
 340                         compatible = "sprd,sensor_main";
 341                         reg = <0x3c>;
 342                  };
 343                  sensor_sub@0x21{
 344                         compatible = "sprd,sensor_sub";
 345                         reg = <0x21>;
 346                  };
 347          };
 348          i2c1: i2c@f536c000{
 349                  compatible  = "sprd,i2c";
 350                  interrupts = <0 12 0x0>;
 351                  reg = <0xf536c000 0x1000>;
 352                  #address-cells = <1>;
 353                  #size-cells = <0>;
 354                 focaltech_ts@38{
 355                         compatible = "focaltech,focaltech_ts";
 356                         reg = <0x38>;
 357                         gpios = <&d_gpio_gpio 81 0
 358                                 &d_gpio_gpio 82 0>;
 359                         vdd_name = "vdd28";
 360                         virtualkeys = <100 1020 80 65
 361                                 280 1020 80 65
 362                                 470 1020 80 65>;
 363                         TP_MAX_X = <640>;
 364                         TP_MAX_Y = <1138>;
 365                 };
 366          };
 367          i2c2: i2c@f5370000{
 368                  compatible  = "sprd,i2c";
 369                  interrupts = <0 13 0x0>;
 370                  reg = <0xf5370000 0x1000>;
 371                  #address-cells = <1>;
 372                  #size-cells = <0>;
 373                 lis3dh_acc@18{
 374                         compatible = "ST,lis3dh_acc";
 375                         reg = <0x18>;
 376                         poll_interval = <10>;
 377                         min_interval = <10>;
 378                         g_range = <0>;
 379                         axis_map_x = <1>;
 380                         axis_map_y = <0>;
 381                         axis_map_z = <2>;
 382                         negate_x = <0>;
 383                         negate_y = <1>;
 384                         negate_z = <0>;
 385                 };
 386                 ltr_558als@23{
 387                         compatible = "LITEON,ltr_558als";
 388                         reg = <0x23>;
 389                         gpios = <&d_gpio_gpio 216 0>;
 390                 };
 391          };
 392          i2c3: i2c@f5372000{
 393                  compatible  = "sprd,i2c";
 394                  interrupts = <0 14 0x0>;
 395                  reg = <0xf5372000 0x1000>;
 396                  #address-cells = <1>;
 397                  #size-cells = <0>;
 398          };
 399          sprd_dcam{
 400                  compatible  = "sprd,sprd_dcam";
 401                  interrupts = <0 45 0>;
 402                  reg = <0xf52f0000 0x100000>;
 403                  clock-names = "clk_mm_i","clk_dcam";
 404                  clocks = <&clk_mm>, <&clk_dcam>;
 405          };
 406          sprd_scale {
 407                  compatible  = "sprd,sprd_scale";
 408          };
 409          sprd_rotation {
 410                  compatible  = "sprd,sprd_rotation";
 411          };
 412          sprd_sensor {
 413                  compatible  = "sprd,sprd_sensor";
 414                  reg = <0x60c00000 0x100000>;
 415                  gpios = <&d_gpio_gpio 186 0   /*main reset*/
 416                         &d_gpio_gpio 187 0    /*main power down*/
 417                         &d_gpio_gpio 186 0    /*sub reset */
 418                         &d_gpio_gpio 188 0    /*sub power down*/
 419                         &d_gpio_gpio 0 0      /*main core voltage*/
 420                         &d_gpio_gpio 0 0
 421                         &d_gpio_gpio 0 0
 422                         &d_gpio_gpio 0 0>;
 423                  clock-names ="clk_mm_i","clk_sensor","clk_ccir","clk_dcam","clk_dcam_mipi";
 424                  clocks = <&clk_mm>, <&clk_sensor>,<&clk_ccir>, <&clk_dcam>, <&clk_dcam_mipi>;
 425                  };
 426          sprd_isp {
 427                  compatible  = "sprd,sprd_isp";
 428                  clock-names = "clk_mm_i","clk_isp";
 429                  clocks = <&clk_mm>, <&clk_isp>;
 430          };
 431          sprd_dma_copy {
 432                  compatible  = "sprd,sprd_dma_copy";
 433          };
 434         fb0: fb@20800000 {
 435                 compatible = "sprd,sprdfb";
 436                 reg = <0xf5122000 0x1000>,<0xf5146000 0x1000>;
 437                 interrupts = <0 46 0x0>,<0 48 0x0>, <0 49 0x0>;
 438                 clock-names = "dispc_clk_parent", "dispc_dbi_clk_parent", "dispc_dpi_clk_parent", "dispc_emc_clk_parent", "dispc_clk", "dispc_dbi_clk", "dispc_dpi_clk", "dispc_emc_clk", "fb_spi_clock", "fb_spi_clock_parent";
 439                 clocks = <&clk_256m>, <&clk_256m>, <&clk_384m>, <&clk_aon_apb>, <&clk_dispc0>, <&clk_dispc0_dbi>, <&clk_dispc0_dpi>, <&clk_disp_emc>, <&clk_spi2>, <&ext_26m>;
 440                 clock-src = <256000000 256000000 384000000>;
 441                 dpi_clk_div = <7>;
 442                 sprd,fb_use_reservemem;
 443                 sprd,fb_mem = <0x8F8DF000 0x321000>;
 444                 sprd,fb_display_size = <480 854>;
 445         };
 446         gsp:gsp@20a00000 {
 447                 compatible = "sprd,gsp";
 448                 reg = <0xf5126000 0x1000>;
 449                 interrupts = <0 51 0x0>;
 450                 clock-names = "clk_gsp", "clk_gsp_emc", "clk_gsp_parent", "clk_aon_apb";
 451                 clocks = <&clk_gsp>, <&clk_gsp_emc>, <&clk_256m>, <&clk_aon_apb>;
 452                 gsp_mmu_ctrl_base = <0xf5418000>;
 453         };
 454
 455         sprd_fm: sprd_fm@40270000{
 456                 compatible  = "sprd,sprd_fm";
 457                 reg = <0xf5210000 0x1000>,
 458                                 <0xf5250000 0x10000>,
 459                 <0xf5230000 0x10000>,
 460                 <0xf5242000 0x10000>;
 461         };
 462
 463         /* sipc initializer */
 464
 465         sipc: sipc@0x87800000 {
 466                 compatible = "sprd,sipc";
 467                 reg = <0x87800000 0x200000>; /* <SMEM SIZE>*/
 468                 //#interrupt-cells = <2>;
 469                 #address-cells = <1>;
 470                 #size-cells = <1>;
 471                 ranges = <0x8000000 0x88000000 0x1b00000>,
 472                                 <0x07800000 0x87800000 0x140000>,
 473                                 <0x9aff000 0x89aff000 0x1000>,
 474                                 <0x0a800000 0x8a800000 0x201000>,/*WCN MEMORY:OFFSET ADDRESS SIZE*/
 475                                 <0x07940000 0x87940000 0xc0000>,
 476                                 <0x0aa00000 0x8aa00000 0x1000>;/*WCN SIPC-RING:OFFSET ADDRESS SIZE*/
 477                 sipc_cpw@0x8000000 {
 478                         sprd,name = "sipc-w";
 479                         sprd,dst = <2>;
 480                         sprd,ap2cp = <0xf5240000>; /* base on ipi reggister */
 481                         sprd,cp2ap = <0xf5240004>;
 482                         sprd,trig = <0x01>; /* trigger bit */
 483                         sprd,clr = <0x01>; /* clear bit */
 484                         interrupts = <0 68 0x0>;
 485                         reg = <0x8000000 0x1b00000> , /* <CP_start_addr size> */
 486                                 <0x07800000 0x140000>, /* <SMEM_phy_addr total_size> */
 487                                 <0x9aff000 0x1000>; /* smsg ring buffer <base size> */
 488                 };
 489                 sipc_wcn@0x0a800000 {
 490                         sprd,name = "sipc-wcn";
 491                         sprd,dst = <3>;
 492                         sprd,ap2cp = <0xf5240000>; /* base on ipi reggister */
 493                         sprd,cp2ap = <0xf5240004>;
 494                         sprd,trig = <0x100>; /* trigger bit */
 495                         sprd,clr = <0x100>; /* clear bit */
 496                         interrupts = <0 73 0x0>;
 497                         reg = <0x0a800000 0x201000> , /* <CP_start_addr size> */
 498                                 <0x07940000 0xc0000>, /* <SMEM_phy_addr total_size> */
 499                                 <0x0aa00000 0x1000>; /* smsg ring buffer <base size> */
 500                 };
 501
 502         };
 503
 504
 505         /* cpw virtual devices */
 506
 507         spipe-cpw {
 508                 compatible = "sprd,spipe";
 509                 sprd,name = "spipe_w";
 510                 sprd,dst = <2>;
 511                 sprd,channel = <4>;
 512                 sprd,ringnr = <9>;
 513                 sprd,size-rxbuf = <0x1000>; /* 4*1024 */
 514                 sprd,size-txbuf = <0x1000>; /* 4*1024 */
 515         };
 516
 517         slog-cpw {
 518                 compatible = "sprd,spipe";
 519                 sprd,name = "slog_w";
 520                 sprd,dst = <2>;
 521                 sprd,channel = <5>;
 522                 sprd,ringnr = <1>;
 523                 sprd,size-rxbuf = <0x40000>; /* 256*1024*/
 524                 sprd,size-txbuf = <0x8000>; /* 32*1024 */
 525         };
 526
 527         stty-cpw {
 528                 compatible = "sprd,spipe";
 529                 sprd,name = "stty_w";
 530                 sprd,dst = <2>;
 531                 sprd,channel = <6>;
 532                 sprd,ringnr = <32>;
 533                 sprd,size-rxbuf = <0x0800>; /* 2*1024*/
 534                 sprd,size-txbuf = <0x0800>; /* 2*1024 */
 535         };
 536
 537         seth0-cpw {
 538                 compatible = "sprd,seth";
 539                 sprd,name = "seth_w0";
 540                 sprd,dst = <2>;
 541                 sprd,channel = <7>;
 542                 sprd,blknum = <64>;
 543         };
 544
 545         seth1-cpw {
 546                 compatible = "sprd,seth";
 547                 sprd,name = "seth_w1";
 548                 sprd,dst = <2>;
 549                 sprd,channel = <8>;
 550                 sprd,blknum = <64>;
 551         };
 552
 553         seth2-cpw {
 554                 compatible = "sprd,seth";
 555                 sprd,name = "seth_w2";
 556                 sprd,dst = <2>;
 557                 sprd,channel = <9>;
 558                 sprd,blknum = <64>;
 559         };
 560
 561         scproc_cpw: scproc@0x88000000 {
 562                 compatible = "sprd,scproc";
 563                 sprd,name = "cpw";
 564                 sprd,ctrl-reg = <0x44 0x44 0xb0 0xbc>; /* <shut_down deep_sleep reset get_status> */
 565                 sprd,ctrl-mask = <0x02000000 0x10000000 0x01 0xf0000>; /* masks <> */
 566                 sprd,iram-data = <0xe59f0000 0xe12fff10 0x88300000>; /* 3rd param equals modem_addr*/
 567                 reg = <0x88000000 0x1b00000>, /* <CP_start_addr total_size> = <+128M 26M> */
 568                         <0xf53d4000 0x0c>, /* <iram1_base size> */
 569                         <0xf5230000 0x10000>; /* <pmu_base size> */
 570                 interrupts = <0 84 0x0>; /* cp1_wdg_int */
 571                 #address-cells = <1>;
 572                 #size-cells = <1>;
 573                 /* segnr=2 */
 574                 ranges = <0x300000 0x88300000 0x00800000>,
 575                                 <0x20000 0x88020000 0x00220000>;
 576                 modem@0x300000 {
 577                         cproc,name = "modem";
 578                         reg = <0x300000 0x00800000>; /* <modem_addr size> */
 579                 };
 580                 dsp@0x20000 {
 581                         cproc,name = "dsp";
 582                         reg = <0x20000 0x00220000>; /* <dsp_addr size>*/
 583                 };
 584         };
 585
 586         saudio_w{
 587                 compatible = "sprd,saudio";
 588                 sprd,saudio-dst-id = <2>;
 589                 sprd,saudio-names = "saudio_w";
 590         };
 591         saudio_voip{
 592                 compatible = "sprd,saudio";
 593                 sprd,saudio-dst-id = <2>;
 594                 sprd,saudio-names = "saudiovoip";
 595         };
 596
 597         /* cpwcn virtual devices */
 598
 599         spipe_cpwcn {
 600                 compatible = "sprd,spipe";
 601                 sprd,name = "spipe_wcn";
 602                 sprd,dst = <3>;
 603                 sprd,channel = <4>;
 604                 sprd,ringnr = <12>;
 605                 sprd,size-rxbuf = <0x1000>; /* 4*1024 */
 606                 sprd,size-txbuf = <0x1000>; /* 4*1024 */
 607         };
 608
 609         slog_cpwcn {
 610                 compatible = "sprd,spipe";
 611                 sprd,name = "slog_wcn";
 612                 sprd,dst = <3>;
 613                 sprd,channel = <5>;
 614                 sprd,ringnr = <1>;
 615                 sprd,size-rxbuf = <0x40000>; /* 256*1024*/
 616                 sprd,size-txbuf = <0x8000>; /* 32*1024 */
 617         };
 618
 619         stty4bt_cpwcn {
 620                 compatible = "sprd,stty4bt";
 621                 sprd,name = "sttybt";
 622                 sprd,dst = <3>;
 623                 sprd,channel = <4>;
 624                 sprd,bufid = <10>;
 625         };
 626
 627         scproc_cpwcn: scproc@0x8a800000 {
 628                 compatible = "sprd,scproc";
 629                 sprd,name = "cpwcn";
 630                 sprd,ctrl-reg = <0x68 0x68 0xb0 0xb0>; /* <shut_down deep_sleep reset get_status> */
 631                 sprd,ctrl-mask = <0x02000000 0x10000000 0x04 0x04>; /* masks <> */
 632                 sprd,iram-data = <0xe59f0000 0xe12fff10 0x8a808000>; /* 3rd param equals modem_addr*/
 633                 reg = <0x8a800000 0x201000>, /* <CP_start_addr total_size> = <+168M 2M+4k> */
 634                         <0x50003000 0x1000>, /* <iram1_phys size> use iram1 phys because of cp2 iram not maped */
 635                         <0xf5230000 0x10000>; /* <pmu_base size> */
 636                 interrupts = <0 85 0x0>; /* cp2_wdg_int */
 637                 #address-cells = <1>;
 638                 #size-cells = <1>;
 639                 /* segnr=1 */
 640                 ranges = <0x8000 0x8a808000 0x201000>;
 641                 modem@0x8000 {
 642                         cproc,name = "modem";
 643                         reg = <0x8000 0x201000>; /* <modem_addr size> */
 644                 };
 645         };
 646
 647         sprd_wlan{
 648                 compatible = "sprd,sprd_wlan";
 649         };
 650
 651         sdhci0: sdhci@f5117000{
 652                 compatible  = "sprd,sdhci-shark";
 653                 interrupts = <0 57 0x0>;
 654                 reg = <0xf5117000 0x1000>;
 655                 id = <0>;
 656                 bus-width = <4>;
 657                 max-frequency = <384000000>;
 658                 keep-power-in-suspend = <1>;
 659                 caps = <0x80000000>;
 660                 caps2 = <0x202>;
 661                 host-caps-mask = <0x05000000>;
 662                 vdd-vqmmc = "vddsd";
 663                 sd-supply = <&vddsd>;
 664                 vdd-level = <0 0 1800000 3000000>;
 665                 vqmmc-voltage-level = <3000000>;
 666                 pinmap-offset = <0x0184>;
 667                 d3-gpio = <100>;
 668                 d3-index = <0>;
 669                 sd-func = <0>;
 670                 gpio-func = <3>;
 671                 clock-names = "clk_sdio0";
 672                 clocks = <&clk_sdio0>, <&clk_384m>;
 673                 enb-bit = <0x100>;
 674                 rst-bit = <0x800>;
 675                 keep-power = <0>;
 676                 runtime = <1>;
 677         };
 678         sdhci1: sdhci@f5118000{
 679                 compatible  = "sprd,sdhci-shark";
 680                 interrupts = <0 58 0x0>;
 681                 reg = <0xf5118000 0x1000>;
 682                 id = <1>;
 683                 bus-width = <4>;
 684                 max-frequency = <96000000>;
 685                 keep-power-in-suspend = <1>;
 686                 cap-power-off-card = <1>;
 687                 caps = <0x80000000>;
 688                 clock-names = "clk_sdio1";
 689                 clocks = <&clk_sdio1>, <&clk_96m>;
 690                 enb-bit = <0x200>;
 691                 rst-bit = <0x1000>;
 692                 keep-power = <0>;
 693                 runtime = <1>;
 694         };
 695
 696         nand0:nand@f5128000 {
 697                 compatible  = "sprd,sprd-nand";
 698                 reg = <0xf5128000 0x1000>;
 699         };
 700
 701          usb: usb@f5116000{
 702                  compatible  = "sprd,usb";
 703                  interrupts = <0 55 0x0>;
 704                 ngpios = <2>;
 705                 gpios = <&a_eic_gpio 0 0>,<&d_gpio_gpio 72 0>;
 706                  reg = <0xf5116000 0x1000>;
 707                  tune_value = <0x44073e33>;
 708                  usb-supply = <&vddusb>;
 709                  #address-cells = <1>;
 710                  #size-cells = <0>;
 711          };
 712         sprd_thermal {
 713                 compatible = "sprd,sprd-thermal";
 714                 id = <0>;
 715                 interrupts = <0 26 0x0>;
 716                 reg = <0x402f0000 0x1000>;
 717                 trip_points_active = <105>;
 718                 trip_points_critical = <114>;
 719                 trip_num = <2>;
 720         };
 721
 722          spi0: spi@70a00000{
 723                  compatible  = "sprd,sprd-spi";
 724                  interrupts = <0 7 0x0>;
 725                  reg = <0xf5376000 0x1000>;
 726                  clock-names = "clk_spi0";
 727                  #address-cells = <1>;
 728                  #size-cells = <0>;
 729          };
 730          spi1: spi@70b00000{
 731                  compatible  = "sprd,sprd-spi";
 732                  interrupts = <0 8 0x0>;
 733                  reg = <0xf5378000 0x1000>;
 734                  clock-names = "clk_spi1";
 735                  #address-cells = <1>;
 736                  #size-cells = <0>;
 737          };
 738          spi2: spi@70c00000{
 739                  compatible  = "sprd,sprd-spi";
 740                  interrupts = <0 9 0x0>;
 741                  reg = <0xf537a000 0x1000>;
 742                  clock-names = "clk_spi2";
 743                  #address-cells = <1>;
 744                  #size-cells = <0>;
 745          };
 746          dmac: dmac@20100000{
 747                  compatible  = "sprd,sprd-dma";
 748                  interrupts = <0 50 0x0>;
 749                  reg = <0xf5112000 0x4000>;
 750          };
 751          adc: adc@40038300{
 752                  compatible  = "sprd,sprd-adc";
 753                  reg = <0xf53f8300 0x400>;
 754          };
 755          hwspinlock0: hwspinlock0@20c00000{
 756                  compatible  = "sprd,sprd-hwspinlock";
 757                  reg = <0xf512a000 0x1000>;
 758          };
 759          hwspinlock1: hwspinlock1@40060000{
 760                  compatible  = "sprd,sprd-hwspinlock";
 761                  reg = <0xf51f6000 0x1000>;
 762          };
 763          gpu {
 764                  compatible  = "sprd,mali-utgard";
 765                  mali_pp_core_number = <4>;
 766                  interrupt-names =     "mali_gp_irq",
 767                                        "mali_gp_mmu_irq",
 768                                        "mali_pp0_irq",
 769                                        "mali_pp0_mmu_irq",
 770                                        "mali_pp1_irq",
 771                                        "mali_pp1_mmu_irq";
 772                  reg-names       =     "mali_l2",
 773                                        "mali_gp",
 774                                        "mali_gp_mmu",
 775                                        "mali_pp0",
 776                                        "mali_pp0_mmu",
 777                                        "mali_pp1",
 778                                        "mali_pp1_mmu",
 779                                        "mali_pmu";
 780                  interrupts =  <0 39 0x0>,  //  MALI_GP_IRQ,
 781                        <0 39 0x0>,  //  MALI_GP_MMU_IRQ,
 782                        <0 39 0x0>,  //  MALI_PP0_IRQ,
 783                        <0 39 0x0>,  //  MALI_PP0_MMU_IRQ,
 784                        <0 39 0x0>,  //  MALI_PP1_IRQ,
 785                        <0 39 0x0>;  //  MALI_PP1_MMU_IRQ,
 786                  reg = <0x60001000 0x200>,//  MALI_L2,MALI_GPU_RESOURCE_L2(base_addr + 0x1000)
 787                        <0x60000000 0x100>,//  MALI_GP,
 788                        <0x60003000 0x100>,//  MALI_GP_MMU,
 789                        <0x60008000 0x1100>,//  MALI_PP0,
 790                        <0x60004000 0x100>,//  MALI_PP0_MMU,
 791                        <0x6000A000 0x1100>,//  MALI_PP1,
 792                        <0x60005000 0x100>,//  MALI_PP1_MMU,
 793                        <0x60002000 0x100>;//  MALI_PMU,
 794                  clock-names = "clk_gpu_axi","clk_gpu","clk_153m6","clk_208m","clk_256m","clk_312m","clk_384m","clk_460m8";
 795                  clocks = <&clk_gpu_axi>,<&clk_gpu>,<&clk_153m6>,<&clk_208m>,<&clk_256m>,<&clk_312m>,<&clk_384m>,<&clk_460m8>;
 796          };
 797          ion {
 798                  compatible = "sprd,ion-sprd";
 799                  #address-cells = <1>;
 800                  #size-cells = <0>;
 801
 802                  sprd,ion-heap@1 {
 803                        reg = <1>;                      /* SYSTEM */
 804                        reg-names = "ion_heap_system";
 805                        sprd,ion-heap-type = <0>;       /* SYSTEM */
 806                        sprd,ion-heap-mem = <0x0 0x0>;
 807                  };
 808
 809                  sprd,ion-heap@2 {
 810                        reg = <2>;                      /* MM */
 811                        reg-names = "ion_heap_carveout_mm";
 812                        sprd,ion-heap-type = <0>;       /* carveout mm */
 813                        sprd,ion-heap-mem = <0x88b00000 0x7100000>;
 814                  };
 815
 816                  sprd,ion-heap@3 {
 817                        reg = <3>;                      /* OVERLAY */
 818                        reg-names = "ion_heap_carveout_overlay";
 819                        sprd,ion-heap-type = <2>;       /* CARVEOUT */
 820                        sprd,ion-heap-mem = <0x8fc00000 0x0>;      /* 0M */
 821                  };
 822          };
 823          sprd_iommu0:sprd_iommu@F5410000 {
 824                  compatible  = "sprd,sprd_iommu";//gsp
 825                  func-name = "sprd_iommu_gsp";
 826                  reg = <0x10000000 0x2000000>, //iova
 827                        <0xF5410000 0x8000>,  //pgt
 828                        <0xF5418000 0x8000>;  //ctrl_reg
 829                  reg_name = "iova","pgt","ctrl_reg";
 830                  clock-names = "clk_gsp_emc","clk_153m6","clk_gsp";
 831                  clocks = <&clk_gsp_emc>, <&clk_153m6>,<&clk_gsp>;
 832                  status = "ok";
 833          };
 834          sprd_iommu1:sprd_iommu@F5430000 {
 835                  compatible  = "sprd,sprd_iommu";//mm
 836                  func-name = "sprd_iommu_mm";
 837                  reg = <0x20000000 0x8000000>,   //iova
 838                        <0xF5430000 0x20000>,     //pgt
 839                        <0xF5450000 0x2000>;      //ctrl_reg
 840                  reg_name = "iova","pgt","ctrl_reg";
 841                  clock-names = "clk_mmu","clk_mm_i";
 842                  clocks = <&clk_mmu>,<&clk_mm>;
 843                  status = "ok";
 844          };
 845          sprd_rf2351: sprd_rf2351@40070000{
 846                 compatible  = "sprd,sprd_rf2351";
 847                 reg = <0xf51f8000 0x1000>,              /*RFSPI*/
 848                         <0xf5250000 0x10000>;           /*APB_EB0*/
 849                 clock-names = "clk_cpll";
 850                 clocks = <&clk_cpll>;
 851          };
 852          gps_2351: gps_2351@21c00000{
 853                 compatible  = "sprd,gps_2351";
 854                 interrupts = <0 52 0x0>;
 855                 gpios = <&d_gpio_gpio 50 0>;
 856                 reg = <0xf5150000 0x1000>,              /*GPS CORE BASE*/
 857                         <0xf5130000 0x10000>,           /*AHB_ADDR*/
 858                         <0xf5230000 0x10000>;           /*PMU BASE*/
 859          };
 860 };
 861
 862 &vbc_r2p0 {
 863         status = "okay";
 864 };
 865
 866 &sprd_codec_v3 {
 867         status = "okay";
 868         sprd,audio_power_ver = <3>;
 869 };
 870
 871
 872 &i2s0 {
 873         sprd,config = <&pcm_def_config>;
 874         status = "okay";
 875 };
 876
 877 &i2s1 {
 878         status = "okay";
 879 };
 880
 881 &i2s2 {
 882         status = "okay";
 883 };
 884
 885 &i2s3 {
 886         status = "okay";
 887 };
 888
 889 &i2s_sound {
 890         sprd,i2s = <&i2s0>, <&i2s1>, <&i2s2>, <&i2s3>;
 891 };
 892 &sprd_battery {
 893         chg-end-vol-l = <4150>;
 894 };