arch/arm/boot/dts/sprd-scx35_sp7731geaopenphone.dts

   1 /*
   2 * Copyright (C) 2013 Spreadtrum Communication Incorporated
   3 *               http://www.spreadtrum.com/
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License version 2 as
   7 * published by the Free Software Foundation.
   8 */
   9 /dts-v1/;
  10
  11 /* memory reserved for SMEM */
  12 /memreserve/ 0x87800000 0x200000; /* 2MK */
  13
  14 /* memory reserved for CPW modem */
  15 /memreserve/ 0x88000000 0x1b00000; /* 27M */
  16
  17 /* memory reserved for CPWCN modem */
  18 /memreserve/ 0x8a800000 0x201000;/*Offset:168M, SIZE:2M+4k*/
  19
  20 /* memory reserved for fb */
  21 /memreserve/ 0x9F311000 0x5EF000; /* 540*960*4*3, 4K alignment */
  22
  23 /* memory reserved for ION */
  24 /memreserve/ 0x9f900000 0x700000; /* 7MK */
  25
  26 /include/ "skeleton.dtsi"
  27 /include/ "scx30g-clocks.dtsi"
  28 /include/ "scx30g-regulators.dtsi"
  29 /include/ "sprd-sound.dtsi"
  30 /include/ "sprd-battery.dtsi"
  31
  32 / {
  33         model = "Spreadtrum SP8835EB board";
  34         compatible = "sprd,sp8835eb";
  35         sprd,sc-id = <8830 1 0x20000>;
  36         #address-cells = <1>;
  37         #size-cells = <1>;
  38         interrupt-parent = <&gic>;
  39
  40         chosen {
  41                 bootargs = "loglevel=1 console=ttyS1,115200n8 init=/init root=/dev/ram0 rw";
  42                 linux,initrd-start = <0x85500000>;
  43                 linux,initrd-end   = <0x855a3212>;
  44         };
  45
  46         memory {
  47                 device_type = "memory";
  48                 reg = <0x80000000 0x20000000>;
  49         };
  50
  51         aliases {
  52                 serial0 = &uart0;
  53                 serial1 = &uart1;
  54                 serial2 = &uart2;
  55                 serial3 = &uart3;
  56                 i2c0 = &i2c0;
  57                 i2c1 = &i2c1;
  58                 i2c2 = &i2c2;
  59                 i2c3 = &i2c3;
  60                 lcd0 = &fb0;
  61                 spi0 = &spi0;
  62                 spi1 = &spi1;
  63                 spi2 = &spi2;
  64                 hwspinlock0 = &hwspinlock0;
  65                 hwspinlock1 = &hwspinlock1;
  66         };
  67
  68         cpus {
  69                 #address-cells = <1>;
  70                 #size-cells = <0>;
  71
  72                 cpu@f00 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a7";
  75                         reg = <0xf00>;
  76                 };
  77
  78                 cpu@f01 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a7";
  81                         reg = <0xf01>;
  82                 };
  83
  84                 cpu@f02 {
  85                         device_type = "cpu";
  86                         compatible = "arm,cortex-a7";
  87                         reg = <0xf02>;
  88                 };
  89
  90                 cpu@f03 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a7";
  93                         reg = <0xf03>;
  94                 };
  95         };
  96
  97     gic: interrupt-controller@12001000 {
  98         compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  99         #interrupt-cells = <3>;
 100         #address-cells = <0>;
 101         interrupt-controller;
 102         reg = <0x12001000 0x1000>,
 103               <0x12002000 0x1000>;
 104     };
 105
 106          uart0: uart@f5360000{
 107                  compatible  = "sprd,serial";
 108                  interrupts = <0 2 0x0>;
 109                  reg = <0xf5360000 0x1000>;
 110                  clock-names = "clk_uart0";
 111                  clocks = <&clock 60>;
 112                  sprdclk = <48000000>;
 113                  sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP";
 114          };
 115          uart1: uart@f5362000{
 116                  compatible  = "sprd,serial";
 117                  interrupts = <0 3 0x0>;
 118                  reg = <0xf5362000 0x1000>;
 119                  clock-names = "clk_uart1";
 120                  clocks = <&clock 61>;
 121                  sprdclk = <26000000>;
 122                  sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP";
 123          };
 124          uart2: uart@f5364000{
 125                  compatible  = "sprd,serial";
 126                  interrupts = <0 4 0x0>;
 127                  reg = <0xf5364000 0x1000>;
 128                  clock-names = "clk_uart2";
 129                  clocks = <&clock 62>;
 130                  sprdclk = <26000000>;
 131                  sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP";
 132          };
 133          uart3: uart@f5366000{
 134                  compatible  = "sprd,serial";
 135                  interrupts = <0 5 0x0>;
 136                  reg = <0xf5366000 0x1000>;
 137                  clock-names = "clk_uart3";
 138                  clocks = <&clock 63>;
 139                  sprdclk = <26000000>;
 140                  sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP";
 141          };
 142
 143          timer{
 144                  compatible  = "sprd,scx35-timer";
 145                  reg = <0xf5204000 0x1000>,
 146                          <0xf51f4000 0x1000>,
 147                          <0xf5202000 0x1000>,
 148                          <0xf5292000 0x1000>,
 149                          <0xf5294000 0x1000>;
 150                  interrupts = <0 118 0x0>,
 151                                         <0 28 0x0>,
 152                                         <0 29 0x0>,
 153                                         <0 119 0x0>,
 154                                         <0 121 0x0>,
 155                                         <0 31 0x0>;
 156          };
 157          clock: clockdevice{
 158                  compatible = "sprd,scx35-clock";
 159                 #clock-cells = <1>;
 160          };
 161          d_eic_gpio: gpio@f5200000{
 162                  compatible = "sprd,d-eic-gpio";
 163                  reg = <0Xf5200000 0x1000>;
 164                  gpio-controller;
 165                  interrupt-controller;
 166                  #interrupt-cells = <2>;
 167                  #gpio-cells = <2>;
 168                  gpiobase = <288>;
 169                  ngpios = <16>;
 170                  interrupts = <0 37 0x0>;
 171          };
 172          d_gpio_gpio: gpio@f5220000{
 173                  compatible = "sprd,d-gpio-gpio";
 174                  reg = <0Xf5220000 0x1000>;
 175                  gpio-controller;
 176                  interrupt-controller;
 177                  #interrupt-cells = <2>;
 178                  #gpio-cells = <2>;
 179                  gpiobase = <0>;
 180                  ngpios = <256>;
 181                  interrupts = <0 35 0x0>;
 182          };
 183         pinctrl{
 184                 compatible = "sprd,pinctrl";
 185                 reg = <0xf5224000 0x1000>;
 186                 pwr_domain = "vdd28",
 187                                          "vdd28",
 188                                          "vddsim0",
 189                                          "vddsim1",
 190                                          "vddsim2",
 191                                          "vddsd",
 192                                          "vdd18";
 193                 ctrl_desc = <0x10 0 1
 194                                     0x10 1 1
 195                                     0x10 2 1
 196                                     0x10 3 1
 197                                     0x10 4 1
 198                                     0x10 5 1
 199                                     0x10 6 1>;
 200         };
 201         adic:adic{
 202                 compatible = "sprd,adic";
 203                 reg = <0Xf53f0000 0x1000>;
 204         };
 205          adi: adi_bus{
 206                  compatible = "sprd,adi-bus";
 207                  interrupts = <0 38 0x0>;
 208                  reg = <0Xf53f8000 0x1000>;
 209                  interrupt-controller;
 210                  sprd,irqnums = <11>;
 211                  #interrupt-cells = <2>;
 212                  #address-cells = <1>;
 213                  #size-cells = <1>;
 214                  ranges = <0X40 0Xf53f8040 0x40>,
 215                                   <0X80 0Xf53f8080 0x80>,
 216                                   <0X100 0Xf53f8100 0x80>,
 217                                   <0X480 0Xf53f8480 0x80>;
 218                  sprd_backlight {
 219                         compatible = "sprd,sprd_backlight";
 220                         start = <3>;
 221                         end = <3>;
 222                         flags = <0x100>;
 223                  };
 224                  headset_detect {
 225                         compatible = "sprd,headset-detect";
 226                         gpio_switch = <0>;
 227                         gpio_detect = <309>;
 228                         gpio_button = <307>;
 229                         irq_trigger_level_detect = <1>;
 230                         irq_trigger_level_button = <1>;
 231                         adc_threshold_3pole_detect = <100>;
 232                         adc_threshold_4pole_detect = <3100>;
 233                         irq_threshold_buttont = <1>;
 234                         voltage_headmicbias = <3000000>;
 235                         nbuttons = <1>;
 236                         headset_buttons {
 237                                 adc_min = <0>;
 238                                 adc_max = <170>;
 239                                 code = <226>;
 240                                 type = <0>;
 241                         };
 242                  };
 243                  keyboard_backlight {
 244                         compatible = "sprd,keyboard-backlight";
 245                  };
 246                  watchdog@40{
 247                         compatible = "sprd,watchdog";
 248                         reg = <0X40 0x40>;
 249                         interrupts = <3 0x0>;
 250                  };
 251                  rtc@80{
 252                         compatible = "sprd,rtc";
 253                         reg = <0X80 0x80>;
 254                         interrupts = <2 0x0>;
 255                 };
 256                  a_eic_gpio: gpio@100{
 257                          compatible = "sprd,a-eic-gpio";
 258                          reg = <0X100 0x80>; /* adi reg */
 259                          gpio-controller;
 260                          interrupt-controller;
 261                          #interrupt-cells = <2>;
 262                          #gpio-cells = <2>;
 263                          gpiobase = <304>;
 264                          ngpios = <16>;
 265                          interrupt-parent = <&adi>;
 266                          interrupts = <5 0x0>; /* ext irq 5 */
 267                  };
 268                  a_gpio_gpio: gpio@480{
 269                          compatible = "sprd,a-gpio-gpio";
 270                          reg = <0X480 0x80>; /* adi reg */
 271                          gpio-controller;
 272                          interrupt-controller;
 273                          #interrupt-cells = <2>;
 274                          #gpio-cells = <2>;
 275                          gpiobase = <256>;
 276                          ngpios = <32>;
 277                          interrupt-parent = <&adi>;
 278                          interrupts = <1 0x0>; /* ext irq 1 */
 279                  };
 280          };
 281          keypad@f5208000{
 282                  compatible = "sprd,sci-keypad";
 283                  reg = <0Xf5208000 0x1000>;
 284                  gpios = <&a_eic_gpio 2 0>;
 285                  interrupts = <0 36 0x0>;
 286                  sprd,keypad-num-rows = <2>;
 287                  sprd,keypad-num-columns = <2>;
 288                  sprd,keypad-rows-choose-hw = <0x30000>;
 289                  sprd,keypad-cols-choose-hw = <0x300>;
 290                  sprd,debounce_time = <5000>;
 291                  linux,keypad-no-autorepeat;
 292                  sprd,support_long_key;
 293
 294                  key_volume_down {
 295                          keypad,row = <0>;
 296                          keypad,column = <0>;
 297                          linux,code = <114>;
 298                  };
 299                  key_volume_up {
 300                          keypad,row = <1>;
 301                          keypad,column = <0>;
 302                          linux,code = <115>;
 303                  };
 304                  key_home {
 305                          keypad,row = <0>;
 306                          keypad,column = <1>;
 307                          linux,code = <102>;
 308                  };
 309          };
 310          sprd_vsp@f5300000{
 311                  compatible = "sprd,sprd_vsp";
 312                  reg = <0Xf5300000 0xc000>;
 313                  interrupts = <0 43 0x0>;
 314                  clock-names = "clk_mm_i", "clk_vsp";
 315                  clocks = <&clk_mm>, <&clk_vsp>;
 316                  version = <2>;
 317          };
 318         sprd_jpg {
 319                  compatible  = "sprd,sprd_jpg";
 320                  reg = <0Xf5320000 0x8000>;
 321                  interrupts = <0 42 0x0>;
 322                  clock-names = "clk_mm_i","clk_jpg";
 323                  clocks = <&clk_mm>, <&clk_jpg>;
 324          };
 325
 326
 327          i2c0: i2c@f536a000{
 328                  compatible  = "sprd,i2c";
 329                  interrupts = <0 11 0x0>;
 330                  reg = <0xf536a000 0x1000>;
 331                  #address-cells = <1>;
 332                  #size-cells = <0>;
 333                  sensor_main@0x3c{
 334                         compatible = "sprd,sensor_main";
 335                         reg = <0x3c>;
 336                  };
 337                  sensor_sub@0x21{
 338                         compatible = "sprd,sensor_sub";
 339                         reg = <0x21>;
 340                  };
 341          };
 342          i2c1: i2c@f536c000{
 343                  compatible  = "sprd,i2c";
 344                  interrupts = <0 12 0x0>;
 345                  reg = <0xf536c000 0x1000>;
 346                  #address-cells = <1>;
 347                  #size-cells = <0>;
 348                 focaltech_ts@38{
 349                         compatible = "focaltech,focaltech_ts";
 350                         reg = <0x38>;
 351                         gpios = <&d_gpio_gpio 81 0
 352                                 &d_gpio_gpio 82 0>;
 353                         vdd_name = "vdd28";
 354                         virtualkeys = <100 1020 80 65
 355                                  280 1020 80 65
 356                                  470 1020 80 65>;
 357                         TP_MAX_X = <720>;
 358                         TP_MAX_Y = <1280>;
 359                 };
 360          };
 361          i2c2: i2c@f5370000{
 362                  compatible  = "sprd,i2c";
 363                  interrupts = <0 13 0x0>;
 364                  reg = <0xf5370000 0x1000>;
 365                  #address-cells = <1>;
 366                  #size-cells = <0>;
 367                 lis3dh_acc@18{
 368                         compatible = "ST,lis3dh_acc";
 369                         reg = <0x18>;
 370                         poll_interval = <10>;
 371                         min_interval = <10>;
 372                         g_range = <0>;
 373                         axis_map_x = <1>;
 374                         axis_map_y = <0>;
 375                         axis_map_z = <2>;
 376                         negate_x = <0>;
 377                         negate_y = <1>;
 378                         negate_z = <0>;
 379                 };
 380                 ltr_558als@23{
 381                         compatible = "LITEON,ltr_558als";
 382                         reg = <0x23>;
 383                         gpios = <&d_gpio_gpio 216 0>;
 384                 };
 385          };
 386          i2c3: i2c@f5372000{
 387                  compatible  = "sprd,i2c";
 388                  interrupts = <0 14 0x0>;
 389                  reg = <0xf5372000 0x1000>;
 390                  #address-cells = <1>;
 391                  #size-cells = <0>;
 392          };
 393          sprd_dcam{
 394                  compatible  = "sprd,sprd_dcam";
 395                  interrupts = <0 45 0>;
 396                  reg = <0xf52f0000 0x100000>;
 397                  clock-names = "clk_mm_i","clk_dcam";
 398                  clocks = <&clk_mm>, <&clk_dcam>;
 399          };
 400          sprd_scale {
 401                  compatible  = "sprd,sprd_scale";
 402          };
 403          sprd_rotation {
 404                  compatible  = "sprd,sprd_rotation";
 405          };
 406          sprd_sensor {
 407                  compatible  = "sprd,sprd_sensor";
 408                  reg = <0x60c00000 0x100000>;
 409                  gpios = <&d_gpio_gpio 186 0   /*main reset*/
 410                         &d_gpio_gpio 187 0    /*main power down*/
 411                         &d_gpio_gpio 186 0    /*sub reset*/
 412                         &d_gpio_gpio 188 0    /*sub power down*/
 413                         &d_gpio_gpio 0 0      /*main core voltage*/
 414                         &d_gpio_gpio 0 0
 415                         &d_gpio_gpio 0 0
 416                         &d_gpio_gpio 0 0>;
 417                  clock-names ="clk_mm_i","clk_sensor","clk_ccir","clk_dcam","clk_dcam_mipi";
 418                  clocks = <&clk_mm>, <&clk_sensor>,<&clk_ccir>, <&clk_dcam>, <&clk_dcam_mipi>;
 419                  };
 420          sprd_isp {
 421                  compatible  = "sprd,sprd_isp";
 422                  clock-names = "clk_mm_i","clk_isp";
 423                  clocks = <&clk_mm>, <&clk_isp>;
 424          };
 425          sprd_dma_copy {
 426                  compatible  = "sprd,sprd_dma_copy";
 427          };
 428         fb0: fb@20800000 {
 429                 compatible = "sprd,sprdfb";
 430                 reg = <0xf5122000 0x1000>,<0xf5146000 0x1000>;
 431                 interrupts = <0 46 0x0>,<0 48 0x0>, <0 49 0x0>;
 432                 clock-names = "dispc_clk_parent", "dispc_dbi_clk_parent", "dispc_dpi_clk_parent", "dispc_emc_clk_parent", "dispc_clk", "dispc_dbi_clk", "dispc_dpi_clk", "dispc_emc_clk", "fb_spi_clock", "fb_spi_clock_parent";
 433                 clocks = <&clk_256m>, <&clk_256m>, <&clk_384m>, <&clk_aon_apb>, <&clk_dispc0>, <&clk_dispc0_dbi>, <&clk_dispc0_dpi>, <&clk_disp_emc>, <&clk_spi2>, <&ext_26m>;
 434                 clock-src = <256000000 256000000 384000000>;
 435                 dpi_clk_div = <7>;
 436                 sprd,fb_use_reservemem;
 437                 sprd,fb_mem = <0x9F311000 0x5EF000>;
 438         };
 439         gsp:gsp@20a00000 {
 440                 compatible = "sprd,gsp";
 441                 reg = <0xf5126000 0x1000>;
 442                 interrupts = <0 51 0x0>;
 443                 clock-names = "clk_gsp", "clk_gsp_emc", "clk_gsp_parent", "clk_aon_apb";
 444                 clocks = <&clk_gsp>, <&clk_gsp_emc>, <&clk_256m>, <&clk_aon_apb>;
 445                 gsp_mmu_ctrl_base = <0xf5418000>;
 446         };
 447
 448         sprd_fm: sprd_fm@40270000{
 449                 compatible  = "sprd,sprd_fm";
 450                 reg = <0xf5210000 0x1000>,
 451                                 <0xf5250000 0x10000>,
 452                 <0xf5230000 0x10000>,
 453                 <0xf5242000 0x10000>;
 454         };
 455
 456         /* sipc initializer */
 457
 458         sipc: sipc@0x87800000 {
 459                 compatible = "sprd,sipc";
 460                 reg = <0x87800000 0x200000>; /* <SMEM SIZE>*/
 461                 //#interrupt-cells = <2>;
 462                 #address-cells = <1>;
 463                 #size-cells = <1>;
 464                 ranges = <0x8000000 0x88000000 0x1b00000>,
 465                                 <0x07800000 0x87800000 0x140000>,
 466                                 <0x9aff000 0x89aff000 0x1000>,
 467                                 <0x0a800000 0x8a800000 0x201000>,/*WCN MEMORY:OFFSET ADDRESS SIZE*/
 468                                 <0x07940000 0x87940000 0xc0000>,
 469                                 <0x0aa00000 0x8aa00000 0x1000>;/*WCN SIPC-RING:OFFSET ADDRESS SIZE*/
 470                 sipc_cpw@0x8000000 {
 471                         sprd,name = "sipc-w";
 472                         sprd,dst = <2>;
 473                         sprd,ap2cp = <0xf5240000>; /* base on ipi reggister */
 474                         sprd,cp2ap = <0xf5240004>;
 475                         sprd,trig = <0x01>; /* trigger bit */
 476                         sprd,clr = <0x01>; /* clear bit */
 477                         interrupts = <0 68 0x0>;
 478                         reg = <0x8000000 0x1b00000> , /* <CP_start_addr size> */
 479                                 <0x07800000 0x140000>, /* <SMEM_phy_addr total_size> */
 480                                 <0x9aff000 0x1000>; /* smsg ring buffer <base size> */
 481                 };
 482                 sipc_wcn@0x0a800000 {
 483                         sprd,name = "sipc-wcn";
 484                         sprd,dst = <3>;
 485                         sprd,ap2cp = <0xf5240000>; /* base on ipi reggister */
 486                         sprd,cp2ap = <0xf5240004>;
 487                         sprd,trig = <0x100>; /* trigger bit */
 488                         sprd,clr = <0x100>; /* clear bit */
 489                         interrupts = <0 73 0x0>;
 490                         reg = <0x0a800000 0x201000> , /* <CP_start_addr size> */
 491                                 <0x07940000 0xc0000>, /* <SMEM_phy_addr total_size> */
 492                                 <0x0aa00000 0x1000>; /* smsg ring buffer <base size> */
 493                 };
 494
 495         };
 496
 497
 498         /* cpw virtual devices */
 499
 500         spipe-cpw {
 501                 compatible = "sprd,spipe";
 502                 sprd,name = "spipe_w";
 503                 sprd,dst = <2>;
 504                 sprd,channel = <4>;
 505                 sprd,ringnr = <15>;
 506                 sprd,size-rxbuf = <0x1000>; /* 4*1024 */
 507                 sprd,size-txbuf = <0x1000>; /* 4*1024 */
 508         };
 509
 510         slog-cpw {
 511                 compatible = "sprd,spipe";
 512                 sprd,name = "slog_w";
 513                 sprd,dst = <2>;
 514                 sprd,channel = <5>;
 515                 sprd,ringnr = <1>;
 516                 sprd,size-rxbuf = <0x40000>; /* 256*1024*/
 517                 sprd,size-txbuf = <0x8000>; /* 32*1024 */
 518         };
 519
 520         stty-cpw {
 521                 compatible = "sprd,spipe";
 522                 sprd,name = "stty_w";
 523                 sprd,dst = <2>;
 524                 sprd,channel = <6>;
 525                 sprd,ringnr = <32>;
 526                 sprd,size-rxbuf = <0x0800>; /* 2*1024*/
 527                 sprd,size-txbuf = <0x0800>; /* 2*1024 */
 528         };
 529
 530         seth0-cpw {
 531                 compatible = "sprd,seth";
 532                 sprd,name = "seth_w0";
 533                 sprd,dst = <2>;
 534                 sprd,channel = <7>;
 535                 sprd,blknum = <64>;
 536         };
 537
 538         seth1-cpw {
 539                 compatible = "sprd,seth";
 540                 sprd,name = "seth_w1";
 541                 sprd,dst = <2>;
 542                 sprd,channel = <8>;
 543                 sprd,blknum = <64>;
 544         };
 545
 546         seth2-cpw {
 547                 compatible = "sprd,seth";
 548                 sprd,name = "seth_w2";
 549                 sprd,dst = <2>;
 550                 sprd,channel = <9>;
 551                 sprd,blknum = <64>;
 552         };
 553
 554         scproc_cpw: scproc@0x88000000 {
 555                 compatible = "sprd,scproc";
 556                 sprd,name = "cpw";
 557                 sprd,ctrl-reg = <0x44 0x44 0xb0 0xbc>; /* <shut_down deep_sleep reset get_status> */
 558                 sprd,ctrl-mask = <0x02000000 0x10000000 0x01 0xf0000>; /* masks <> */
 559                 sprd,iram-data = <0xe59f0000 0xe12fff10 0x88300000>; /* 3rd param equals modem_addr*/
 560                 reg = <0x88000000 0x1b00000>, /* <CP_start_addr total_size> = <+128M 26M> */
 561                         <0xf53d4000 0x0c>, /* <iram1_base size> */
 562                         <0xf5230000 0x10000>; /* <pmu_base size> */
 563                 interrupts = <0 84 0x0>; /* cp1_wdg_int */
 564                 #address-cells = <1>;
 565                 #size-cells = <1>;
 566                 /* segnr=2 */
 567                 ranges = <0x300000 0x88300000 0x00800000>,
 568                                 <0x20000 0x88020000 0x00220000>;
 569                 modem@0x300000 {
 570                         cproc,name = "modem";
 571                         reg = <0x300000 0x00800000>; /* <modem_addr size> */
 572                 };
 573                 dsp@0x20000 {
 574                         cproc,name = "dsp";
 575                         reg = <0x20000 0x00220000>; /* <dsp_addr size>*/
 576                 };
 577         };
 578
 579         saudio_w{
 580                 compatible = "sprd,saudio";
 581                 sprd,saudio-dst-id = <2>;
 582                 sprd,saudio-names = "saudio_w";
 583         };
 584         saudio_voip{
 585                 compatible = "sprd,saudio";
 586                 sprd,saudio-dst-id = <2>;
 587                 sprd,saudio-names = "saudiovoip";
 588         };
 589
 590         /* cpwcn virtual devices */
 591
 592         spipe_cpwcn {
 593                 compatible = "sprd,spipe";
 594                 sprd,name = "spipe_wcn";
 595                 sprd,dst = <3>;
 596                 sprd,channel = <4>;
 597                 sprd,ringnr = <12>;
 598                 sprd,size-rxbuf = <0x1000>; /* 4*1024 */
 599                 sprd,size-txbuf = <0x1000>; /* 4*1024 */
 600         };
 601
 602         slog_cpwcn {
 603                 compatible = "sprd,spipe";
 604                 sprd,name = "slog_wcn";
 605                 sprd,dst = <3>;
 606                 sprd,channel = <5>;
 607                 sprd,ringnr = <1>;
 608                 sprd,size-rxbuf = <0x40000>; /* 256*1024*/
 609                 sprd,size-txbuf = <0x8000>; /* 32*1024 */
 610         };
 611
 612         stty4bt_cpwcn {
 613                 compatible = "sprd,stty4bt";
 614                 sprd,name = "sttybt";
 615                 sprd,dst = <3>;
 616                 sprd,channel = <4>;
 617                 sprd,bufid = <10>;
 618         };
 619
 620         scproc_cpwcn: scproc@0x8a800000 {
 621                 compatible = "sprd,scproc";
 622                 sprd,name = "cpwcn";
 623                 sprd,ctrl-reg = <0x68 0x68 0xb0 0xb0>; /* <shut_down deep_sleep reset get_status> */
 624                 sprd,ctrl-mask = <0x02000000 0x10000000 0x04 0x04>; /* masks <> */
 625                 sprd,iram-data = <0xe59f0000 0xe12fff10 0x8a808000>; /* 3rd param equals modem_addr*/
 626                 reg = <0x8a800000 0x201000>, /* <CP_start_addr total_size> = <+168M 2M+4k> */
 627                         <0x50003000 0x1000>, /* <iram1_phys size> use iram1 phys because of cp2 iram not maped */
 628                         <0xf5230000 0x10000>; /* <pmu_base size> */
 629                 interrupts = <0 85 0x0>; /* cp2_wdg_int */
 630                 #address-cells = <1>;
 631                 #size-cells = <1>;
 632                 /* segnr=1 */
 633                 ranges = <0x8000 0x8a808000 0x201000>;
 634                 modem@0x8000 {
 635                         cproc,name = "modem";
 636                         reg = <0x8000 0x201000>; /* <modem_addr size> */
 637                 };
 638         };
 639
 640         sprd_wlan{
 641                 compatible = "sprd,sprd_wlan";
 642         };
 643
 644         sdhci3: sdhci@f511c000{
 645                 compatible  = "sprd,sdhci-shark";
 646                 interrupts = <0 60 0x0>;
 647                 reg = <0xf511c000 0x1000>;
 648                 id = <3>;
 649                 bus-width = <8>;
 650                 max-frequency = <384000000>;
 651                 keep-power-in-suspend = <1>;
 652                 non-removable = <1>;
 653                 caps = <0x80000000>;
 654                 caps2 = <0x202>;
 655                 host-caps-mask = <0x03000000>;
 656                 vdd-vmmc = "vddemmccore";
 657                 vdd-vqmmc = "vddemmcio";
 658                 emmc-signal-supply = <&vddemmccore>;
 659                 vdd-level = <1200000 1300000 1500000 1800000>;
 660                 clock-names = "clk_emmc";
 661                 clocks = <&clk_emmc>, <&clk_384m>;
 662                 enb-bit = <0x800>;
 663                 rst-bit = <0x4000>;
 664                 write-delay = <0x20>;
 665                 read-pos-delay = <0x07>;
 666                 read-neg-delay = <0x05>;
 667                 keep-power = <0>;
 668                 runtime = <1>;
 669         };
 670         sdhci0: sdhci@f5117000{
 671                 compatible  = "sprd,sdhci-shark";
 672                 interrupts = <0 57 0x0>;
 673                 reg = <0xf5117000 0x1000>;
 674                 id = <0>;
 675                 bus-width = <4>;
 676                 max-frequency = <384000000>;
 677                 keep-power-in-suspend = <1>;
 678                 caps = <0x80000000>;
 679                 caps2 = <0x202>;
 680                 host-caps-mask = <0x05000000>;
 681                 vdd-vqmmc = "vddsd";
 682                 sd-supply = <&vddsd>;
 683                 vdd-level = <0 0 1800000 3000000>;
 684                 vqmmc-voltage-level = <3000000>;
 685                 pinmap-offset = <0x0184>;
 686                 d3-gpio = <100>;
 687                 d3-index = <0>;
 688                 sd-func = <0>;
 689                 gpio-func = <3>;
 690                 clock-names = "clk_sdio0";
 691                 clocks = <&clk_sdio0>, <&clk_384m>;
 692                 enb-bit = <0x100>;
 693                 rst-bit = <0x800>;
 694                 keep-power = <0>;
 695                 runtime = <1>;
 696         };
 697         sdhci1: sdhci@f5118000{
 698                 compatible  = "sprd,sdhci-shark";
 699                 interrupts = <0 58 0x0>;
 700                 reg = <0xf5118000 0x1000>;
 701                 id = <1>;
 702                 bus-width = <4>;
 703                 max-frequency = <96000000>;
 704                 keep-power-in-suspend = <1>;
 705                 cap-power-off-card = <1>;
 706                 caps = <0x80000000>;
 707                 clock-names = "clk_sdio1";
 708                 clocks = <&clk_sdio1>, <&clk_96m>;
 709                 enb-bit = <0x200>;
 710                 rst-bit = <0x1000>;
 711                 keep-power = <0>;
 712                 runtime = <1>;
 713         };
 714
 715          usb: usb@f5116000{
 716                  compatible  = "sprd,usb";
 717                  interrupts = <0 55 0x0>;
 718                 ngpios = <2>;
 719                 gpios = <&a_eic_gpio 0 0>,<&d_gpio_gpio 72 0>;
 720                  reg = <0xf5116000 0x1000>;
 721                  tune_value = <0x44073e33>;
 722                  usb-supply = <&vddusb>;
 723                  #address-cells = <1>;
 724                  #size-cells = <0>;
 725          };
 726         sprd_thermal {
 727                 compatible = "sprd,sprd-thermal";
 728                 id = <0>;
 729                 interrupts = <0 26 0x0>;
 730                 reg = <0x402f0000 0x1000>;
 731                 trip_points_active = <105>;
 732                 trip_points_critical = <114>;
 733                 trip_num = <2>;
 734         };
 735          spi0: spi@70a00000{
 736                  compatible  = "sprd,sprd-spi";
 737                  interrupts = <0 7 0x0>;
 738                  reg = <0xf5376000 0x1000>;
 739                  clock-names = "clk_spi0";
 740                  #address-cells = <1>;
 741                  #size-cells = <0>;
 742          };
 743          spi1: spi@70b00000{
 744                  compatible  = "sprd,sprd-spi";
 745                  interrupts = <0 8 0x0>;
 746                  reg = <0xf5378000 0x1000>;
 747                  clock-names = "clk_spi1";
 748                  #address-cells = <1>;
 749                  #size-cells = <0>;
 750          };
 751          spi2: spi@70c00000{
 752                  compatible  = "sprd,sprd-spi";
 753                  interrupts = <0 9 0x0>;
 754                  reg = <0xf537a000 0x1000>;
 755                  clock-names = "clk_spi2";
 756                  #address-cells = <1>;
 757                  #size-cells = <0>;
 758          };
 759          dmac: dmac@20100000{
 760                  compatible  = "sprd,sprd-dma";
 761                  interrupts = <0 50 0x0>;
 762                  reg = <0xf5112000 0x4000>;
 763          };
 764          adc: adc@40038300{
 765                  compatible  = "sprd,sprd-adc";
 766                  reg = <0xf53f8300 0x400>;
 767          };
 768          hwspinlock0: hwspinlock0@20c00000{
 769                  compatible  = "sprd,sprd-hwspinlock";
 770                  reg = <0xf512a000 0x1000>;
 771          };
 772          hwspinlock1: hwspinlock1@40060000{
 773                  compatible  = "sprd,sprd-hwspinlock";
 774                  reg = <0xf51f6000 0x1000>;
 775          };
 776          gpu {
 777                  compatible  = "sprd,mali-utgard";
 778                  mali_pp_core_number = <4>;
 779                  interrupt-names =     "mali_gp_irq",
 780                                        "mali_gp_mmu_irq",
 781                                        "mali_pp0_irq",
 782                                        "mali_pp0_mmu_irq",
 783                                        "mali_pp1_irq",
 784                                        "mali_pp1_mmu_irq";
 785                  reg-names       =     "mali_l2",
 786                                        "mali_gp",
 787                                        "mali_gp_mmu",
 788                                        "mali_pp0",
 789                                        "mali_pp0_mmu",
 790                                        "mali_pp1",
 791                                        "mali_pp1_mmu",
 792                                        "mali_pmu";
 793                  interrupts =  <0 39 0x0>,  //  MALI_GP_IRQ,
 794                        <0 39 0x0>,  //  MALI_GP_MMU_IRQ,
 795                        <0 39 0x0>,  //  MALI_PP0_IRQ,
 796                        <0 39 0x0>,  //  MALI_PP0_MMU_IRQ,
 797                        <0 39 0x0>,  //  MALI_PP1_IRQ,
 798                        <0 39 0x0>;  //  MALI_PP1_MMU_IRQ,
 799                  reg = <0x60001000 0x200>,//  MALI_L2,MALI_GPU_RESOURCE_L2(base_addr + 0x1000)
 800                        <0x60000000 0x100>,//  MALI_GP,
 801                        <0x60003000 0x100>,//  MALI_GP_MMU,
 802                        <0x60008000 0x1100>,//  MALI_PP0,
 803                        <0x60004000 0x100>,//  MALI_PP0_MMU,
 804                        <0x6000A000 0x1100>,//  MALI_PP1,
 805                        <0x60005000 0x100>,//  MALI_PP1_MMU,
 806                        <0x60002000 0x100>;//  MALI_PMU,
 807                  clock-names = "clk_gpu_axi","clk_gpu","clk_153m6","clk_208m","clk_256m","clk_312m","clk_384m","clk_460m8";
 808                  clocks = <&clk_gpu_axi>,<&clk_gpu>,<&clk_153m6>,<&clk_208m>,<&clk_256m>,<&clk_312m>,<&clk_384m>,<&clk_460m8>;
 809          };
 810          ion {
 811                  compatible = "sprd,ion-sprd";
 812                  #address-cells = <1>;
 813                  #size-cells = <0>;
 814
 815                  sprd,ion-heap@1 {
 816                        reg = <1>;                      /* SYSTEM */
 817                        reg-names = "ion_heap_system";
 818                        sprd,ion-heap-type = <0>;       /* SYSTEM */
 819                        sprd,ion-heap-mem = <0x0 0x0>;
 820                  };
 821
 822                  sprd,ion-heap@2 {
 823                        reg = <2>;                      /* MM */
 824                        reg-names = "ion_heap_carveout_mm";
 825                        sprd,ion-heap-type = <0>;       /* carveout mm */
 826                        sprd,ion-heap-mem = <0x98800000 0x7100000>;
 827                  };
 828
 829                  sprd,ion-heap@3 {
 830                        reg = <3>;                      /* OVERLAY */
 831                        reg-names = "ion_heap_carveout_overlay";
 832                        sprd,ion-heap-type = <2>;       /* CARVEOUT */
 833                        sprd,ion-heap-mem = <0x9f900000 0x700000>;      /* 7M */
 834                  };
 835          };
 836          sprd_iommu0:sprd_iommu@F5410000 {
 837                  compatible  = "sprd,sprd_iommu";//gsp
 838                  func-name = "sprd_iommu_gsp";
 839                  reg = <0x10000000 0x2000000>, //iova
 840                        <0xF5410000 0x8000>,  //pgt
 841                        <0xF5418000 0x8000>;  //ctrl_reg
 842                  reg_name = "iova","pgt","ctrl_reg";
 843                  clock-names = "clk_gsp_emc","clk_153m6","clk_gsp";
 844                  clocks = <&clk_gsp_emc>, <&clk_153m6>,<&clk_gsp>;
 845                  status = "ok";
 846          };
 847          sprd_iommu1:sprd_iommu@F5430000 {
 848                  compatible  = "sprd,sprd_iommu";//mm
 849                  func-name = "sprd_iommu_mm";
 850                  reg = <0x20000000 0x8000000>,   //iova
 851                        <0xF5430000 0x20000>,     //pgt
 852                        <0xF5450000 0x2000>;      //ctrl_reg
 853                  reg_name = "iova","pgt","ctrl_reg";
 854                  clock-names = "clk_mmu","clk_mm_i";
 855                  clocks = <&clk_mmu>,<&clk_mm>;
 856                  status = "ok";
 857          };
 858          sprd_rf2351: sprd_rf2351@40070000{
 859                 compatible  = "sprd,sprd_rf2351";
 860                 reg = <0xf51f8000 0x1000>,              /*RFSPI*/
 861                         <0xf5250000 0x10000>;           /*APB_EB0*/
 862                 clock-names = "clk_cpll";
 863                 clocks = <&clk_cpll>;
 864          };
 865          gps_2351: gps_2351@21c00000{
 866                 compatible  = "sprd,gps_2351";
 867                 interrupts = <0 52 0x0>;
 868                 gpios = <&d_gpio_gpio 50 0>;
 869                 reg = <0xf5150000 0x1000>,              /*GPS CORE BASE*/
 870                         <0xf5130000 0x10000>,           /*AHB_ADDR*/
 871                         <0xf5230000 0x10000>;           /*PMU BASE*/
 872          };
 873 };
 874
 875 &vbc_r2p0 {
 876         status = "okay";
 877 };
 878
 879 &sprd_codec_v3 {
 880         status = "okay";
 881         sprd,audio_power_ver = <3>;
 882 };
 883
 884 &i2s0 {
 885         sprd,config = <&pcm_def_config>;
 886         status = "okay";
 887 };
 888
 889 &i2s1 {
 890         status = "okay";
 891 };
 892
 893 &i2s2 {
 894         status = "okay";
 895 };
 896
 897 &i2s3 {
 898         status = "okay";
 899 };
 900
 901 &i2s_sound {
 902         sprd,i2s = <&i2s0>, <&i2s1>, <&i2s2>, <&i2s3>;
 903 };
 904 &sprd_battery {
 905         chg-end-vol-l = <4150>;
 906 };