arch/arm/boot/dts/sprd-scx35_sp7731gea_hd.dts

   1 /*
   2 * Copyright (C) 2013 Spreadtrum Communication Incorporated
   3 *               http://www.spreadtrum.com/
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License version 2 as
   7 * published by the Free Software Foundation.
   8 */
   9 /dts-v1/;
  10
  11 /* memory reserved for SMEM */
  12 /memreserve/ 0x87800000 0x200000; /* 2MK */
  13
  14 /* memory reserved for CPW modem */
  15 /memreserve/ 0x88000000 0x1b00000; /* 27M */
  16
  17 /* memory reserved for CPWCN modem */
  18 /memreserve/ 0x8a800000 0x201000;/*Offset:168M, SIZE:2M+4k*/
  19
  20 /* memory reserved for fb */
  21 /memreserve/ 0x9F82D000 0x4B1000; /* 480*854*4*3, 4K alignment, for display size*/
  22
  23 /* memory reserved for ION */
  24 /memreserve/ 0x9FCDE000 0x322000; /* 480*854*4*2, 8K alignment, for display size*/
  25
  26 /include/ "skeleton.dtsi"
  27 /include/ "scx30g-clocks.dtsi"
  28 /include/ "scx30g-regulators.dtsi"
  29 /include/ "sprd-sound.dtsi"
  30 /include/ "sprd-battery.dtsi"
  31
  32 / {
  33         model = "Spreadtrum SP8835EB board";
  34         compatible = "sprd,sp8835eb";
  35         sprd,sc-id = <8830 1 0x20000>;
  36         #address-cells = <1>;
  37         #size-cells = <1>;
  38         interrupt-parent = <&gic>;
  39
  40         chosen {
  41                 bootargs = "loglevel=1 console=ttyS1,115200n8 init=/init root=/dev/ram0 rw";
  42                 linux,initrd-start = <0x85500000>;
  43                 linux,initrd-end   = <0x855a3212>;
  44         };
  45
  46         memory {
  47                 device_type = "memory";
  48                 reg = <0x80000000 0x40000000>;
  49         };
  50
  51         aliases {
  52                 serial0 = &uart0;
  53                 serial1 = &uart1;
  54                 serial2 = &uart2;
  55                 serial3 = &uart3;
  56                 i2c0 = &i2c0;
  57                 i2c1 = &i2c1;
  58                 i2c2 = &i2c2;
  59                 i2c3 = &i2c3;
  60                 lcd0 = &fb0;
  61                 spi0 = &spi0;
  62                 spi1 = &spi1;
  63                 spi2 = &spi2;
  64                 hwspinlock0 = &hwspinlock0;
  65                 hwspinlock1 = &hwspinlock1;
  66         };
  67
  68         cpus {
  69                 #address-cells = <1>;
  70                 #size-cells = <0>;
  71
  72                 cpu@f00 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a7";
  75                         reg = <0xf00>;
  76                 };
  77
  78                 cpu@f01 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a7";
  81                         reg = <0xf01>;
  82                 };
  83
  84                 cpu@f02 {
  85                         device_type = "cpu";
  86                         compatible = "arm,cortex-a7";
  87                         reg = <0xf02>;
  88                 };
  89
  90                 cpu@f03 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a7";
  93                         reg = <0xf03>;
  94                 };
  95         };
  96         pmu {
  97                 compatible = "arm,cortex-a7-pmu";
  98                 interrupts = <0 92 0x0>,
  99                                 <0 93 0x0>,
 100                                 <0 94 0x0>,
 101                                 <0 95 0x0>;
 102         };
 103
 104     gic: interrupt-controller@12001000 {
 105         compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
 106         #interrupt-cells = <3>;
 107         #address-cells = <0>;
 108         interrupt-controller;
 109         reg = <0x12001000 0x1000>,
 110               <0x12002000 0x1000>;
 111     };
 112
 113         uart0: uart@70000000 {
 114                 compatible  = "sprd,serial";
 115                 interrupts = <0 2 0x0>;
 116                 reg = <0x70000000 0x1000>;
 117                 clock-names = "clk_uart0";
 118                 clocks = <&clock 60>;
 119                 sprdclk = <48000000>;
 120                 sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP";
 121         };
 122         uart1: uart@70100000 {
 123                 compatible  = "sprd,serial";
 124                 interrupts = <0 3 0x0>;
 125                 reg = <0x70100000 0x1000>;
 126                 clock-names = "clk_uart1";
 127                 clocks = <&clock 61>;
 128                 sprdclk = <26000000>;
 129                 sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP";
 130         };
 131         uart2: uart@70200000 {
 132                 compatible  = "sprd,serial";
 133                 interrupts = <0 4 0x0>;
 134                 reg = <0x70200000 0x1000>;
 135                 clock-names = "clk_uart2";
 136                 clocks = <&clock 62>;
 137                 sprdclk = <26000000>;
 138                 sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP";
 139         };
 140         uart3: uart@70300000 {
 141                 compatible  = "sprd,serial";
 142                 interrupts = <0 5 0x0>;
 143                 reg = <0x70300000 0x1000>;
 144                 clock-names = "clk_uart3";
 145                 clocks = <&clock 63>;
 146                 sprdclk = <26000000>;
 147                 sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP";
 148         };
 149
 150         timer {
 151                 compatible  = "sprd,scx35-timer";
 152                 reg =   <0x40230000 0x1000>, /* SYSCNT */
 153                         <0x40050000 0x1000>, /* GPTIMER0 */
 154                         <0x40220000 0x1000>, /* APTIMER0 */
 155                         <0x40330000 0x1000>, /* APTIMER1 */
 156                         <0x40340000 0x1000>; /* APTIMER2 */
 157                 interrupts = <0 118 0x0>,
 158                                 <0 28 0x0>,
 159                                 <0 29 0x0>,
 160                                 <0 119 0x0>,
 161                                 <0 121 0x0>,
 162                                 <0 31 0x0>;/*ap system timer*/
 163         };
 164         clock: clockdevice {
 165                 compatible = "sprd,scx35-clock";
 166                 #clock-cells = <1>;
 167         };
 168         d_eic_gpio: gpio@40210000{
 169                 compatible = "sprd,d-eic-gpio";
 170                 reg = <0x40210000 0x1000>;
 171                 gpio-controller;
 172                 interrupt-controller;
 173                 #interrupt-cells = <2>;
 174                 #gpio-cells = <2>;
 175                 gpiobase = <288>;
 176                 ngpios = <16>;
 177                 interrupts = <0 37 0x0>;
 178         };
 179         d_gpio_gpio: gpio@40280000{
 180                 compatible = "sprd,d-gpio-gpio";
 181                 reg = <0x40280000 0x1000>;
 182                 gpio-controller;
 183                 interrupt-controller;
 184                 #interrupt-cells = <2>;
 185                 #gpio-cells = <2>;
 186                 gpiobase = <0>;
 187                 ngpios = <256>;
 188                 interrupts = <0 35 0x0>;
 189         };
 190         pinctrl{
 191                 compatible = "sprd,pinctrl";
 192                 reg = <0x402a0000 0x1000>;
 193                 pwr_domain = "vdd28",
 194                                          "vdd28",
 195                                          "vddsim0",
 196                                          "vddsim1",
 197                                          "vddsim2",
 198                                          "vddsd",
 199                                          "vdd18";
 200                 ctrl_desc = <0x10 0 1
 201                                     0x10 1 1
 202                                     0x10 2 1
 203                                     0x10 3 1
 204                                     0x10 4 1
 205                                     0x10 5 1
 206                                     0x10 6 1>;
 207         };
 208         adic:adic{
 209                 compatible = "sprd,adi";
 210                 reg = <0x40030000 0x10000>;
 211         };
 212          adi: adi_bus{
 213                  compatible = "sprd,adi-bus";
 214                  interrupts = <0 38 0x0>;
 215                  reg = <0x40038000 0x1000>;
 216                  interrupt-controller;
 217                  sprd,irqnums = <11>;
 218                  #interrupt-cells = <2>;
 219                  #address-cells = <1>;
 220                  #size-cells = <1>;
 221                  ranges = <0X40 0x40038040 0x40>,
 222                                   <0x80 0x40038080 0x80>,
 223                                   <0x100 0x40038100 0x80>,
 224                                   <0x480 0x40038480 0x80>;
 225                  sprd_backlight {
 226                         compatible = "sprd,sprd_backlight";
 227                         start = <3>;
 228                         end = <3>;
 229                         flags = <0x100>;
 230                  };
 231                  headset_detect {
 232                         compatible = "sprd,headset-detect";
 233                         gpio_switch = <0>;
 234                         gpio_detect = <309>;
 235                         gpio_button = <307>;
 236                         irq_trigger_level_detect = <1>;
 237                         irq_trigger_level_button = <1>;
 238                         adc_threshold_3pole_detect = <100>;
 239                         adc_threshold_4pole_detect = <3100>;
 240                         irq_threshold_buttont = <1>;
 241                         voltage_headmicbias = <3000000>;
 242                         nbuttons = <1>;
 243                         headset_buttons {
 244                                 adc_min = <0>;
 245                                 adc_max = <170>;
 246                                 code = <226>;
 247                                 type = <0>;
 248                         };
 249                  };
 250                  keyboard_backlight {
 251                         compatible = "sprd,keyboard-backlight";
 252                  };
 253                  watchdog@40{
 254                         compatible = "sprd,watchdog";
 255                         reg = <0X40 0x40>;
 256                         interrupts = <3 0x0>;
 257                  };
 258                  rtc@80{
 259                         compatible = "sprd,rtc";
 260                         reg = <0X80 0x80>;
 261                         interrupts = <2 0x0>;
 262                 };
 263                  a_eic_gpio: gpio@100{
 264                          compatible = "sprd,a-eic-gpio";
 265                          reg = <0X100 0x80>; /* adi reg */
 266                          gpio-controller;
 267                          interrupt-controller;
 268                          #interrupt-cells = <2>;
 269                          #gpio-cells = <2>;
 270                          gpiobase = <304>;
 271                          ngpios = <16>;
 272                          interrupt-parent = <&adi>;
 273                          interrupts = <5 0x0>; /* ext irq 5 */
 274                  };
 275                  a_gpio_gpio: gpio@480{
 276                          compatible = "sprd,a-gpio-gpio";
 277                          reg = <0X480 0x80>; /* adi reg */
 278                          gpio-controller;
 279                          interrupt-controller;
 280                          #interrupt-cells = <2>;
 281                          #gpio-cells = <2>;
 282                          gpiobase = <256>;
 283                          ngpios = <32>;
 284                          interrupt-parent = <&adi>;
 285                          interrupts = <1 0x0>; /* ext irq 1 */
 286                  };
 287          };
 288          keypad@40250000{
 289                  compatible = "sprd,sci-keypad";
 290                  reg = <0x40250000 0x1000>;
 291                  gpios = <&a_eic_gpio 2 0>;
 292                  interrupts = <0 36 0x0>;
 293                  sprd,keypad-num-rows = <2>;
 294                  sprd,keypad-num-columns = <2>;
 295                  sprd,keypad-rows-choose-hw = <0x30000>;
 296                  sprd,keypad-cols-choose-hw = <0x300>;
 297                  sprd,debounce_time = <5000>;
 298                  linux,keypad-no-autorepeat;
 299                  sprd,support_long_key;
 300
 301                  key_volume_down {
 302                          keypad,row = <0>;
 303                          keypad,column = <0>;
 304                          linux,code = <114>;
 305                  };
 306                  key_volume_up {
 307                          keypad,row = <1>;
 308                          keypad,column = <0>;
 309                          linux,code = <115>;
 310                  };
 311                  key_home {
 312                          keypad,row = <0>;
 313                          keypad,column = <1>;
 314                          linux,code = <102>;
 315                  };
 316          };
 317          sprd_vsp@60900000{
 318                  compatible = "sprd,sprd_vsp";
 319                  reg = <0x60900000 0xc000>;
 320                  interrupts = <0 43 0x0>;
 321                  clock-names = "clk_mm_i", "clk_vsp", "clk_parent_0", "clk_parent_1", "clk_parent_2", "clk_parent_3";
 322                  clocks = <&clk_mm>, <&clk_vsp>, <&clk_256m>, <&clk_192m>, <&clk_128m>, <&clk_76m8>;
 323                  clock-parent-info = <2 4>;
 324                  version = <2>;
 325          };
 326         sprd_jpg {
 327                  compatible = "sprd,sprd_jpg";
 328                  reg = <0x60b00000 0x8000>;
 329                  interrupts = <0 42 0x0>;
 330                  clock-names = "clk_mm_i","clk_jpg";
 331                  clocks = <&clk_mm>, <&clk_jpg>;
 332          };
 333
 334
 335          i2c0: i2c@70500000 {
 336                  compatible  = "sprd,i2c";
 337                  interrupts = <0 11 0x0>;
 338                  reg = <0x70500000 0x1000>;
 339                  #address-cells = <1>;
 340                  #size-cells = <0>;
 341                  sensor_main@0x3c{
 342                         compatible = "sprd,sensor_main";
 343                         reg = <0x3c>;
 344                  };
 345                  sensor_sub@0x21{
 346                         compatible = "sprd,sensor_sub";
 347                         reg = <0x21>;
 348                  };
 349          };
 350          i2c1: i2c@70600000 {
 351                  compatible  = "sprd,i2c";
 352                  interrupts = <0 12 0x0>;
 353                  reg = <0x70600000 0x1000>;
 354                  #address-cells = <1>;
 355                  #size-cells = <0>;
 356                 focaltech_ts@38{
 357                         compatible = "focaltech,focaltech_ts";
 358                         reg = <0x38>;
 359                         gpios = <&d_gpio_gpio 81 0
 360                                 &d_gpio_gpio 82 0>;
 361                         vdd_name = "vdd28";
 362                         virtualkeys = <130 1360 80 60
 363                                    373 1360 80 60
 364                                    630 1360 80 60>;
 365                         TP_MAX_X = <480>;
 366                         TP_MAX_Y = <854>;
 367                 };
 368          };
 369          i2c2: i2c@70700000{
 370                  compatible  = "sprd,i2c";
 371                  interrupts = <0 13 0x0>;
 372                  reg = <0x70700000 0x1000>;
 373                  #address-cells = <1>;
 374                  #size-cells = <0>;
 375                 lis3dh_acc@18{
 376                         compatible = "ST,lis3dh_acc";
 377                         reg = <0x18>;
 378                         poll_interval = <10>;
 379                         min_interval = <10>;
 380                         g_range = <0>;
 381                         axis_map_x = <1>;
 382                         axis_map_y = <0>;
 383                         axis_map_z = <2>;
 384                         negate_x = <0>;
 385                         negate_y = <1>;
 386                         negate_z = <0>;
 387                 };
 388                 ltr_558als@23{
 389                         compatible = "LITEON,ltr_558als";
 390                         reg = <0x23>;
 391                         gpios = <&d_gpio_gpio 216 0>;
 392                 };
 393          };
 394          i2c3: i2c@70800000{
 395                  compatible  = "sprd,i2c";
 396                  interrupts = <0 14 0x0>;
 397                  reg = <0x70800000 0x1000>;
 398                  #address-cells = <1>;
 399                  #size-cells = <0>;
 400          };
 401          sprd_dcam{
 402                  compatible  = "sprd,sprd_dcam";
 403                  interrupts = <0 45 0>;
 404                  reg = <0x60800000 0x100000>;
 405                  clock-names = "clk_mm_i","clk_dcam";
 406                  clocks = <&clk_mm>, <&clk_dcam>;
 407          };
 408          sprd_scale {
 409                  compatible  = "sprd,sprd_scale";
 410          };
 411          sprd_rotation {
 412                  compatible  = "sprd,sprd_rotation";
 413          };
 414          sprd_sensor {
 415                  compatible  = "sprd,sprd_sensor";
 416                  reg = <0x60c00000 0x1000>;
 417                  gpios = <&d_gpio_gpio 186 0   /*main reset*/
 418                         &d_gpio_gpio 187 0     /*main power down*/
 419                         &d_gpio_gpio 186 0     /*sub reset*/
 420                         &d_gpio_gpio 188 0     /*sub power down*/
 421                         &d_gpio_gpio 0 0       /*main core voltage*/
 422                         &d_gpio_gpio 0 0
 423                         &d_gpio_gpio 0 0
 424                         &d_gpio_gpio 0 0>;
 425                  clock-names ="clk_mm_i","clk_sensor","clk_ccir","clk_dcam","clk_dcam_mipi";
 426                  clocks = <&clk_mm>, <&clk_sensor>,<&clk_ccir>, <&clk_dcam>, <&clk_dcam_mipi>;
 427                  };
 428         sprd_isp {
 429                 compatible  = "sprd,sprd_isp";
 430                 reg = <0x60a00000 0x100000>;
 431                 clock-names = "clk_mm_i","clk_isp";
 432                 clocks = <&clk_mm>, <&clk_isp>;
 433         };
 434         sprd_dma_copy {
 435                 compatible  = "sprd,sprd_dma_copy";
 436         };
 437         fb0: fb@20800000 {
 438                 compatible = "sprd,sprdfb";
 439                 reg = <0x20800000 0x1000>,<0x21800000 0x1000>;
 440                 interrupts = <0 46 0x0>,<0 48 0x0>, <0 49 0x0>;
 441                 clock-names = "dispc_clk_parent", "dispc_dbi_clk_parent", "dispc_dpi_clk_parent", "dispc_emc_clk_parent", "dispc_clk", "dispc_dbi_clk", "dispc_dpi_clk", "dispc_emc_clk", "fb_spi_clock", "fb_spi_clock_parent";
 442                 clocks = <&clk_256m>, <&clk_256m>, <&clk_384m>, <&clk_aon_apb>, <&clk_dispc0>, <&clk_dispc0_dbi>, <&clk_dispc0_dpi>, <&clk_disp_emc>, <&clk_spi2>, <&ext_26m>;
 443                 clock-src = <256000000 256000000 384000000>;
 444                 dpi_clk_div = <7>;
 445                 sprd,fb_use_reservemem;
 446                 sprd,fb_mem = <0x9F82D000 0x4B1000>;
 447                 sprd,fb_display_size = <480 854>;
 448         };
 449         gsp:gsp@20a00000 {
 450                 compatible = "sprd,gsp";
 451                 reg = <0x20a00000 0x1000>;
 452                 interrupts = <0 51 0x0>;
 453                 clock-names = "clk_gsp", "clk_gsp_emc", "clk_gsp_parent", "clk_aon_apb";
 454                 clocks = <&clk_gsp>, <&clk_gsp_emc>, <&clk_256m>, <&clk_aon_apb>;
 455                 gsp_mmu_ctrl_base = <0x21408000>;
 456         };
 457
 458         sprd_fm: sprd_fm@40270000{
 459                 compatible  = "sprd,sprd_fm";
 460                 reg = <0x40270000 0x1000>,/*FM base*/
 461                         <0x402E0000 0x10000>, /*AONAPB base*/
 462                         <0x402B0000 0x10000>, /*PMU base*/
 463                         <0x402D0000 0x1000>,  /*AONCKG base*/
 464                         <0x402A0000 0x1000> ; /*PIN base*/
 465         };
 466
 467         /* sipc initializer */
 468         sipc: sipc@0x87800000 {
 469                 compatible = "sprd,sipc";
 470                 reg = <0x87800000 0x200000>; /* <SMEM SIZE>*/
 471                 //#interrupt-cells = <2>;
 472                 #address-cells = <1>;
 473                 #size-cells = <1>;
 474                 ranges = <0x8000000 0x88000000 0x1b00000>,
 475                                 <0x07800000 0x87800000 0x140000>,
 476                                 <0x9aff000 0x89aff000 0x1000>,
 477                                 <0x0a800000 0x8a800000 0x201000>,/*WCN MEMORY:OFFSET ADDRESS SIZE*/
 478                                 <0x07940000 0x87940000 0xc0000>,
 479                                 <0x0aa00000 0x8aa00000 0x1000>;/*WCN SIPC-RING:OFFSET ADDRESS SIZE*/
 480                 sipc_cpw@0x8000000 {
 481                         sprd,name = "sipc-w";
 482                         sprd,dst = <2>;
 483                         sprd,ap2cp = <0x402c0000>; /* base on ipi reggister */
 484                         sprd,cp2ap = <0x402c0004>;
 485                         sprd,trig = <0x01>; /* trigger bit */
 486                         sprd,clr = <0x01>; /* clear bit */
 487                         interrupts = <0 68 0x0>;
 488                         reg = <0x8000000 0x1b00000> , /* <CP_start_addr size> */
 489                                 <0x07800000 0x140000>, /* <SMEM_phy_addr total_size> */
 490                                 <0x9aff000 0x1000>; /* smsg ring buffer <base size> */
 491                 };
 492                 sipc_wcn@0x0a800000 {
 493                         sprd,name = "sipc-wcn";
 494                         sprd,dst = <3>;
 495                         sprd,ap2cp = <0x402c0000>; /* base on ipi reggister */
 496                         sprd,cp2ap = <0x402c0004>;
 497                         sprd,trig = <0x100>; /* trigger bit */
 498                         sprd,clr = <0x100>; /* clear bit */
 499                         interrupts = <0 73 0x0>;
 500                         reg = <0x0a800000 0x201000> , /* <CP_start_addr size> */
 501                                 <0x07940000 0xc0000>, /* <SMEM_phy_addr total_size> */
 502                                 <0x0aa00000 0x1000>; /* smsg ring buffer <base size> */
 503                 };
 504
 505         };
 506
 507
 508         /* cpw virtual devices */
 509
 510         spipe-cpw {
 511                 compatible = "sprd,spipe";
 512                 sprd,name = "spipe_w";
 513                 sprd,dst = <2>;
 514                 sprd,channel = <4>;
 515                 sprd,ringnr = <9>;
 516                 sprd,size-rxbuf = <0x1000>; /* 4*1024 */
 517                 sprd,size-txbuf = <0x1000>; /* 4*1024 */
 518         };
 519
 520         slog-cpw {
 521                 compatible = "sprd,spipe";
 522                 sprd,name = "slog_w";
 523                 sprd,dst = <2>;
 524                 sprd,channel = <5>;
 525                 sprd,ringnr = <1>;
 526                 sprd,size-rxbuf = <0x40000>; /* 256*1024*/
 527                 sprd,size-txbuf = <0x8000>; /* 32*1024 */
 528         };
 529
 530         stty-cpw {
 531                 compatible = "sprd,spipe";
 532                 sprd,name = "stty_w";
 533                 sprd,dst = <2>;
 534                 sprd,channel = <6>;
 535                 sprd,ringnr = <32>;
 536                 sprd,size-rxbuf = <0x0800>; /* 2*1024*/
 537                 sprd,size-txbuf = <0x0800>; /* 2*1024 */
 538         };
 539
 540         seth0-cpw {
 541                 compatible = "sprd,seth";
 542                 sprd,name = "seth_w0";
 543                 sprd,dst = <2>;
 544                 sprd,channel = <7>;
 545                 sprd,blknum = <64>;
 546         };
 547
 548         seth1-cpw {
 549                 compatible = "sprd,seth";
 550                 sprd,name = "seth_w1";
 551                 sprd,dst = <2>;
 552                 sprd,channel = <8>;
 553                 sprd,blknum = <64>;
 554         };
 555
 556         seth2-cpw {
 557                 compatible = "sprd,seth";
 558                 sprd,name = "seth_w2";
 559                 sprd,dst = <2>;
 560                 sprd,channel = <9>;
 561                 sprd,blknum = <64>;
 562         };
 563
 564         scproc_cpw: scproc@0x88000000 {
 565                 compatible = "sprd,scproc";
 566                 sprd,name = "cpw";
 567                 sprd,ctrl-reg = <0x44 0x44 0xb0 0xff>; /* <shut_down deep_sleep reset get_status> */
 568                 sprd,ctrl-mask = <0x02000000 0x10000000 0x01 0xf0000>; /* masks <> */
 569                 sprd,iram-data = <0xe59f0000 0xe12fff10 0x88300000>; /* 3rd param equals modem_addr*/
 570                 reg = <0x88000000 0x1b00000>, /* <CP_start_addr total_size> = <+128M 26M> */
 571                         <0x50000000 0x0c>, /* <iram1_base size> */
 572                         <0x402b0000 0x10000>, /* <pmu_base size> */
 573                         <0x402b0000 0x10000>, /* <pmu_base size> */
 574                         <0x402b0000 0x10000>, /* <pmu_base size> */
 575                         <0x402b0000 0x10000>; /* <pmu_base size> */
 576                 interrupts = <0 84 0x0>; /* cp1_wdg_int */
 577                 #address-cells = <1>;
 578                 #size-cells = <1>;
 579                 /* segnr=2 */
 580                 ranges = <0x300000 0x88300000 0x00800000>,
 581                                 <0x20000 0x88020000 0x00220000>;
 582                 modem@0x300000 {
 583                         cproc,name = "modem";
 584                         reg = <0x300000 0x00800000>; /* <modem_addr size> */
 585                 };
 586                 dsp@0x20000 {
 587                         cproc,name = "dsp";
 588                         reg = <0x20000 0x00220000>; /* <dsp_addr size>*/
 589                 };
 590         };
 591
 592         saudio_w{
 593                 compatible = "sprd,saudio";
 594                 sprd,saudio-dst-id = <2>;
 595                 sprd,ctrl_channel = <10>;       /* SMSG_CH_VBC */
 596                 sprd,playback_channel = <11>;   /* SMSG_CH_PLAYBACK */
 597                 sprd,capture_channel = <12>;    /* SMSG_CH_CAPTURE */
 598                 sprd,monitor_channel = <13>;    /*SMSG_CH_MONITOR_AUDIO */
 599                 sprd,saudio-names = "VIRTUAL AUDIO W";
 600         };
 601         saudio_voip{
 602                 compatible = "sprd,saudio";
 603                 sprd,saudio-dst-id = <2>;
 604                 sprd,ctrl_channel = <14>;       /* SMSG_CH_CTRL_VOIP */
 605                 sprd,playback_channel = <15>;   /* SMSG_CH_PLAYBACK_VOIP */
 606                 sprd,capture_channel = <16>;    /* SMSG_CH_CAPTURE_VOIP */
 607                 sprd,monitor_channel = <17>;    /*SMSG_CH_MONITOR_VOIP */
 608                 sprd,saudio-names = "saudiovoip";
 609         };
 610
 611         /* cpwcn virtual devices */
 612
 613         spipe_cpwcn {
 614                 compatible = "sprd,spipe";
 615                 sprd,name = "spipe_wcn";
 616                 sprd,dst = <3>;
 617                 sprd,channel = <4>;
 618                 sprd,ringnr = <12>;
 619                 sprd,size-rxbuf = <0x1000>; /* 4*1024 */
 620                 sprd,size-txbuf = <0x1000>; /* 4*1024 */
 621         };
 622
 623         slog_cpwcn {
 624                 compatible = "sprd,spipe";
 625                 sprd,name = "slog_wcn";
 626                 sprd,dst = <3>;
 627                 sprd,channel = <5>;
 628                 sprd,ringnr = <1>;
 629                 sprd,size-rxbuf = <0x40000>; /* 256*1024*/
 630                 sprd,size-txbuf = <0x8000>; /* 32*1024 */
 631         };
 632
 633         stty4bt_cpwcn {
 634                 compatible = "sprd,stty4bt";
 635                 sprd,name = "sttybt";
 636                 sprd,dst = <3>;
 637                 sprd,channel = <4>;
 638                 sprd,bufid = <10>;
 639         };
 640
 641
 642         scproc_cpwcn: scproc@0x8a800000 {
 643                 compatible = "sprd,scproc";
 644                 sprd,name = "cpwcn";
 645                 sprd,ctrl-reg = <0x68 0x68 0xb0 0xb0>; /* <shut_down deep_sleep reset get_status> */
 646                 sprd,ctrl-mask = <0x02000000 0x10000000 0x04 0x04>; /* masks <> */
 647                 sprd,iram-data = <0xe59f0000 0xe12fff10 0x8a808000>; /* 3rd param equals modem_addr*/
 648                 reg = <0x8a800000 0x201000>, /* <CP_start_addr total_size> = <+168M 2M+4k> */
 649                         <0x50003000 0x1000>, /* <iram1_phys size> use iram1 phys because of cp2 iram not maped */
 650                         <0x402b0000 0x10000>, /* <pmu_base size> */
 651                         <0x402b0000 0x10000>, /* <pmu_base size> */
 652                         <0x402b0000 0x10000>, /* <pmu_base size> */
 653                         <0x402b0000 0x10000>; /* <pmu_base size> */
 654                 interrupts = <0 85 0x0>; /* cp2_wdg_int */
 655                 #address-cells = <1>;
 656                 #size-cells = <1>;
 657                 /* segnr=1 */
 658                 ranges = <0x8000 0x8a808000 0x201000>;
 659                 modem@0x8000 {
 660                         cproc,name = "modem";
 661                         reg = <0x8000 0x201000>; /* <modem_addr size> */
 662                 };
 663         };
 664
 665         sprd_wlan{
 666                 compatible = "sprd,sprd_wlan";
 667         };
 668
 669         sdios{
 670                 #address-cells = <2>;
 671                 #size-cells = <2>;
 672                 ranges;
 673                 sdio3: sdio@20600000{
 674                         compatible  = "sprd,sdhost-3.0";
 675                         reg = <0 0x20600000 0 0x1000>;
 676                         interrupts = <0 60 0x0>;
 677                         sprd,name = "sdio_emmc";
 678                         /*detect_gpio = <-1>; */
 679                         SD_Pwr_Name = "vddemmccore";
 680                         _1_8V_signal_Name = "vddemmcio";
 681                         signal_default_Voltage = <1800000>;
 682                         ocr_avail = <0x00040000>;
 683                         clocks = <&clk_emmc>, <&clk_384m>;
 684                         base_clk = <384000000>;
 685                         caps = <0xC00F8D47>;
 686                         caps2 = <0x202>;
 687                         pm_caps = <0x4>;
 688                         writeDelay = <0x4>;
 689                         readPosDelay = <0x4>;
 690                         readNegDelay = <0x4>;
 691                 };
 692
 693                 sdio0: sdio@20300000{
 694                         compatible  = "sprd,sdhost-3.0";
 695                         reg = <0 0x20300000 0 0x1000>;
 696                         interrupts = <0 57 0x0>;
 697                         sprd,name = "sdio_sd";
 698                         detect_gpio = <141>;
 699                         SD_Pwr_Name = "vddsd";
 700                         /* _1_8V_signal_Name = "vddsdio"; */
 701                         signal_default_Voltage = <3000000>;
 702                         ocr_avail = <0x00040000>;
 703                         clocks = <&clk_sdio0>, <&clk_384m>;
 704                         base_clk = <384000000>;
 705                         caps = <0xC0000407>;
 706                         caps2 = <0x200>;
 707                         pm_caps = <0x4>;
 708                         writeDelay = <0x4>;
 709                         readPosDelay = <0x4>;
 710                         readNegDelay = <0x4>;
 711                 };
 712
 713
 714                 sdio1: sdio@20400000{
 715                         compatible  = "sprd,sdhost-3.0";
 716                         reg = <0 0x20400000 0 0x1000>;
 717                         interrupts = <0 58 0x0>;
 718                         sprd,name = "sdio_wifi";
 719                         /* detect_gpio = <-1>; */
 720                         /* SD_Pwr_Name = "vddsdcore"; */
 721                         /* _1_8V_signal_Name = "vddsdio";*/
 722                         /* signal_default_Voltage = <3000000>; */
 723                         ocr_avail = <0x00360080>;
 724                         clocks = <&clk_sdio1>, <&clk_96m>;
 725                         base_clk = <96000000>;
 726                         caps = <0xC00FA407>;
 727                         caps2 = <0x0>;
 728                         pm_caps = <0x5>;
 729                         writeDelay = <0x03>;
 730                         readPosDelay = <0x03>;
 731                         readNegDelay = <0x03>;
 732                 };
 733         };
 734
 735          usb: usb@20200000{
 736                  compatible  = "sprd,usb";
 737                  interrupts = <0 55 0x0>;
 738                 ngpios = <2>;
 739                 gpios = <&a_eic_gpio 0 0>,<&d_gpio_gpio 72 0>;
 740                  reg = <0x20200000 0x1000>;
 741                  tune_value = <0x44073e33>;
 742                  usb-supply = <&vddusb>;
 743                  #address-cells = <1>;
 744                  #size-cells = <0>;
 745          };
 746         sprd_thermal {
 747                 compatible = "sprd,sprd-thermal";
 748                 id = <0>;
 749                 interrupts = <0 26 0x0>;
 750                 reg = <0x402f0000 0x1000>;
 751                 trip_points_active = <65 69 95 110>;
 752                 trip_points_lowoff = <0 57 61 80>;
 753                 trip_points_critical = <110>;
 754                 trip_num = <5>;
 755         };
 756         sprd_cpu_cooling{
 757                 compatible = "sprd,sprd-cpu-cooling";
 758                 id = <0>;
 759                 max_freq = <1300000 1200000 1000000 768000>;
 760                 max_core = <4 4 4 1>;
 761                 state_num = <4>;
 762         };
 763
 764          spi0: spi@70a00000{
 765                  compatible  = "sprd,sprd-spi";
 766                  interrupts = <0 7 0x0>;
 767                  reg = <0x70a00000 0x1000>;
 768                  clock-names = "clk_spi0";
 769                  #address-cells = <1>;
 770                  #size-cells = <0>;
 771          };
 772          spi1: spi@70b00000{
 773                  compatible  = "sprd,sprd-spi";
 774                  interrupts = <0 8 0x0>;
 775                  reg = <0x70b00000 0x1000>;
 776                  clock-names = "clk_spi1";
 777                  #address-cells = <1>;
 778                  #size-cells = <0>;
 779          };
 780          spi2: spi@70c00000{
 781                  compatible  = "sprd,sprd-spi";
 782                  interrupts = <0 9 0x0>;
 783                  reg = <0x70c00000 0x1000>;
 784                  clock-names = "clk_spi2";
 785                  #address-cells = <1>;
 786                  #size-cells = <0>;
 787          };
 788          dmac: dmac@20100000{
 789                  compatible  = "sprd,sprd-dma";
 790                  interrupts = <0 50 0x0>;
 791                  reg = <0x20100000 0x4000>;
 792          };
 793          adc: adc@40038300{
 794                  compatible  = "sprd,sprd-adc";
 795                  reg = <0x40038300 0x400>;
 796          };
 797          hwspinlock0: hwspinlock0@20c00000{
 798                  compatible  = "sprd,sprd-hwspinlock";
 799                  reg = <0x20c00000 0x1000>;
 800          };
 801          hwspinlock1: hwspinlock1@40060000{
 802                  compatible  = "sprd,sprd-hwspinlock";
 803                  reg = <0x40060000 0x1000>;
 804          };
 805         gpu@60000000 {
 806                 compatible = "arm,mali-400", "arm,mali-utgard";
 807                 reg = <0x60000000 0x10000>;
 808                 interrupts = <0 39 0>, <0 39 0>, <0 39 0>, <0 39 0>, <0 39 0>, <0 39 0>, <0 39 0>;
 809                 interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1", "IRQPMU";
 810
 811                 pmu_domain_config = <0x1000 0x1000 0x1000 0x0 0x0 0x0 0x0 0x0 0x0 0x1000 0x0 0x0>;
 812                 pmu_switch_delay = <0xffff>;
 813
 814                 clocks = <&clk_gpu_axi>,<&clk_gpu>,<&clk_153m6>,<&clk_208m>,<&clk_256m>,<&clk_312m>,<&clk_384m>,<&clk_460m8>;
 815                 clock-names = "clk_gpu_axi","clk_gpu","clk_153m6","clk_208m","clk_256m","clk_312m","clk_384m","clk_460m8";
 816
 817                 freq-list-len = <4>;
 818                 freq-lists = <153600 2 1>, <256000 4 1>, <384000 6 1>, <460800 7 1>;
 819                 freq-default = <1>;
 820                 freq-9 = <2>;
 821                 freq-8 = <1>;
 822                 freq-7 = <0>;
 823                 freq-5 = <0>;
 824                 freq-range-max = <3>;
 825                 freq-range-min = <0>;
 826         };
 827          ion {
 828                  compatible = "sprd,ion-sprd";
 829                  #address-cells = <1>;
 830                  #size-cells = <0>;
 831
 832                  sprd,ion-heap@1 {
 833                        reg = <1>;                      /* SYSTEM */
 834                        reg-names = "ion_heap_system";
 835                        sprd,ion-heap-type = <0>;       /* SYSTEM */
 836                        sprd,ion-heap-mem = <0x0 0x0>;
 837                  };
 838
 839                  sprd,ion-heap@2 {
 840                        reg = <2>;                      /* MM */
 841                        reg-names = "ion_heap_carveout_mm";
 842                        sprd,ion-heap-type = <0>;       /* carveout mm */
 843                        sprd,ion-heap-mem = <0x98800000 0x7100000>;
 844                  };
 845
 846                  sprd,ion-heap@3 {
 847                        reg = <3>;                      /* OVERLAY */
 848                        reg-names = "ion_heap_carveout_overlay";
 849                        sprd,ion-heap-type = <2>;       /* CARVEOUT */
 850                        sprd,ion-heap-mem = <0x9FCDE000 0x322000>;/* 480*854*4*2, 8K alignment, for display size*/
 851                  };
 852          };
 853          sprd_iommu0:sprd_iommu@21400000 {
 854                  compatible  = "sprd,sprd_iommu";//gsp
 855                  func-name = "sprd_iommu_gsp";
 856                  reg = <0x10000000 0x2000000>, //iova
 857                        <0x21400000 0x8000>,  //pgt
 858                        <0x21408000 0x8000>;  //ctrl_reg
 859                  reg_name = "iova","pgt","ctrl_reg";
 860                  clock-names = "clk_gsp_emc","clk_153m6","clk_gsp";
 861                  clocks = <&clk_gsp_emc>, <&clk_153m6>,<&clk_gsp>;
 862                  status = "ok";
 863          };
 864          sprd_iommu1:sprd_iommu@60f00000 {
 865                  compatible  = "sprd,sprd_iommu";//mm
 866                  func-name = "sprd_iommu_mm";
 867                  reg = <0x20000000 0x8000000>,   //iova
 868                        <0x60f00000 0x20000>,     //pgt
 869                        <0x60f20000 0x2000>;      //ctrl_reg
 870                  reg_name = "iova","pgt","ctrl_reg";
 871                  clock-names = "clk_mmu","clk_mm_i";
 872                  clocks = <&clk_mmu>,<&clk_mm>;
 873                  status = "ok";
 874          };
 875
 876          sprd_rf2351: sprd_rf2351@40070000{
 877                 compatible  = "sprd,sprd_rf2351";
 878                 reg = <0X40070000 0x1000>,              /*RFSPI*/
 879                         <0X402E0000 0x10000>;           /*APB_EB0*/
 880                 clock-names = "clk_cpll";
 881                 clocks = <&clk_cpll>;
 882          };
 883          gps_2351: gps_2351@21c00000{
 884                 compatible  = "sprd,gps_2351";
 885                 interrupts = <0 52 0x0>;
 886                 gpios = <&d_gpio_gpio 50 0>;
 887                 reg = <0X21C00000 0x1000>,              /*GPS CORE BASE*/
 888                         <0X20D00000 0x10000>,           /*AHB_ADDR*/
 889                         <0X402B0000 0x10000>;           /*PMU BASE*/
 890          };
 891
 892         sprd-io-base {
 893                 #address-cells = <1>;
 894                 #size-cells = <1>;
 895                 ranges = <0 0 0x80000000>;
 896                 ahb {
 897                         compatible = "sprd,ahb";
 898                         reg = <0x20d00000 0x10000>;
 899                 };
 900                 aonapb {
 901                         compatible = "sprd,aonapb";
 902                         reg = <0x402e0000 0x10000>;
 903                 };
 904                 apbreg {
 905                         compatible = "sprd,apbreg";
 906                         reg = <0x71300000 0x10000>;
 907                 };
 908                 pmu {
 909                         compatible = "sprd,pmu";
 910                         reg = <0x402b0000 0x10000>;
 911                 };
 912                 mmahb {
 913                         compatible = "sprd,mmahb";
 914                         reg = <0x60d00000 0x4000>;
 915                 };
 916                 mmckg {
 917                         compatible = "sprd,mmckg";
 918                         reg = <0x60e00000 0x1000>;
 919                 };
 920                 adislave {
 921                         compatible = "sprd,adislave";
 922                         reg = <0x40038000 0x1000>;
 923                 };
 924                 gpuapb {
 925                         compatible = "sprd,gpuapb";
 926                         reg = <0x60100000 0x1000>;
 927                 };
 928                 aonckg {
 929                         compatible = "sprd,aonckg";
 930                         reg = <0x402d0000 0x1000>;
 931                 };
 932                 apbckg {
 933                         compatible = "sprd,apbckg";
 934                         reg = <0x71200000 0x10000>;
 935                 };
 936                 gpuckg {
 937                         compatible = "sprd,gpuckg";
 938                         reg = <0x60200000 0x1000>;
 939                 };
 940                 core {
 941                         compatible = "sprd,core";
 942                         reg = <0x12000000 0x10000>;
 943                 };
 944                 int {
 945                         compatible = "sprd,int";
 946                         reg = <0x40200000 0x1000>;
 947                 };
 948                 intc0 {
 949                         compatible = "sprd,intc0";
 950                         reg = <0x71400000 0x1000>;
 951                 };
 952                 intc1 {
 953                         compatible = "sprd,intc1";
 954                         reg = <0x71500000 0x1000>;
 955                 };
 956                 intc2 {
 957                         compatible = "sprd,intc2";
 958                         reg = <0x71600000 0x1000>;
 959                 };
 960                 intc3 {
 961                         compatible = "sprd,intc3";
 962                         reg = <0x71700000 0x1000>;
 963                 };
 964                 uidefuse {
 965                         compatible = "sprd,uidefuse";
 966                         reg = <0x40240000 0x1000>;
 967                 };
 968                 isp {
 969                         compatible = "sprd,isp";
 970                         reg = <0x60a00000 0x8000>;
 971                 };
 972                 csi2 {
 973                         compatible = "sprd,csi2";
 974                         reg = <0x60c00000 0x1000>;
 975                 };
 976                 ipi {
 977                         compatible = "sprd,ipi";
 978                         reg = <0x402c0000 0x1000>;
 979                 };
 980                 dcam {
 981                         compatible = "sprd,dcam";
 982                         reg = <0x60800000 0x10000>;
 983                 };
 984                 syscnt {
 985                         compatible = "sprd,syscnt";
 986                         reg = <0x40230000 0x1000>;
 987                 };
 988                 dma0 {
 989                         compatible = "sprd,dma0";
 990                         reg = <0x20100000 0x4000>;
 991                 };
 992                 pub {
 993                         compatible = "sprd,pub";
 994                         reg = <0x30020000 0x10000>;
 995                 };
 996                 pin {
 997                         compatible = "sprd,pin";
 998                         reg = <0x402a0000 0x1000>;
 999                 };
1000                 axibm0 {
1001                         compatible  = "sprd,axibm0";
1002                         reg = <0 0x30040000 0 0x20000>;
1003                         interrupts = <0 86 0x0>;
1004                 };
1005         };
1006         sprd_bm {
1007                 compatible = "sprd,sprd_bm";
1008                 reg = <0x30040000 0xA0000>,
1009                                 <0x20E00000 0x300000>;
1010                 interrupts = <0 86 0x0>;
1011                 sprd,bm_status = <1>;
1012                 sprd,bm_count = <10 10>;
1013                 sprd,mm_chn = <0 1>;
1014                 sprd,gpu_chn = <1 1>;
1015                 sprd,disp_chn = <2 1>;
1016                 sprd,cpu_chn = <3 1>;
1017                 sprd,cp0_dsp_chn = <4 1>;
1018                 sprd,cp0_arm1_chn = <5 1>;
1019                 sprd,cp0_arm0_chn = <6 1>;
1020                 sprd,ap_chn = <7 1>;
1021                 sprd,zip_chn = <8 1>;
1022                 sprd,cp2_chn = <9 1>;
1023                 sprd,ap_cpu_chn = <0 0>;
1024                 sprd,ap_dap_chn = <0 1>;
1025                 sprd,ap_dma_w_chn = <1 0>;
1026                 sprd,ap_dma_r_chn = <1 1>;
1027                 sprd,ap_sdio_0_chn = <1 2>;
1028                 sprd,ap_sdio_1_chn = <1 3>;
1029                 sprd,ap_emmc_chn = <2 0>;
1030                 sprd,ap_sdio_2_chn = <2 1>;
1031                 sprd,ap_nfc_chn = <2 2>;
1032                 sprd,ap_usb_chn = <2 3>;
1033         };
1034         wdt@40290000 {
1035                 compatible = "sprd,sprd-wdt";
1036                 reg = <0x40290000 0x1000>,
1037                         <0x40320000 0x1000>;
1038                 interrupts = <0 124 0x0>;
1039         };
1040 };
1041
1042 &vbc_r2p0 {
1043         status = "okay";
1044 };
1045
1046 &sprd_codec_v3 {
1047         status = "okay";
1048         sprd,audio_power_ver = <3>;
1049 };
1050
1051 &i2s0 {
1052         sprd,config_type = "pcm";
1053         sprd,slave_timeout = <0xF11>;
1054         sprd,_hw_port = <0>;
1055         sprd,fs = <8000>;
1056         sprd,bus_type = <1>;
1057         sprd,rtx_mode = <3>;
1058         sprd,byte_per_chan = <1>;
1059         sprd,slave_mode = <0>;
1060         sprd,lsb = <1>;
1061         sprd,lrck = <1>;
1062         sprd,low_for_left = <1>;
1063         sprd,clk_inv = <0>;
1064         sprd,pcm_short_frame = <1>;
1065         sprd,pcm_slot = <0x1>;
1066         sprd,pcm_cycle = <1>;
1067         sprd,tx_watermark = <12>;
1068         sprd,rx_watermark = <20>;
1069         status = "okay";
1070 };
1071
1072 &i2s1 {
1073         status = "okay";
1074 };
1075
1076 &i2s2 {
1077         status = "okay";
1078 };
1079
1080 &i2s3 {
1081         status = "okay";
1082 };
1083
1084 &i2s_sound {
1085         sprd,i2s = <&i2s0>, <&i2s1>, <&i2s2>, <&i2s3>;
1086 };
1087 &sprd_battery {
1088         cap-valid-range-poweron = <50>;
1089         chg-end-vol-l = <4150>;
1090 };