arch/arm/boot/dts/sprd-scx35_sc7727s.dtsi

   1 /*
   2  * Copyright (C) 2013 Spreadtrum Communication Incorporated
   3  *              http://www.spreadtrum.com/
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 / {
  11         cpus {
  12                 #address-cells = <1>;
  13                 #size-cells = <0>;
  14
  15                 cpu@f00 {
  16                         device_type = "cpu";
  17                         compatible = "arm,cortex-a7";
  18                         reg = <0xf00>;
  19                 };
  20
  21                 cpu@f01 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a7";
  24                         reg = <0xf01>;
  25                 };
  26         };
  27
  28         fb0: fb@20800000 {
  29                 compatible = "sprd,sprdfb";
  30                 reg = <0xf5122000 0x1000>,<0xf5146000 0x1000>;
  31                 interrupts = <0 46 0x0>,<0 48 0x0>, <0 49 0x0>;
  32                 clock-names = "dispc_clk_parent", "dispc_dbi_clk_parent", "dispc_dpi_clk_parent", "dispc_emc_clk_parent", "dispc_clk", "dispc_dbi_clk", "dispc_dpi_clk", "dispc_emc_clk", "fb_spi_clock", "fb_spi_clock_parent";
  33                 clocks = <&clk_256m>, <&clk_256m>, <&clk_384m>, <&clk_aon_apb>, <&clk_dispc0>, <&clk_dispc0_dbi>, <&clk_dispc0_dpi>, <&clk_disp_emc>, <&clk_spi2>, <&ext_26m>;
  34                 clock-src = <256000000 256000000 384000000>;
  35                 dpi_clk_div = <7>;
  36                 sprd,fb_use_reservemem;
  37                 sprd,fb_mem = <0x9F73E000 0x1c2000>;
  38         };
  39
  40         sprd_sensor {
  41                 compatible  = "sprd,sprd_sensor";
  42                 gpios = <&d_gpio_gpio 186 0   /*reset*/
  43                         &d_gpio_gpio 188 0    /*main*/
  44                         &d_gpio_gpio 187 0>;  /*sub */
  45                 clock-names ="clk_mm_i","clk_sensor","clk_ccir","clk_dcam","clk_dcam_mipi";
  46                 clocks = <&clk_mm>, <&clk_sensor>,<&clk_ccir>, <&clk_dcam>, <&clk_dcam_mipi>;
  47         };
  48
  49         sdhci0: sdhci@f5117000 {
  50                 compatible  = "sprd,sdhci-shark";
  51                 interrupts = <0 57 0x0>;
  52                 reg = <0xf5117000 0x1000>;
  53                 id = <0>;
  54                 bus-width = <4>;
  55                 max-frequency = <384000000>;
  56                 keep-power-in-suspend = <1>;
  57                 caps = <0x80000000>;
  58                 caps2 = <0x202>;
  59                 host-caps-mask = <0x05000000>;
  60                 vdd-vqmmc = "vddsdcore";
  61                 sd-supply = <&vddsdio>;
  62                 vdd-level = <0 0 1800000 3000000>;
  63                 pinmap-offset = <0x0184>;
  64                 d3-gpio = <100>;
  65                 d3-index = <0>;
  66                 sd-func = <0>;
  67                 gpio-func = <3>;
  68                 clock-names = "clk_sdio0";
  69                 clocks = <&clk_sdio0>, <&clk_384m>;
  70                 enb-bit = <0x100>;
  71                 rst-bit = <0x800>;
  72                 keep-power = <0>;
  73                 runtime = <1>;
  74         };
  75
  76         gpu {
  77                 compatible  = "sprd,mali-utgard";
  78                 mali_pp_core_number = <1>;
  79                 interrupt-names = "mali_gp_irq",
  80                                 "mali_gp_mmu_irq",
  81                                 "mali_pp0_irq",
  82                                 "mali_pp0_mmu_irq";
  83                 reg-names = "mali_l2",
  84                                 "mali_gp",
  85                                 "mali_gp_mmu",
  86                                 "mali_pp0",
  87                                 "mali_pp0_mmu",
  88                                 "mali_pmu";
  89                 interrupts =  <0 39 0x0>,  //  MALI_GP_IRQ,
  90                                         <0 39 0x0>,  //  MALI_GP_MMU_IRQ,
  91                                         <0 39 0x0>,  //  MALI_PP0_IRQ,
  92                                         <0 39 0x0>;  //  MALI_PP0_MMU_IRQ,
  93                 reg = <0x60001000 0x200>,//  MALI_L2,MALI_GPU_RESOURCE_L2(base_addr + 0x1000)
  94                         <0x60000000 0x100>,//  MALI_GP,
  95                         <0x60003000 0x100>,//  MALI_GP_MMU,
  96                         <0x60008000 0x1100>,//  MALI_PP0,
  97                         <0x60004000 0x100>,//  MALI_PP0_MMU,
  98                         <0x60002000 0x100>;//  MALI_PMU,
  99                 clock-names = "clk_gpu_axi","clk_gpu","clk_153m6","clk_208m","clk_256m","clk_312m","clk_384m","clk_460m8";
 100                 clocks = <&clk_gpu_axi>,<&clk_gpu>,<&clk_153m6>,<&clk_208m>,<&clk_256m>,<&clk_312m>,<&clk_384m>,<&clk_460m8>;
 101         };
 102
 103         ion {
 104                 compatible = "sprd,ion-sprd";
 105                 #address-cells = <1>;
 106                 #size-cells = <0>;
 107
 108                 sprd,ion-heap@1 {
 109                         reg = <1>;                      /* SYSTEM */
 110                         reg-names = "ion_heap_system";
 111                         sprd,ion-heap-type = <0>;       /* SYSTEM */
 112                         sprd,ion-heap-mem = <0x0 0x0>;
 113                 };
 114
 115                 sprd,ion-heap@2 {
 116                         reg = <2>;                      /* MM */
 117                         reg-names = "ion_heap_carveout_mm";
 118                         sprd,ion-heap-type = <0>;       /* carveout mm */
 119                         sprd,ion-heap-mem = <0x0 0x0>;
 120                 };
 121
 122                 sprd,ion-heap@3 {
 123                         reg = <3>;                      /* OVERLAY */
 124                         reg-names = "ion_heap_carveout_overlay";
 125                         sprd,ion-heap-type = <2>;       /* CARVEOUT */
 126                         sprd,ion-heap-mem = <0x9f900000 0x700000>;      /* 7M */
 127                 };
 128         };
 129
 130         /* sipc initializer */
 131         sipc: sipc-common {
 132                 compatible = "sprd,sipc";
 133                 reg = <0x87800000 0x240000>; /* <SMEM SIZE>*/
 134                 //#interrupt-cells = <2>;
 135                 #address-cells = <1>;
 136                 #size-cells = <1>;
 137                 ranges = <0x8000000 0x88000000 0x1b00000>,
 138                                 <0x07800000 0x87800000 0x180000>,
 139                                 <0x9aff000 0x89aff000 0x1000>;
 140                 sipc_cpw@0x8000000 {
 141                         sprd,name = "sipc-w";
 142                         sprd,dst = <2>;
 143                         sprd,ap2cp = <0xf5240000>; /* base on ipi reggister */
 144                         sprd,cp2ap = <0xf5240004>;
 145                         sprd,trig = <0x01>; /* trigger bit */
 146                         sprd,clr = <0x01>; /* clear bit */
 147                         interrupts = <0 68 0x0>;
 148                         reg = <0x8000000 0x1b00000> , /* <CP_start_addr size> */
 149                                 <0x07800000 0x180000>, /* <SMEM_phy_addr total_size> */
 150                                 <0x9aff000 0x1000>; /* smsg ring buffer <base size> */
 151                 };
 152         };
 153
 154         /* cpw virtual devices */
 155
 156         scproc_cpw: scproc@0x88000000 {
 157                 compatible = "sprd,scproc";
 158                 sprd,name = "cpw";
 159                 sprd,ctrl-reg = <0x44 0x44 0xb0 0xbc>; /* <shut_down deep_sleep reset get_status> */
 160                 sprd,ctrl-mask = <0x02000000 0x10000000 0x01 0xf0000>; /* masks <> */
 161                 sprd,iram-data = <0xe59f0000 0xe12fff10 0x88300000>; /* 3rd param equals modem_addr*/
 162                 reg = <0x88000000 0x1b00000>, /* <CP_start_addr total_size> = <+128M 27M> */
 163                         <0xf53d4000 0x0c>, /* <iram1_base size> */
 164                         <0xf5230000 0x10000>; /* <pmu_base size> */
 165                 interrupts = <0 84 0x0>; /* cp1_wdg_int */
 166                 #address-cells = <1>;
 167                 #size-cells = <1>;
 168                 /* segnr=2 */
 169                 ranges = <0x300000 0x88300000 0x00800000>,
 170                                 <0x20000 0x88020000 0x00220000>;
 171                 modem@0x300000 {
 172                         cproc,name = "modem";
 173                         reg = <0x300000 0x00800000>; /* <modem_addr size> */
 174                 };
 175                 dsp@0x20000 {
 176                         cproc,name = "dsp";
 177                         reg = <0x20000 0x00220000>; /* <dsp_addr size>*/
 178                 };
 179         };
 180
 181
 182 };
 183