arch/arm/boot/dts/sprd-scx20_sp7720ea.dts

   1 /*
   2 * Copyright (C) 2013 Spreadtrum Communication Incorporated
   3 *               http://www.spreadtrum.com/
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License version 2 as
   7 * published by the Free Software Foundation.
   8 */
   9 /dts-v1/;
  10
  11 /* memory reserved for SMEM */
  12 /memreserve/ 0x87800000 0x200000; /* 2M */
  13
  14 /* memory reserved for CPW modem */
  15 /memreserve/ 0x88000000 0x1b00000; /* 27M */
  16
  17 /* memory reserved for CPWCN modem */
  18 /memreserve/ 0x8a800000 0x201000;/*Offset:168M, SIZE:2M+4k*/
  19
  20 /* memory reserved for fb */
  21 /memreserve/ 0x9F82D000 0x4B1000; /* 480*854*4*3, 4K alignment*/
  22
  23 /* memory reserved for ION */
  24 /memreserve/ 0x9FCDE000 0x322000; /* 480*854*4*2, 1M alignment*/
  25
  26 /include/ "skeleton.dtsi"
  27 /include/ "scx20-clocks.dtsi"
  28 /include/ "sc2723-regulators.dtsi"
  29 /include/ "sprd-sound.dtsi"
  30 /include/ "sprd-battery.dtsi"
  31
  32 / {
  33         model = "Spreadtrum SP8835EB board";
  34         compatible = "sprd,sp8835eb";
  35         sprd,sc-id = <8830 1 0x20000>;
  36         #address-cells = <1>;
  37         #size-cells = <1>;
  38         interrupt-parent = <&gic>;
  39
  40         chosen {
  41                 bootargs = "loglevel=1 console=ttyS1,115200n8 init=/init root=/dev/ram0 rw";
  42                 linux,initrd-start = <0x85500000>;
  43                 linux,initrd-end   = <0x855a3212>;
  44         };
  45
  46         memory {
  47                 device_type = "memory";
  48                 reg = <0x80000000 0x40000000>;
  49         };
  50
  51         aliases {
  52                 serial0 = &uart0;
  53                 serial1 = &uart1;
  54                 serial2 = &uart2;
  55                 i2c0 = &i2c0;
  56                 i2c1 = &i2c1;
  57                 i2c2 = &i2c2;
  58                 i2c3 = &i2c3;
  59                 lcd0 = &fb0;
  60                 spi0 = &spi0;
  61                 spi1 = &spi1;
  62                 spi2 = &spi2;
  63                 hwspinlock0 = &hwspinlock0;
  64                 hwspinlock1 = &hwspinlock1;
  65         };
  66
  67         cpus {
  68                 #address-cells = <1>;
  69                 #size-cells = <0>;
  70
  71                 cpu@f00 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a7";
  74                         reg = <0xf00>;
  75                 };
  76
  77                 cpu@f01 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a7";
  80                         reg = <0xf01>;
  81                 };
  82
  83                 cpu@f02 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a7";
  86                         reg = <0xf02>;
  87                 };
  88
  89                 cpu@f03 {
  90                         device_type = "cpu";
  91                         compatible = "arm,cortex-a7";
  92                         reg = <0xf03>;
  93                 };
  94         };
  95         pmu {
  96                 compatible = "arm,cortex-a7-pmu";
  97                 interrupts = <0 92 0x0>,
  98                                 <0 93 0x0>,
  99                                 <0 94 0x0>,
 100                                 <0 95 0x0>;
 101         };
 102
 103     gic: interrupt-controller@12001000 {
 104         compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
 105         #interrupt-cells = <3>;
 106         #address-cells = <0>;
 107         interrupt-controller;
 108         reg = <0x12001000 0x1000>,
 109               <0x12002000 0x1000>;
 110     };
 111
 112         uart0: uart@70000000 {
 113                 compatible  = "sprd,serial";
 114                 interrupts = <0 2 0x0>;
 115                 reg = <0x70000000 0x1000>;
 116                 clock-names = "clk_uart0";
 117                 clocks = <&clock 60>;
 118                 sprdclk = <48000000>;
 119                 sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP";
 120         };
 121         uart1: uart@70100000 {
 122                 compatible  = "sprd,serial";
 123                 interrupts = <0 3 0x0>;
 124                 reg = <0x70100000 0x1000>;
 125                 clock-names = "clk_uart1";
 126                 clocks = <&clock 61>;
 127                 sprdclk = <26000000>;
 128                 sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP";
 129         };
 130         uart2: uart@70200000 {
 131                 compatible  = "sprd,serial";
 132                 interrupts = <0 4 0x0>;
 133                 reg = <0x70200000 0x1000>;
 134                 clock-names = "clk_uart2";
 135                 clocks = <&clock 62>;
 136                 sprdclk = <26000000>;
 137                 sprdwaketype = "BT_RTS_HIGH_WHEN_SLEEP";
 138         };
 139
 140         timer {
 141                 compatible  = "sprd,scx35-timer";
 142                 reg =   <0x40230000 0x1000>, /* SYSCNT */
 143                         <0x40050000 0x1000>, /* GPTIMER0 */
 144                         <0x40220000 0x1000>, /* APTIMER0 */
 145                         <0x40330000 0x1000>, /* APTIMER1 */
 146                         <0x40340000 0x1000>; /* APTIMER2 */
 147                 interrupts = <0 118 0x0>,
 148                                 <0 28 0x0>,
 149                                 <0 29 0x0>,
 150                                 <0 119 0x0>,
 151                                 <0 121 0x0>,
 152                                 <0 31 0x0>;/*ap system timer*/
 153         };
 154         clock: clockdevice {
 155                 compatible = "sprd,scx35-clock";
 156                 #clock-cells = <1>;
 157         };
 158         d_eic_gpio: gpio@40210000{
 159                 compatible = "sprd,d-eic-gpio";
 160                 reg = <0x40210000 0x1000>;
 161                 gpio-controller;
 162                 interrupt-controller;
 163                 #interrupt-cells = <2>;
 164                 #gpio-cells = <2>;
 165                 gpiobase = <288>;
 166                 ngpios = <16>;
 167                 interrupts = <0 37 0x0>;
 168         };
 169         d_gpio_gpio: gpio@40280000{
 170                 compatible = "sprd,d-gpio-gpio";
 171                 reg = <0x40280000 0x1000>;
 172                 gpio-controller;
 173                 interrupt-controller;
 174                 #interrupt-cells = <2>;
 175                 #gpio-cells = <2>;
 176                 gpiobase = <0>;
 177                 ngpios = <256>;
 178                 interrupts = <0 35 0x0>;
 179         };
 180         pinctrl{
 181                 compatible = "sprd,pinctrl";
 182                 reg = <0x402a0000 0x1000>;
 183                 pwr_domain = "vddsdio",
 184                                          "vddsim0",
 185                                          "vddsim1",
 186                                          "vddsim2",
 187                                          "vdd28";
 188                 ctrl_desc = <0x10 16 1
 189                                     0x10 17 1
 190                                     0x10 18 1
 191                                     0x10 19 1
 192                                     0x10 20 1>;
 193         };
 194         adic:adic{
 195                 compatible = "sprd,adi";
 196                 reg = <0x40030000 0x10000>;
 197         };
 198          adi: adi_bus{
 199                  compatible = "sprd,adi-bus";
 200                  interrupts = <0 38 0x0>;
 201                  reg = <0x40038000 0x1000>;
 202                  interrupt-controller;
 203                  sprd,irqnums = <11>;
 204                  #interrupt-cells = <2>;
 205                  #address-cells = <1>;
 206                  #size-cells = <1>;
 207                  ranges = <0X40 0x40038040 0x40>,
 208                                   <0x80 0x40038080 0x80>,
 209                                   <0x100 0x40038100 0x80>,
 210                                   <0x480 0x40038480 0x80>;
 211                  sprd_backlight {
 212                         compatible = "sprd,sprd_backlight";
 213                         start = <3>;
 214                         end = <3>;
 215                         flags = <0x100>;
 216                  };
 217                 headset_sprd_sc2723 {
 218                         compatible = "sprd,headset_sprd_sc2723";
 219                         gpio_switch = <0>;
 220                         gpio_detect = <312>;
 221                         gpio_button = <307>;
 222                         irq_trigger_level_detect = <1>;
 223                         irq_trigger_level_button = <1>;
 224                         adc_threshold_3pole_detect = <2600>;
 225                         adc_threshold_4pole_detect = <2601>;
 226                         irq_threshold_buttont = <1>;
 227                         voltage_headmicbias = <3000000>;
 228                         nbuttons = <3>;
 229                         headset_buttons_media {
 230                                 adc_min = <0>;
 231                                 adc_max = <410>;
 232                                 code = <226>;
 233                                 type = <0>;
 234                         };
 235
 236                         headset_buttons_up {
 237                                 adc_min = <411>;
 238                                 adc_max = <840>;
 239                                 code = <115>;
 240                                 type = <0>;
 241                         };
 242                         headset_buttons_down {
 243                                 adc_min = <841>;
 244                                 adc_max =<1900>;
 245                                 code = <114>;
 246                                 type = <0>;
 247                         };
 248                 };
 249
 250                  keyboard_backlight {
 251                         compatible = "sprd,keyboard-backlight";
 252                  };
 253                  watchdog@40{
 254                         compatible = "sprd,watchdog";
 255                         reg = <0X40 0x40>;
 256                         interrupts = <3 0x0>;
 257                  };
 258                  rtc@80{
 259                         compatible = "sprd,rtc";
 260                         reg = <0X80 0x80>;
 261                         interrupts = <2 0x0>;
 262                 };
 263                  a_eic_gpio: gpio@100{
 264                          compatible = "sprd,a-eic-gpio";
 265                          reg = <0X100 0x80>; /* adi reg */
 266                          gpio-controller;
 267                          interrupt-controller;
 268                          #interrupt-cells = <2>;
 269                          #gpio-cells = <2>;
 270                          gpiobase = <304>;
 271                          ngpios = <16>;
 272                          interrupt-parent = <&adi>;
 273                          interrupts = <5 0x0>; /* ext irq 5 */
 274                  };
 275                  a_gpio_gpio: gpio@480{
 276                          compatible = "sprd,a-gpio-gpio";
 277                          reg = <0X480 0x80>; /* adi reg */
 278                          gpio-controller;
 279                          interrupt-controller;
 280                          #interrupt-cells = <2>;
 281                          #gpio-cells = <2>;
 282                          gpiobase = <256>;
 283                          ngpios = <32>;
 284                          interrupt-parent = <&adi>;
 285                          interrupts = <1 0x0>; /* ext irq 1 */
 286                  };
 287                 sprd_eic_keys {
 288                         compatible = "sprd,sprd-eic-keys";
 289
 290                         key_power {
 291                                 label = "Power Key";
 292                                 linux,code = <116>;
 293                                 gpios = <&a_eic_gpio 2 0>;
 294                                 debounce-interval = <2>;
 295                                 gpio-key,wakeup;
 296                         };
 297 /*
 298                         key_volumeup {
 299                                 label = "Volumeup Key";
 300                                 linux,code = <115>;
 301                                 gpios = <&a_eic_gpio 10 0>;
 302                                 debounce-interval = <2>;
 303                                 gpio-key,wakeup;
 304                         };
 305 */
 306                 };
 307
 308          };
 309         sprd_pwm_bl {
 310                 compatible = "sprd,sprd_pwm_bl";
 311                 reg = <0x40260000 0xf>;
 312                 brightness_max = <255>;
 313                 brightness_min = <0>;
 314                 pwm_index = <0>;
 315                 gpio_ctrl_pin = <0>;
 316                 gpio_active_level = <0>;
 317         };
 318
 319         gpio_keys {
 320                 compatible = "gpio-keys";
 321                 input-name = "sprd-gpio-keys";
 322                 key_volumedown {
 323                         label = "Volumedown Key";
 324                         linux,code = <114>;
 325                         gpios = <&d_gpio_gpio 199 1>;
 326                         debounce-interval = <2>;
 327                         gpio-key,wakeup;
 328                 };
 329                 key_volumeup {
 330                         label = "Volumeup Key";
 331                         linux,code = <115>;
 332                         gpios = <&d_gpio_gpio 200 1>;
 333                         debounce-interval = <2>;
 334                         gpio-key,wakeup;
 335                 };
 336         };
 337
 338          keypad@40250000{
 339                  compatible = "sprd,sci-keypad";
 340                  reg = <0x40250000 0x1000>;
 341                  gpios = <&a_eic_gpio 2 0>;
 342                  interrupts = <0 36 0x0>;
 343                  sprd,keypad-num-rows = <2>;
 344                  sprd,keypad-num-columns = <2>;
 345                  sprd,keypad-rows-choose-hw = <0x30000>;
 346                  sprd,keypad-cols-choose-hw = <0x300>;
 347                  sprd,debounce_time = <5000>;
 348                  linux,keypad-no-autorepeat;
 349                  sprd,support_long_key;
 350
 351                  key_volume_down {
 352                          keypad,row = <0>;
 353                          keypad,column = <0>;
 354                          linux,code = <114>;
 355                  };
 356 /*
 357                  key_volume_up {
 358                          keypad,row = <1>;
 359                          keypad,column = <0>;
 360                          linux,code = <115>;
 361                  };
 362 */
 363                  key_home {
 364                          keypad,row = <0>;
 365                          keypad,column = <1>;
 366                          linux,code = <102>;
 367                  };
 368          };
 369          sprd_vsp@60900000{
 370                  compatible = "sprd,sprd_vsp";
 371                  reg = <0x60900000 0xc000>;
 372                  interrupts = <0 43 0x0>;
 373                  clock-names = "clk_mm_i", "clk_vsp", "clk_parent_0", "clk_parent_1", "clk_parent_2";
 374                  clocks = <&clk_mm>, <&clk_vsp>, <&clk_192m>, <&clk_128m>, <&clk_76m8>;
 375                  clock-parent-info = <2 3>;
 376                  version = <4>;
 377          };
 378         sprd_jpg {
 379                  compatible = "sprd,sprd_jpg";
 380                  reg = <0x60b00000 0x8000>;
 381                  interrupts = <0 42 0x0>;
 382                  clock-names = "clk_mm_i","clk_jpg";
 383                  clocks = <&clk_mm>, <&clk_jpg>;
 384          };
 385
 386
 387          i2c0: i2c@70500000 {
 388                  compatible  = "sprd,i2c";
 389                  interrupts = <0 11 0x0>;
 390                  reg = <0x70500000 0x1000>;
 391                  #address-cells = <1>;
 392                  #size-cells = <0>;
 393                  sensor_main@0x3c{
 394                         compatible = "sprd,sensor_main";
 395                         reg = <0x3c>;
 396                  };
 397                  sensor_sub@0x21{
 398                         compatible = "sprd,sensor_sub";
 399                         reg = <0x21>;
 400                  };
 401          };
 402          i2c1: i2c@70600000 {
 403                  compatible  = "sprd,i2c";
 404                  interrupts = <0 12 0x0>;
 405                  reg = <0x70600000 0x1000>;
 406                  #address-cells = <1>;
 407                  #size-cells = <0>;
 408                  msg2138_ts@26{
 409                         compatible = "Mstar,msg2138_ts";
 410                         reg = <0x26>;
 411                         gpios = <&d_gpio_gpio 71 0
 412                                  &d_gpio_gpio 72 0>;
 413                         vdd_name = "vdd28";
 414                         virtualkeys = <256 1068 64 64
 415                                 128 1068 64 64
 416                                 192 1068 64 64>;
 417                         TP_MAX_X = <480>;
 418                         TP_MAX_Y = <800>;
 419                  };
 420          };
 421          i2c2: i2c@70700000{
 422                  compatible  = "sprd,i2c";
 423                  interrupts = <0 13 0x0>;
 424                  reg = <0x70700000 0x1000>;
 425                  #address-cells = <1>;
 426                  #size-cells = <0>;
 427                 lis3dh_acc@18{
 428                         compatible = "ST,lis3dh_acc";
 429                         reg = <0x18>;
 430                         poll_interval = <10>;
 431                         min_interval = <10>;
 432                         g_range = <0>;
 433                         axis_map_x = <0>;
 434                         axis_map_y = <1>;
 435                         axis_map_z = <2>;
 436                         negate_x = <1>;
 437                         negate_y = <1>;
 438                         negate_z = <0>;
 439                 };
 440                 ltr_558als@23{
 441                         compatible = "LITEON,ltr_558als";
 442                         reg = <0x23>;
 443                         gpios = <&d_gpio_gpio 239 0>;
 444                 };
 445                 epl2182_pls@49{
 446                         compatible = "ELAN,epl2182_pls";
 447                         reg = <0x49>;
 448                         gpios = <&d_gpio_gpio 239 0>;
 449                 };
 450          };
 451          i2c3: i2c@70800000{
 452                  compatible  = "sprd,i2c";
 453                  interrupts = <0 14 0x0>;
 454                  reg = <0x70800000 0x1000>;
 455                  #address-cells = <1>;
 456                  #size-cells = <0>;
 457          };
 458          sprd_dcam{
 459                  compatible  = "sprd,sprd_dcam";
 460                  interrupts = <0 45 0>;
 461                  reg = <0x60800000 0x100000>;
 462                  clock-names = "clk_mm_i","clk_dcam";
 463                  clocks = <&clk_mm>, <&clk_dcam>;
 464          };
 465          sprd_scale {
 466                  compatible  = "sprd,sprd_scale";
 467          };
 468          sprd_rotation {
 469                  compatible  = "sprd,sprd_rotation";
 470          };
 471          sprd_sensor {
 472                  compatible  = "sprd,sprd_sensor";
 473                  reg = <0x60c00000 0x1000>;
 474                  gpios = <&d_gpio_gpio 186 0   /*main reset*/
 475                         &d_gpio_gpio 187 0     /*main power down*/
 476                         &d_gpio_gpio 186 0     /*sub reset*/
 477                         &d_gpio_gpio 188 0     /*sub power down*/
 478                         &d_gpio_gpio 0 0       /*main core voltage*/
 479                         &d_gpio_gpio 0 0
 480                         &d_gpio_gpio 0 0
 481                         &d_gpio_gpio 0 0>;
 482                  clock-names ="clk_mm_i","clk_sensor","clk_ccir","clk_dcam","clk_dcam_mipi";
 483                  clocks = <&clk_mm>, <&clk_sensor>,<&clk_ccir>, <&clk_dcam>, <&clk_dcam_mipi>;
 484                  };
 485         sprd_isp {
 486                 compatible  = "sprd,sprd_isp";
 487                 reg = <0x60a00000 0x100000>;
 488                 clock-names = "clk_mm_i","clk_isp";
 489                 clocks = <&clk_mm>, <&clk_isp>;
 490         };
 491         sprd_dma_copy {
 492                 compatible  = "sprd,sprd_dma_copy";
 493         };
 494         fb0: fb@20800000 {
 495                 compatible = "sprd,sprdfb";
 496                 reg = <0x20800000 0x1000>,<0x21800000 0x1000>;
 497                 interrupts = <0 46 0x0>,<0 48 0x0>, <0 49 0x0>, <0 47 0x0>;
 498                 clock-names = "dispc_clk_parent", "dispc_dbi_clk_parent", "dispc_dpi_clk_parent", "dispc_emc_clk_parent", "dispc_clk", "dispc_dbi_clk", "dispc_dpi_clk", "dispc_emc_clk", "fb_spi_clock", "fb_spi_clock_parent";
 499                 clocks = <&clk_256m>, <&clk_256m>, <&clk_384m>, <&clk_aon_apb>, <&clk_dispc0>, <&clk_dispc0_dbi>, <&clk_dispc0_dpi>, <&clk_disp_emc>, <&clk_spi2>, <&ext_26m>;
 500                 clock-src = <256000000 256000000 384000000>;
 501                 dpi_clk_div = <7>;
 502                 sprd,fb_use_reservemem;
 503                 sprd,fb_mem = <0x9F82D000 0x4B1000>;
 504         };
 505         gsp:gsp@20a00000 {
 506                 compatible = "sprd,gsp";
 507                 reg = <0x20a00000 0x1000>;
 508                 interrupts = <0 51 0x0>;
 509                 clock-names = "clk_gsp", "clk_gsp_emc", "clk_gsp_parent", "clk_aon_apb";
 510                 clocks = <&clk_gsp>, <&clk_gsp_emc>, <&clk_256m>, <&clk_aon_apb>;
 511                 gsp_mmu_ctrl_base = <0x21408000>;
 512         };
 513
 514         sprd_fm: sprd_fm@40270000{
 515                 compatible  = "sprd,sprd_fm";
 516                 reg = <0x40270000 0x1000>,/*FM base*/
 517                         <0x402E0000 0x10000>, /*AONAPB base*/
 518                         <0x402B0000 0x10000>, /*PMU base*/
 519                         <0x402D000 0x1000>,  /*AONCKG base*/
 520                         <0x402A000 0x1000> ; /*PIN base*/
 521         };
 522
 523         /* sipc initializer */
 524         sipc: sipc@0x87800000 {
 525                 compatible = "sprd,sipc";
 526                 reg = <0x87800000 0x200000>; /* <SMEM SIZE>*/
 527                 //#interrupt-cells = <2>;
 528                 #address-cells = <1>;
 529                 #size-cells = <1>;
 530                 ranges = <0x8000000 0x88000000 0x1b00000>,
 531                                 <0x07800000 0x87800000 0x140000>,
 532                                 <0x9aff000 0x89aff000 0x1000>,
 533                                 <0x0a800000 0x8a800000 0x201000>,/*WCN MEMORY:OFFSET ADDRESS SIZE*/
 534                                 <0x07940000 0x87940000 0xc0000>,
 535                                 <0x0aa00000 0x8aa00000 0x1000>;/*WCN SIPC-RING:OFFSET ADDRESS SIZE*/
 536                 sipc_cpw@0x8000000 {
 537                         sprd,name = "sipc-w";
 538                         sprd,dst = <2>;
 539                         sprd,ap2cp = <0x402c0000>; /* base on ipi reggister */
 540                         sprd,cp2ap = <0x402c0004>;
 541                         sprd,trig = <0x01>; /* trigger bit */
 542                         sprd,clr = <0x01>; /* clear bit */
 543                         interrupts = <0 68 0x0>;
 544                         reg = <0x8000000 0x1b00000> , /* <CP_start_addr size> */
 545                                 <0x07800000 0x140000>, /* <SMEM_phy_addr total_size> */
 546                                 <0x9aff000 0x1000>; /* smsg ring buffer <base size> */
 547                 };
 548                 sipc_wcn@0x0a800000 {
 549                         sprd,name = "sipc-wcn";
 550                         sprd,dst = <3>;
 551                         sprd,ap2cp = <0x402c0000>; /* base on ipi reggister */
 552                         sprd,cp2ap = <0x402c0004>;
 553                         sprd,trig = <0x100>; /* trigger bit */
 554                         sprd,clr = <0x100>; /* clear bit */
 555                         interrupts = <0 73 0x0>;
 556                         reg = <0x0a800000 0x201000> , /* <CP_start_addr size> */
 557                                 <0x07940000 0xc0000>, /* <SMEM_phy_addr total_size> */
 558                                 <0x0aa00000 0x1000>; /* smsg ring buffer <base size> */
 559                 };
 560
 561         };
 562
 563
 564         /* cpw virtual devices */
 565
 566         spipe-cpw {
 567                 compatible = "sprd,spipe";
 568                 sprd,name = "spipe_w";
 569                 sprd,dst = <2>;
 570                 sprd,channel = <4>;
 571                 sprd,ringnr = <9>;
 572                 sprd,size-rxbuf = <0x1000>; /* 4*1024 */
 573                 sprd,size-txbuf = <0x1000>; /* 4*1024 */
 574         };
 575
 576         slog-cpw {
 577                 compatible = "sprd,spipe";
 578                 sprd,name = "slog_w";
 579                 sprd,dst = <2>;
 580                 sprd,channel = <5>;
 581                 sprd,ringnr = <1>;
 582                 sprd,size-rxbuf = <0x40000>; /* 256*1024*/
 583                 sprd,size-txbuf = <0x8000>; /* 32*1024 */
 584         };
 585
 586         stty-cpw {
 587                 compatible = "sprd,spipe";
 588                 sprd,name = "stty_w";
 589                 sprd,dst = <2>;
 590                 sprd,channel = <6>;
 591                 sprd,ringnr = <32>;
 592                 sprd,size-rxbuf = <0x0800>; /* 2*1024*/
 593                 sprd,size-txbuf = <0x0800>; /* 2*1024 */
 594         };
 595
 596         seth0-cpw {
 597                 compatible = "sprd,seth";
 598                 sprd,name = "seth_w0";
 599                 sprd,dst = <2>;
 600                 sprd,channel = <7>;
 601                 sprd,blknum = <64>;
 602         };
 603
 604         seth1-cpw {
 605                 compatible = "sprd,seth";
 606                 sprd,name = "seth_w1";
 607                 sprd,dst = <2>;
 608                 sprd,channel = <8>;
 609                 sprd,blknum = <64>;
 610         };
 611
 612         seth2-cpw {
 613                 compatible = "sprd,seth";
 614                 sprd,name = "seth_w2";
 615                 sprd,dst = <2>;
 616                 sprd,channel = <9>;
 617                 sprd,blknum = <64>;
 618         };
 619
 620         scproc_cpw: scproc@0x88000000 {
 621                 compatible = "sprd,scproc";
 622                 sprd,name = "cpw";
 623                 sprd,ctrl-reg = <0x44 0x44 0xb0 0xff>; /* <shut_down deep_sleep reset get_status> */
 624                 sprd,ctrl-mask = <0x02000000 0x10000000 0x01 0xf0000>; /* masks <> */
 625                 sprd,iram-data = <0xe59f0000 0xe12fff10 0x88300000>; /* 3rd param equals modem_addr*/
 626                 reg = <0x88000000 0x1b00000>, /* <CP_start_addr total_size> = <+128M 26M> */
 627                         <0x50000000 0x0c>, /* <iram1_base size> */
 628                         <0x402b0000 0x10000>, /* <pmu_base size> */
 629                         <0x402b0000 0x10000>, /* <pmu_base size> */
 630                         <0x402b0000 0x10000>, /* <pmu_base size> */
 631                         <0x402b0000 0x10000>; /* <pmu_base size> */
 632                 interrupts = <0 83 0x0>; /* cp1_wdg_int */
 633                 #address-cells = <1>;
 634                 #size-cells = <1>;
 635                 /* segnr=2 */
 636                 ranges = <0x300000 0x88300000 0x00800000>,
 637                                 <0x20000 0x88020000 0x00220000>;
 638                 modem@0x300000 {
 639                         cproc,name = "modem";
 640                         reg = <0x300000 0x00800000>; /* <modem_addr size> */
 641                 };
 642                 dsp@0x20000 {
 643                         cproc,name = "dsp";
 644                         reg = <0x20000 0x00220000>; /* <dsp_addr size>*/
 645                 };
 646         };
 647
 648         saudio_w{
 649                 compatible = "sprd,saudio";
 650                 sprd,saudio-dst-id = <2>;
 651                 sprd,ctrl_channel = <10>;       /* SMSG_CH_VBC */
 652                 sprd,playback_channel = <11>;   /* SMSG_CH_PLAYBACK */
 653                 sprd,capture_channel = <12>;    /* SMSG_CH_CAPTURE */
 654                 sprd,monitor_channel = <13>;    /*SMSG_CH_MONITOR_AUDIO */
 655                 sprd,saudio-names = "VIRTUAL AUDIO W";
 656         };
 657         saudio_voip{
 658                 compatible = "sprd,saudio";
 659                 sprd,saudio-dst-id = <2>;
 660                 sprd,ctrl_channel = <14>;       /* SMSG_CH_CTRL_VOIP */
 661                 sprd,playback_channel = <15>;   /* SMSG_CH_PLAYBACK_VOIP */
 662                 sprd,capture_channel = <16>;    /* SMSG_CH_CAPTURE_VOIP */
 663                 sprd,monitor_channel = <17>;    /*SMSG_CH_MONITOR_VOIP */
 664                 sprd,saudio-names = "saudiovoip";
 665         };
 666
 667         /* cpwcn virtual devices */
 668
 669         spipe_cpwcn {
 670                 compatible = "sprd,spipe";
 671                 sprd,name = "spipe_wcn";
 672                 sprd,dst = <3>;
 673                 sprd,channel = <4>;
 674                 sprd,ringnr = <12>;
 675                 sprd,size-rxbuf = <0x1000>; /* 4*1024 */
 676                 sprd,size-txbuf = <0x1000>; /* 4*1024 */
 677         };
 678
 679         slog_cpwcn {
 680                 compatible = "sprd,spipe";
 681                 sprd,name = "slog_wcn";
 682                 sprd,dst = <3>;
 683                 sprd,channel = <5>;
 684                 sprd,ringnr = <1>;
 685                 sprd,size-rxbuf = <0x40000>; /* 256*1024*/
 686                 sprd,size-txbuf = <0x8000>; /* 32*1024 */
 687         };
 688
 689         stty4bt_cpwcn {
 690                 compatible = "sprd,stty4bt";
 691                 sprd,name = "sttybt";
 692                 sprd,dst = <3>;
 693                 sprd,channel = <4>;
 694                 sprd,bufid = <10>;
 695         };
 696
 697
 698         scproc_cpwcn: scproc@0x8a800000 {
 699                 compatible = "sprd,scproc";
 700                 sprd,name = "cpwcn";
 701                 sprd,ctrl-reg = <0x68 0x68 0xb0 0xb0>; /* <shut_down deep_sleep reset get_status> */
 702                 sprd,ctrl-mask = <0x02000000 0x10000000 0x04 0x04>; /* masks <> */
 703                 sprd,iram-data = <0xe59f0000 0xe12fff10 0x8a808000>; /* 3rd param equals modem_addr*/
 704                 reg = <0x8a800000 0x201000>, /* <CP_start_addr total_size> = <+168M 2M+4k> */
 705                         <0x50003000 0x1000>, /* <iram1_phys size> use iram1 phys because of cp2 iram not maped */
 706                         <0x402b0000 0x10000>, /* <pmu_base size> */
 707                         <0x402b0000 0x10000>, /* <pmu_base size> */
 708                         <0x402b0000 0x10000>, /* <pmu_base size> */
 709                         <0x402b0000 0x10000>; /* <pmu_base size> */
 710                 interrupts = <0 85 0x0>; /* cp2_wdg_int */
 711                 #address-cells = <1>;
 712                 #size-cells = <1>;
 713                 /* segnr=1 */
 714                 ranges = <0x8000 0x8a808000 0x201000>;
 715                 modem@0x8000 {
 716                         cproc,name = "modem";
 717                         reg = <0x8000 0x201000>; /* <modem_addr size> */
 718                 };
 719         };
 720
 721         sprd_wlan{
 722                 compatible = "sprd,sprd_wlan";
 723         };
 724
 725         sdios{
 726                 #address-cells = <2>;
 727                 #size-cells = <2>;
 728                 ranges;
 729                 sdio3: sdio@20600000{
 730                         compatible  = "sprd,sdhost-3.0";
 731                         reg = <0 0x20600000 0 0x1000>;
 732                         interrupts = <0 60 0x0>;
 733                         sprd,name = "sdio_emmc";
 734                         /* detect_gpio = <-1>; */
 735                         SD_Pwr_Name = "vddemmccore";
 736                         _1_8V_signal_Name = "vddgen0";
 737                         signal_default_Voltage = <1800000>;
 738                         ocr_avail = <0x00040000>;
 739                         clocks = <&clk_emmc>, <&clk_192m>;
 740                         base_clk = <192000000>;
 741                         caps = <0xC00F8D47>;
 742                         caps2 = <0x202>;
 743                         pm_caps = <0x4>;
 744                         writeDelay = <0x1B>;
 745                         readPosDelay = <0xC>;
 746                         readNegDelay = <0xC>;
 747                 };
 748
 749                 sdio0: sdio@20300000{
 750                         compatible  = "sprd,sdhost-3.0";
 751                         reg = <0 0x20300000 0 0x1000>;
 752                         interrupts = <0 57 0x0>;
 753                         sprd,name = "sdio_sd";
 754                         detect_gpio = <237>;
 755                         SD_Pwr_Name = "vddsdcore";
 756                         _1_8V_signal_Name = "vddsdio";
 757                         signal_default_Voltage = <3000000>;
 758                         ocr_avail = <0x00040000>;
 759                         clocks = <&clk_sdio0>, <&clk_192m>;
 760                         base_clk = <192000000>;
 761                         caps = <0x40038407>;
 762                         caps2 = <0x200>;
 763                         pm_caps = <0x4>;
 764                         writeDelay = <0x3>;
 765                         readPosDelay = <0x3>;
 766                         readNegDelay = <0x3>;
 767                 };
 768         };
 769
 770          usb: usb@20200000{
 771                  compatible  = "sprd,usb";
 772                  interrupts = <0 55 0x0>;
 773                 ngpios = <2>;
 774                 gpios = <&a_eic_gpio 0 0>,<&d_gpio_gpio 72 0>;
 775                  reg = <0x20200000 0x1000>;
 776                  tune_value = <0XD2200000>;
 777                  usb-supply = <&vddusb>;
 778                  #address-cells = <1>;
 779                  #size-cells = <0>;
 780          };
 781         sprd_thermal {
 782                 compatible = "sprd,sprd-thermal";
 783                 id = <0>;
 784                 interrupts = <0 26 0x0>;
 785                 reg = <0x402f0000 0x1000>;
 786                 trip_points_active = <65 69 95 110>;
 787                 trip_points_lowoff = <0 57 61 80>;
 788                 trip_points_critical = <110>;
 789                 trip_num = <5>;
 790         };
 791         sprd_cpu_cooling{
 792                 compatible = "sprd,sprd-cpu-cooling";
 793                 id = <0>;
 794                 max_freq = <1200000 1200000 813000 813000>;
 795                 max_core = <4 4 4 1>;
 796                 state_num = <4>;
 797         };
 798
 799          spi0: spi@70a00000{
 800                  compatible  = "sprd,sprd-spi";
 801                  interrupts = <0 7 0x0>;
 802                  reg = <0x70a00000 0x1000>;
 803                  clock-names = "clk_spi0";
 804                  #address-cells = <1>;
 805                  #size-cells = <0>;
 806          };
 807          spi1: spi@70b00000{
 808                  compatible  = "sprd,sprd-spi";
 809                  interrupts = <0 8 0x0>;
 810                  reg = <0x70b00000 0x1000>;
 811                  clock-names = "clk_spi1";
 812                  #address-cells = <1>;
 813                  #size-cells = <0>;
 814          };
 815          spi2: spi@70c00000{
 816                  compatible  = "sprd,sprd-spi";
 817                  interrupts = <0 9 0x0>;
 818                  reg = <0x70c00000 0x1000>;
 819                  clock-names = "clk_spi2";
 820                  #address-cells = <1>;
 821                  #size-cells = <0>;
 822          };
 823          dmac: dmac@20100000{
 824                  compatible  = "sprd,sprd-dma";
 825                  interrupts = <0 50 0x0>;
 826                  reg = <0x20100000 0x4000>;
 827          };
 828          adc: adc@40038300{
 829                  compatible  = "sprd,sprd-adc";
 830                  reg = <0x40038300 0x400>;
 831          };
 832          hwspinlock0: hwspinlock0@20c00000{
 833                  compatible  = "sprd,sprd-hwspinlock";
 834                  reg = <0x20c00000 0x1000>;
 835          };
 836          hwspinlock1: hwspinlock1@40060000{
 837                  compatible  = "sprd,sprd-hwspinlock";
 838                  reg = <0x40060000 0x1000>;
 839          };
 840         gpu@60000000 {
 841                 compatible = "arm,mali-400", "arm,mali-utgard";
 842                 reg = <0x60000000 0x10000>;
 843                 interrupts = <0 39 0>, <0 39 0>, <0 39 0>, <0 39 0>, <0 39 0>;
 844                 interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPMU";
 845
 846                 pmu_domain_config = <0x1000 0x1000 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1000 0x0 0x0>;
 847                 pmu_switch_delay = <0xffff>;
 848
 849                 clocks = <&clk_gpu_axi>,<&clk_gpu>,<&clk_153m6>,<&clk_208m>,<&clk_256m>,<&clk_312m>,<&clk_384m>,<&clk_460m8>,<&clk_512m>;
 850                 clock-names = "clk_gpu_axi","clk_gpu","clk_153m6","clk_208m","clk_256m","clk_312m","clk_384m","clk_460m8","clk_512m";
 851
 852                 freq-list-len = <4>;
 853                 freq-lists = <153600 2 1>, <256000 4 1>, <384000 6 1>, <512000 7 1>;
 854                 freq-default = <1>;
 855                 freq-9 = <2>;
 856                 freq-8 = <1>;
 857                 freq-7 = <0>;
 858                 freq-5 = <0>;
 859                 freq-range-max = <3>;
 860                 freq-range-min = <0>;
 861         };
 862          ion {
 863                  compatible = "sprd,ion-sprd";
 864                  #address-cells = <1>;
 865                  #size-cells = <0>;
 866
 867                  sprd,ion-heap@1 {
 868                        reg = <1>;                      /* SYSTEM */
 869                        reg-names = "ion_heap_system";
 870                        sprd,ion-heap-type = <0>;       /* SYSTEM */
 871                        sprd,ion-heap-mem = <0x0 0x0>;
 872                  };
 873
 874                  sprd,ion-heap@2 {
 875                        reg = <2>;                      /* MM */
 876                        reg-names = "ion_heap_carveout_mm";
 877                        sprd,ion-heap-type = <0>;       /* carveout mm */
 878                        sprd,ion-heap-mem = <0x98800000 0x7100000>;
 879                  };
 880
 881                  sprd,ion-heap@3 {
 882                        reg = <3>;                      /* OVERLAY */
 883                        reg-names = "ion_heap_carveout_overlay";
 884                        sprd,ion-heap-type = <2>;       /* CARVEOUT */
 885                        sprd,ion-heap-mem = <0x9FCDE000 0x322000>;      /* 480*854*4*2, 8K alignment */
 886                  };
 887          };
 888          sprd_iommu0:sprd_iommu@21400000 {
 889                  compatible  = "sprd,sprd_iommu";//gsp
 890                  func-name = "sprd_iommu_gsp";
 891                  reg = <0x10000000 0x2000000>, //iova
 892                        <0x21400000 0x8000>,  //pgt
 893                        <0x21408000 0x8000>;  //ctrl_reg
 894                  reg_name = "iova","pgt","ctrl_reg";
 895                  clock-names = "clk_gsp_emc","clk_153m6","clk_gsp";
 896                  clocks = <&clk_gsp_emc>, <&clk_153m6>,<&clk_gsp>;
 897                  status = "ok";
 898          };
 899          sprd_iommu1:sprd_iommu@60f00000 {
 900                  compatible  = "sprd,sprd_iommu";//mm
 901                  func-name = "sprd_iommu_mm";
 902                  reg = <0x20000000 0x8000000>,   //iova
 903                        <0x60f00000 0x20000>,     //pgt
 904                        <0x60f20000 0x2000>;      //ctrl_reg
 905                  reg_name = "iova","pgt","ctrl_reg";
 906                  clock-names = "clk_mmu","clk_mm_i";
 907                  clocks = <&clk_mmu>,<&clk_mm>;
 908                  status = "ok";
 909          };
 910
 911          sprd_rf2351: sprd_rf2351@40070000{
 912                 compatible  = "sprd,sprd_rf2351";
 913                 reg = <0X40070000 0x1000>,              /*RFSPI*/
 914                         <0X402E0000 0x10000>;           /*APB_EB0*/
 915                 clock-names = "clk_cpll";
 916                 clocks = <&clk_cpll>;
 917          };
 918          gps_2351: gps_2351@21c00000{
 919                 compatible  = "sprd,gps_2351";
 920                 interrupts = <0 52 0x0>;
 921                 gpios = <&d_gpio_gpio 58 0>;
 922                 reg = <0X21C00000 0x1000>,              /*GPS CORE BASE*/
 923                         <0X20D00000 0x10000>,           /*AHB_ADDR*/
 924                         <0X402B0000 0x10000>;           /*PMU BASE*/
 925          };
 926
 927         sprd-io-base {
 928                 #address-cells = <1>;
 929                 #size-cells = <1>;
 930                 ranges = <0 0 0x80000000>;
 931                 ahb {
 932                         compatible = "sprd,ahb";
 933                         reg = <0x20d00000 0x10000>;
 934                 };
 935                 aonapb {
 936                         compatible = "sprd,aonapb";
 937                         reg = <0x402e0000 0x10000>;
 938                 };
 939                 apbreg {
 940                         compatible = "sprd,apbreg";
 941                         reg = <0x71300000 0x10000>;
 942                 };
 943                 pmu {
 944                         compatible = "sprd,pmu";
 945                         reg = <0x402b0000 0x10000>;
 946                 };
 947                 mmahb {
 948                         compatible = "sprd,mmahb";
 949                         reg = <0x60d00000 0x4000>;
 950                 };
 951                 mmckg {
 952                         compatible = "sprd,mmckg";
 953                         reg = <0x60e00000 0x1000>;
 954                 };
 955                 adislave {
 956                         compatible = "sprd,adislave";
 957                         reg = <0x40038000 0x1000>;
 958                 };
 959                 gpuapb {
 960                         compatible = "sprd,gpuapb";
 961                         reg = <0x60100000 0x1000>;
 962                 };
 963                 aonckg {
 964                         compatible = "sprd,aonckg";
 965                         reg = <0x402d0000 0x1000>;
 966                 };
 967                 apbckg {
 968                         compatible = "sprd,apbckg";
 969                         reg = <0x71200000 0x10000>;
 970                 };
 971                 core {
 972                         compatible = "sprd,core";
 973                         reg = <0x12000000 0x10000>;
 974                 };
 975                 int {
 976                         compatible = "sprd,int";
 977                         reg = <0x40200000 0x1000>;
 978                 };
 979                 intc0 {
 980                         compatible = "sprd,intc0";
 981                         reg = <0x71400000 0x1000>;
 982                 };
 983                 intc1 {
 984                         compatible = "sprd,intc1";
 985                         reg = <0x71500000 0x1000>;
 986                 };
 987                 intc2 {
 988                         compatible = "sprd,intc2";
 989                         reg = <0x71600000 0x1000>;
 990                 };
 991                 intc3 {
 992                         compatible = "sprd,intc3";
 993                         reg = <0x71700000 0x1000>;
 994                 };
 995                 uidefuse {
 996                         compatible = "sprd,uidefuse";
 997                         reg = <0x40240000 0x1000>;
 998                 };
 999                 isp {
1000                         compatible = "sprd,isp";
1001                         reg = <0x60a00000 0x8000>;
1002                 };
1003                 ca7wdg {
1004                         compatible = "sprd,ca7wdg";
1005                         reg = <0x40320000 0x1000>;
1006                 };
1007                 csi2 {
1008                         compatible = "sprd,csi2";
1009                         reg = <0x60c00000 0x1000>;
1010                 };
1011                 wdg {
1012                         compatible = "sprd,wdg";
1013                         reg = <0x40290000 0x1000>;
1014                 };
1015                 ipi {
1016                         compatible = "sprd,ipi";
1017                         reg = <0x402c0000 0x1000>;
1018                 };
1019                 dcam {
1020                         compatible = "sprd,dcam";
1021                         reg = <0x60800000 0x10000>;
1022                 };
1023                 syscnt {
1024                         compatible = "sprd,syscnt";
1025                         reg = <0x40230000 0x1000>;
1026                 };
1027                 dma0 {
1028                         compatible = "sprd,dma0";
1029                         reg = <0x20100000 0x4000>;
1030                 };
1031                 pub {
1032                         compatible = "sprd,pub";
1033                         reg = <0x300e0000 0x10000>;
1034                 };
1035                 pin {
1036                         compatible = "sprd,pin";
1037                         reg = <0x402a0000 0x1000>;
1038                 };
1039                 axibm0 {
1040                         compatible  = "sprd,axibm0";
1041                         reg = <0 0x30040000 0 0x20000>;
1042                         interrupts = <0 86 0x0>;
1043                 };
1044         };
1045         sprd_bm {
1046                 compatible = "sprd,sprd_bm";
1047                 reg = <0x30040000 0xA0000>,
1048                    <0x20E00000 0x300000>;
1049                 interrupts = <0 86 0x0>;
1050                 sprd,bm_status = <1>;
1051                 sprd,bm_count = <10 10>;
1052                 sprd,mm_chn = <0 1>;
1053                 sprd,gpu_chn = <1 1>;
1054                 sprd,disp_chn = <2 1>;
1055                 sprd,cpu_chn = <3 1>;
1056                 sprd,cp0_arm1_chn = <4 1>;
1057                 sprd,cp0_arm0_chn = <5 1>;
1058                 sprd,ap_chn = <6 1>;
1059                 sprd,zip_chn = <7 1>;
1060                 sprd,cp2_chn = <8 1>;
1061                 sprd,cp0_dsp_chn = <9 1>;
1062                 sprd,ap_cpu_chn = <0 0>;
1063                 sprd,ap_dap_chn = <0 1>;
1064                 sprd,ap_dma_w_chn = <1 0>;
1065                 sprd,ap_dma_r_chn = <1 1>;
1066                 sprd,ap_sdio_0_chn = <1 2>;
1067                 sprd,ap_sdio_1_chn = <1 3>;
1068                 sprd,ap_emmc_chn = <2 0>;
1069                 sprd,ap_sdio_2_chn = <2 1>;
1070                 sprd,ap_nfc_chn = <2 2>;
1071                 sprd,ap_usb_chn = <2 3>;
1072         };
1073         wdt@40290000 {
1074                 compatible = "sprd,sprd-wdt";
1075                 reg = <0x40290000 0x1000>,
1076                         <0x40320000 0x1000>;
1077                 interrupts = <0 124 0x0>;
1078         };
1079 };
1080
1081 &vbc_r2p0 {
1082         status = "okay";
1083 };
1084
1085 &sprd_codec {
1086         status = "okay";
1087         sprd,audio_power_ver = <4>;
1088 };
1089
1090 &i2s0 {
1091         sprd,config_type = "pcm";
1092         sprd,slave_timeout = <0xF11>;
1093         sprd,_hw_port = <0>;
1094         sprd,fs = <8000>;
1095         sprd,bus_type = <1>;
1096         sprd,rtx_mode = <3>;
1097         sprd,byte_per_chan = <1>;
1098         sprd,slave_mode = <0>;
1099         sprd,lsb = <1>;
1100         sprd,lrck = <1>;
1101         sprd,low_for_left = <1>;
1102         sprd,clk_inv = <0>;
1103         sprd,pcm_short_frame = <1>;
1104         sprd,pcm_slot = <0x1>;
1105         sprd,pcm_cycle = <1>;
1106         sprd,tx_watermark = <12>;
1107         sprd,rx_watermark = <20>;
1108         status = "okay";
1109 };
1110
1111 &i2s1 {
1112         status = "okay";
1113 };
1114
1115
1116
1117 &i2s_sound {
1118         sprd,i2s = <&i2s0>, <&i2s1>;
1119 };
1120 &sprd_battery {
1121         gpios = <&a_eic_gpio 0 0        /* chg int */
1122                 &a_eic_gpio 4 0        /* cv state */
1123                 &a_eic_gpio 6 0         /* chg ovi */
1124                 &a_eic_gpio 9 0>;       /* battery detect */
1125
1126         fgu-mode = <0>;
1127         alm-soc = <5>;
1128         alm-vol = <3500>;
1129         soft-vbat-uvlo = <3100>;
1130         rint = <250>;
1131         cnom = <1900>;
1132         rsense-real = <230>;
1133         rsense-spec = <200>;
1134         relax-current = <50>;
1135         fgu-cal-ajust = <0>;
1136         ocv-tab-size = <21>;
1137         ocv-tab-vol = <4168 4113 4076 4016 3973 3953 3924 3894 3851 3821 3802 3789 3780 3777 3771 3758 3738 3703 3684 3609 3400>;
1138         ocv-tab-cap = <100  95   90   85   80   75   70   65   60   55   50   45   40   35   30   25   20   15   10   5    0>;
1139 };
1140 &vddcore{
1141         hide-offset = <1150>;/*kernel hide_offset =  hide-offset - 1000*/
1142 };
1143 &vddarm{
1144         hide-offset = <1150>;/*kernel hide_offset =  hide-offset - 1000*/
1145 };