arch/arm/boot/dts/scx35-clocks.dtsi

   1 / {
   2
   3         clks: clocks {
   4                 compatible = "sprd,scx35-clocks";
   5                 #address-cells = <1>;
   6                 #size-cells = <1>;
   7
   8                 ext_26m: ext_26m {
   9                         compatible = "sprd,fixed-clock";
  10                         #clock-cells = <0>;
  11                         clock-frequency = <26000000>;
  12                         clock-output-names = "ext_26m";
  13                 };
  14
  15                 ext_32k: ext_32k {
  16                         compatible = "sprd,fixed-clock";
  17                         #clock-cells = <0>;
  18                         clock-frequency = <32768>;
  19                         clock-output-names = "ext_32k";
  20                 };
  21
  22                 clk_mpll: clk_mpll {
  23                         compatible = "sprd,adjustable-pll-clock";
  24                         #clock-cells = <0>;
  25                         reg = <0x402e0014 0x7ff 0x402b008c 0x1>;        /* mult reg and prepare reg */
  26                         clock-output-names = "clk_mpll";
  27                 };
  28
  29                 clk_dpll: clk_dpll {
  30                         compatible = "sprd,adjustable-pll-clock";
  31                         #clock-cells = <0>;
  32                         reg = <0x402e0018 0x7ff 0x402b0090 0x1>;        /* mult reg and prepare reg */
  33                         clock-output-names = "clk_dpll";
  34                 };
  35
  36                 clk_tdpll: clk_tdpll {
  37                         compatible = "sprd,fixed-pll-clock";
  38                         #clock-cells = <0>;
  39                         clock-frequency = <768000000>;
  40                         reg = <0x402b0094 0x1>; /* prepare reg */
  41                         clock-output-names = "clk_tdpll";
  42                 };
  43
  44                 clk_wpll: clk_wpll {
  45                         compatible = "sprd,fixed-pll-clock";
  46                         #clock-cells = <0>;
  47                         clock-frequency = <921600000>;
  48                         reg = <0x402b0098 0x1>; /* prepare reg */
  49                         clock-output-names = "clk_wpll";
  50                 };
  51
  52                 clk_cpll: clk_cpll {
  53                         compatible = "sprd,fixed-pll-clock";
  54                         #clock-cells = <0>;
  55                         clock-frequency = <624000000>;
  56                         reg = <0x402b009c 0x1>; /* prepare reg */
  57                         clock-output-names = "clk_cpll";
  58                 };
  59
  60                 clk_wifipll: clk_wifipll {
  61                         compatible = "sprd,fixed-pll-clock";
  62                         #clock-cells = <0>;
  63                         clock-frequency = <880000000>;
  64                         reg = <0x402b00a0 0x1>; /* prepare reg */
  65                         clock-output-names = "clk_wifipll";
  66                 };
  67
  68                 clk_300m: clk_300m {
  69                         compatible = "sprd,fixed-factor-clock";
  70                         #clock-cells = <0>;
  71                         clock-mult = <1>;
  72                         clock-div = <3>;
  73                         clocks = <&clk_mpll>;
  74                         clock-output-names = "clk_300m";
  75                 };
  76
  77                 clk_37m5: clk_37m5 {
  78                         compatible = "sprd,fixed-factor-clock";
  79                         #clock-cells = <0>;
  80                         clock-mult = <1>;
  81                         clock-div = <24>;
  82                         clocks = <&clk_mpll>;
  83                         clock-output-names = "clk_37m5";
  84                 };
  85
  86                 clk_66m_d: clk_66m_d {
  87                         compatible = "sprd,fixed-factor-clock";
  88                         #clock-cells = <0>;
  89                         clock-mult = <1>;
  90                         clock-div = <8>;
  91                         clocks = <&clk_dpll>;
  92                         clock-output-names = "clk_66m_d";
  93                 };
  94
  95                 clk_51m2_w: clk_51m2_w {
  96                         compatible = "sprd,fixed-factor-clock";
  97                         #clock-cells = <0>;
  98                         clock-mult = <1>;
  99                         clock-div = <18>;
 100                         clocks = <&clk_wpll>;
 101                         clock-output-names = "clk_51m2_w";
 102                 };
 103
 104                 clk_40m_wf1: clk_40m_wf1 {
 105                         compatible = "sprd,fixed-factor-clock";
 106                         #clock-cells = <0>;
 107                         clock-mult = <1>;
 108                         clock-div = <22>;
 109                         clocks = <&clk_wifipll>;
 110                         clock-output-names = "clk_40m_wf1";
 111                 };
 112
 113                 clk_312m: clk_312m {
 114                         compatible = "sprd,fixed-factor-clock";
 115                         #clock-cells = <0>;
 116                         clock-mult = <1>;
 117                         clock-div = <2>;
 118                         clocks = <&clk_cpll>;
 119                         clock-output-names = "clk_312m";
 120                 };
 121
 122                 clk_208m: clk_208m {
 123                         compatible = "sprd,fixed-factor-clock";
 124                         #clock-cells = <0>;
 125                         clock-mult = <1>;
 126                         clock-div = <3>;
 127                         clocks = <&clk_cpll>;
 128                         clock-output-names = "clk_208m";
 129                 };
 130
 131                 clk_104m: clk_104m {
 132                         compatible = "sprd,fixed-factor-clock";
 133                         #clock-cells = <0>;
 134                         clock-mult = <1>;
 135                         clock-div = <6>;
 136                         clocks = <&clk_cpll>;
 137                         clock-output-names = "clk_104m";
 138                 };
 139
 140                 clk_52m: clk_52m {
 141                         compatible = "sprd,fixed-factor-clock";
 142                         #clock-cells = <0>;
 143                         clock-mult = <1>;
 144                         clock-div = <12>;
 145                         clocks = <&clk_cpll>;
 146                         clock-output-names = "clk_52m";
 147                 };
 148
 149                 clk_384m: clk_384m {
 150                         compatible = "sprd,fixed-factor-clock";
 151                         #clock-cells = <0>;
 152                         clock-mult = <1>;
 153                         clock-div = <2>;
 154                         clocks = <&clk_tdpll>;
 155                         clock-output-names = "clk_384m";
 156                 };
 157
 158                 clk_256m: clk_256m {
 159                         compatible = "sprd,fixed-factor-clock";
 160                         #clock-cells = <0>;
 161                         clock-mult = <1>;
 162                         clock-div = <3>;
 163                         clocks = <&clk_tdpll>;
 164                         clock-output-names = "clk_256m";
 165                 };
 166
 167                 clk_192m: clk_192m {
 168                         compatible = "sprd,fixed-factor-clock";
 169                         #clock-cells = <0>;
 170                         clock-mult = <1>;
 171                         clock-div = <4>;
 172                         clocks = <&clk_tdpll>;
 173                         clock-output-names = "clk_192m";
 174                 };
 175
 176                 clk_153m6: clk_153m6 {
 177                         compatible = "sprd,fixed-factor-clock";
 178                         #clock-cells = <0>;
 179                         clock-mult = <1>;
 180                         clock-div = <5>;
 181                         clocks = <&clk_tdpll>;
 182                         clock-output-names = "clk_153m6";
 183                 };
 184
 185                 clk_128m: clk_128m {
 186                         compatible = "sprd,fixed-factor-clock";
 187                         #clock-cells = <0>;
 188                         clock-mult = <1>;
 189                         clock-div = <6>;
 190                         clocks = <&clk_tdpll>;
 191                         clock-output-names = "clk_128m";
 192                 };
 193
 194                 clk_96m: clk_96m {
 195                         compatible = "sprd,fixed-factor-clock";
 196                         #clock-cells = <0>;
 197                         clock-mult = <1>;
 198                         clock-div = <8>;
 199                         clocks = <&clk_tdpll>;
 200                         clock-output-names = "clk_96m";
 201                 };
 202
 203                 clk_76m8: clk_76m8 {
 204                         compatible = "sprd,fixed-factor-clock";
 205                         #clock-cells = <0>;
 206                         clock-mult = <1>;
 207                         clock-div = <10>;
 208                         clocks = <&clk_tdpll>;
 209                         clock-output-names = "clk_76m8";
 210                 };
 211
 212                 clk_64m: clk_64m {
 213                         compatible = "sprd,fixed-factor-clock";
 214                         #clock-cells = <0>;
 215                         clock-mult = <1>;
 216                         clock-div = <12>;
 217                         clocks = <&clk_tdpll>;
 218                         clock-output-names = "clk_64m";
 219                 };
 220
 221                 clk_51m2: clk_51m2 {
 222                         compatible = "sprd,fixed-factor-clock";
 223                         #clock-cells = <0>;
 224                         clock-mult = <1>;
 225                         clock-div = <15>;
 226                         clocks = <&clk_tdpll>;
 227                         clock-output-names = "clk_51m2";
 228                 };
 229
 230                 clk_48m: clk_48m {
 231                         compatible = "sprd,fixed-factor-clock";
 232                         #clock-cells = <0>;
 233                         clock-mult = <1>;
 234                         clock-div = <16>;
 235                         clocks = <&clk_tdpll>;
 236                         clock-output-names = "clk_48m";
 237                 };
 238
 239                 clk_38m4: clk_38m4 {
 240                         compatible = "sprd,fixed-factor-clock";
 241                         #clock-cells = <0>;
 242                         clock-mult = <1>;
 243                         clock-div = <20>;
 244                         clocks = <&clk_tdpll>;
 245                         clock-output-names = "clk_38m4";
 246                 };
 247
 248                 clk_24m: clk_24m {
 249                         compatible = "sprd,fixed-factor-clock";
 250                         #clock-cells = <0>;
 251                         clock-mult = <1>;
 252                         clock-div = <32>;
 253                         clocks = <&clk_tdpll>;
 254                         clock-output-names = "clk_24m";
 255                 };
 256
 257                 clk_12m: clk_12m {
 258                         compatible = "sprd,fixed-factor-clock";
 259                         #clock-cells = <0>;
 260                         clock-mult = <1>;
 261                         clock-div = <64>;
 262                         clocks = <&clk_tdpll>;
 263                         clock-output-names = "clk_12m";
 264                 };
 265
 266                 clk_mcu: clk_mcu {
 267                         compatible = "sprd,composite-dev-clock";
 268                         #clock-cells = <0>;
 269                         reg = <0x20d0000c 0x7 0x20d0000c 0x70>; /* select reg and divider reg */
 270                         clocks = <&ext_26m>, <&clk_dpll>, <&clk_cpll>, <&clk_tdpll>, <&clk_wifipll>, <&clk_wpll>, <&clk_mpll>;
 271                         clock-output-names = "clk_mcu";
 272                 };
 273
 274                 clk_ca7_axi: clk_ca7_axi {
 275                         compatible = "sprd,divider-clock";
 276                         #clock-cells = <0>;
 277                         reg = <0x20d0000c 0x700>;       /* divider reg */
 278                         clocks = <&clk_mcu>;
 279                         clock-output-names = "clk_ca7_axi";
 280                 };
 281
 282                 clk_ca7_dbg: clk_ca7_dbg {
 283                         compatible = "sprd,divider-clock";
 284                         #clock-cells = <0>;
 285                         reg = <0x20d0000c 0x70000 0x20d00014 0x100>;    /* divider reg and enable reg */
 286                         clocks = <&clk_mcu>;
 287                         clock-output-names = "clk_ca7_dbg";
 288                 };
 289
 290                 clk_ap_ahb: clk_ap_ahb {
 291                         compatible = "sprd,muxed-clock";
 292                         #clock-cells = <0>;
 293                         reg = <0x71200020 0x3>; /* select reg */
 294                         clocks = <&ext_26m>, <&clk_76m8>, <&clk_128m>, <&clk_192m>;
 295                         clock-output-names = "clk_ap_ahb";
 296                 };
 297
 298                 clk_ap_apb: clk_ap_apb {
 299                         compatible = "sprd,muxed-clock";
 300                         #clock-cells = <0>;
 301                         reg = <0x71200024 0x3>; /* select reg */
 302                         clocks = <&ext_26m>, <&clk_64m>, <&clk_96m>, <&clk_128m>;
 303                         clock-output-names = "clk_ap_apb";
 304                 };
 305
 306                 clk_pub_ahb: clk_pub_ahb {
 307                         compatible = "sprd,muxed-clock";
 308                         #clock-cells = <0>;
 309                         reg = <0x402d0020 0x3>; /* select reg */
 310                         clocks = <&ext_26m>, <&clk_96m>, <&clk_128m>, <&clk_153m6>;
 311                         clock-output-names = "clk_pub_ahb";
 312                 };
 313
 314                 clk_emc: clk_emc {
 315                         compatible = "sprd,composite-dev-clock";
 316                         #clock-cells = <0>;
 317                         reg = <0x402d0024 0x3 0x402d0024 0x300>;        /* select reg and divider reg */
 318                         clocks = <&ext_26m>, <&clk_256m>, <&clk_384m>, <&clk_dpll>;
 319                         clock-output-names = "clk_emc";
 320                 };
 321
 322                 clk_aon_apb: clk_aon_apb {
 323                         compatible = "sprd,composite-dev-clock";
 324                         #clock-cells = <0>;
 325                         reg = <0x402d0028 0x3 0x402d0028 0x300>;        /* select reg and divider reg */
 326                         clocks = <&ext_26m>, <&clk_76m8>, <&clk_96m>, <&clk_128m>;
 327                         clock-output-names = "clk_aon_apb";
 328                 };
 329
 330                 clk_disp_emc: clk_disp_emc {
 331                         compatible = "sprd,gate-clock";
 332                         #clock-cells = <0>;
 333                         reg = <0x402e0004 0x800>;       /* enable reg */
 334                         clocks = <&clk_aon_apb>;
 335                         clock-output-names = "clk_disp_emc";
 336                 };
 337
 338                 clk_gsp: clk_gsp {
 339                         compatible = "sprd,muxed-clock";
 340                         #clock-cells = <0>;
 341                         reg = <0x71200028 0x3 0x20d00000 0x8>;  /* select reg and enable reg */
 342                         clocks = <&clk_96m>, <&clk_153m6>, <&clk_192m>, <&clk_256m>;
 343                         clock-output-names = "clk_gsp";
 344                 };
 345
 346                 clk_dispc0: clk_dispc0 {
 347                         compatible = "sprd,composite-dev-clock";
 348                         #clock-cells = <0>;
 349                         reg = <0x7120002c 0x3 0x7120002c 0x700 0x20d00000 0x2>; /* select reg and divider reg and enable reg */
 350                         clocks = <&clk_153m6>, <&clk_192m>, <&clk_256m>, <&clk_312m>;
 351                         clock-output-names = "clk_dispc0";
 352                 };
 353
 354                 clk_dispc0_dbi: clk_dispc0_dbi {
 355                         compatible = "sprd,composite-dev-clock";
 356                         #clock-cells = <0>;
 357                         reg = <0x71200030 0x3 0x71200030 0x700 0x20d00000 0x2>; /* select reg and divider reg and enable reg */
 358                         clocks = <&clk_128m>, <&clk_153m6>, <&clk_192m>, <&clk_256m>;
 359                         clock-output-names = "clk_dispc0_dbi";
 360                 };
 361
 362                 clk_dispc0_dpi: clk_dispc0_dpi {
 363                         compatible = "sprd,composite-dev-clock";
 364                         #clock-cells = <0>;
 365                         reg = <0x71200034 0x3 0x71200034 0xff00 0x20d00000 0x2>;        /* select reg and divider reg and enable reg */
 366                         clocks = <&clk_128m>, <&clk_153m6>, <&clk_192m>, <&clk_384m>;
 367                         clock-output-names = "clk_dispc0_dpi";
 368                 };
 369
 370                 clk_dispc1: clk_dispc1 {
 371                         compatible = "sprd,composite-dev-clock";
 372                         #clock-cells = <0>;
 373                         reg = <0x71200038 0x3 0x71200038 0x700 0x20d00000 0x4>; /* select reg and divider reg and enable reg */
 374                         clocks = <&clk_153m6>, <&clk_192m>, <&clk_256m>, <&clk_312m>;
 375                         clock-output-names = "clk_dispc1";
 376                 };
 377
 378                 clk_dispc1_dbi: clk_dispc1_dbi {
 379                         compatible = "sprd,composite-dev-clock";
 380                         #clock-cells = <0>;
 381                         reg = <0x7120003c 0x3 0x7120003c 0x700 0x20d00000 0x4>; /* select reg and divider reg and enable reg */
 382                         clocks = <&clk_128m>, <&clk_153m6>, <&clk_192m>, <&clk_256m>;
 383                         clock-output-names = "clk_dispc1_dbi";
 384                 };
 385
 386                 clk_dispc1_dpi: clk_dispc1_dpi {
 387                         compatible = "sprd,composite-dev-clock";
 388                         #clock-cells = <0>;
 389                         reg = <0x71200040 0x3 0x71200040 0xff00 0x20d00000 0x4>;        /* select reg and divider reg and enable reg */
 390                         clocks = <&clk_128m>, <&clk_153m6>, <&clk_192m>, <&clk_384m>;
 391                         clock-output-names = "clk_dispc1_dpi";
 392                 };
 393
 394                 clk_nfc: clk_nfc {
 395                         compatible = "sprd,composite-dev-clock";
 396                         #clock-cells = <0>;
 397                         reg = <0x71200044 0x3 0x71200044 0x700 0x20d00000 0x40>;        /* select reg and divider reg and enable reg */
 398                         clocks = <&clk_64m>, <&clk_128m>, <&clk_153m6>;
 399                         clock-output-names = "clk_nfc";
 400                 };
 401
 402                 clk_sdio0: clk_sdio0 {
 403                         compatible = "sprd,composite-dev-clock";
 404                         #clock-cells = <0>;
 405                         reg = <0x71200048 0x3 0x71200048 0x700 0x20d00000 0x100>;       /* select reg and divider reg and enable reg */
 406                         clocks = <&ext_26m>, <&clk_192m>, <&clk_256m>, <&clk_312m>;
 407                         clock-output-names = "clk_sdio0";
 408                 };
 409
 410                 clk_sdio1: clk_sdio1 {
 411                         compatible = "sprd,muxed-clock";
 412                         #clock-cells = <0>;
 413                         reg = <0x7120004c 0x3 0x20d00000 0x200>;        /* select reg and enable reg */
 414                         clocks = <&clk_48m>, <&clk_76m8>, <&clk_96m>, <&clk_128m>;
 415                         clock-output-names = "clk_sdio1";
 416                 };
 417
 418                 clk_sdio2: clk_sdio2 {
 419                         compatible = "sprd,muxed-clock";
 420                         #clock-cells = <0>;
 421                         reg = <0x71200050 0x3 0x20d00000 0x400>;        /* select reg and enable reg */
 422                         clocks = <&clk_48m>, <&clk_76m8>, <&clk_96m>, <&clk_128m>;
 423                         clock-output-names = "clk_sdio2";
 424                 };
 425
 426                 clk_emmc: clk_emmc {
 427                         compatible = "sprd,muxed-clock";
 428                         #clock-cells = <0>;
 429                         reg = <0x71200054 0x3 0x20d00000 0x800>;        /* select reg and enable reg */
 430                         clocks = <&ext_26m>, <&clk_192m>, <&clk_256m>, <&clk_312m>;
 431                         clock-output-names = "clk_emmc";
 432                 };
 433
 434                 clk_gps_tcxo: clk_gps_tcxo {
 435                         compatible = "sprd,fixed-clock";
 436                         #clock-cells = <0>;
 437                         clock-frequency = <64000000>;
 438                         clock-output-names = "clk_gps_tcxo";
 439                 };
 440
 441                 clk_gps: clk_gps {
 442                         compatible = "sprd,muxed-clock";
 443                         #clock-cells = <0>;
 444                         reg = <0x71200058 0x1 0x20d00000 0x1000>;       /* select reg and enable reg */
 445                         clocks = <&clk_64m>, <&clk_76m8>;
 446                         clock-output-names = "clk_gps";
 447                 };
 448
 449                 clk_usb_ref: clk_usb_ref {
 450                         compatible = "sprd,muxed-clock";
 451                         #clock-cells = <0>;
 452                         reg = <0x71200060 0x1 0x20d00000 0x10>; /* select reg and enable reg */
 453                         clocks = <&clk_12m>, <&clk_24m>;
 454                         clock-output-names = "clk_usb_ref";
 455                 };
 456
 457                 clk_uart0: clk_uart0 {
 458                         compatible = "sprd,composite-dev-clock";
 459                         #clock-cells = <0>;
 460                         reg = <0x71200064 0x3 0x71200064 0x700 0x71300000 0x2000>;      /* select reg and divider reg and enable reg */
 461                         clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>;
 462                         clock-output-names = "clk_uart0";
 463                 };
 464
 465                 clk_uart1: clk_uart1 {
 466                         compatible = "sprd,composite-dev-clock";
 467                         #clock-cells = <0>;
 468                         reg = <0x71200068 0x3 0x71200068 0x700 0x71300000 0x4000>;      /* select reg and divider reg and enable reg */
 469                         clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>;
 470                         clock-output-names = "clk_uart1";
 471                 };
 472
 473                 clk_uart2: clk_uart2 {
 474                         compatible = "sprd,composite-dev-clock";
 475                         #clock-cells = <0>;
 476                         reg = <0x7120006c 0x3 0x7120006c 0x700 0x71300000 0x8000>;      /* select reg and divider reg and enable reg */
 477                         clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>;
 478                         clock-output-names = "clk_uart2";
 479                 };
 480
 481                 clk_uart3: clk_uart3 {
 482                         compatible = "sprd,composite-dev-clock";
 483                         #clock-cells = <0>;
 484                         reg = <0x71200070 0x3 0x71200070 0x700 0x71300000 0x10000>;     /* select reg and divider reg and enable reg */
 485                         clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>;
 486                         clock-output-names = "clk_uart3";
 487                 };
 488
 489                 clk_uart4: clk_uart4 {
 490                         compatible = "sprd,composite-dev-clock";
 491                         #clock-cells = <0>;
 492                         reg = <0x71200074 0x3 0x71200074 0x700 0x71300000 0x20000>;     /* select reg and divider reg and enable reg */
 493                         clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>;
 494                         clock-output-names = "clk_uart4";
 495                 };
 496
 497                 clk_i2c0: clk_i2c0 {
 498                         compatible = "sprd,composite-dev-clock";
 499                         #clock-cells = <0>;
 500                         reg = <0x71200078 0x3 0x71200078 0x700 0x71300000 0x100>;       /* select reg and divider reg and enable reg */
 501                         clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>;
 502                         clock-output-names = "clk_i2c0";
 503                 };
 504
 505                 clk_i2c1: clk_i2c1 {
 506                         compatible = "sprd,composite-dev-clock";
 507                         #clock-cells = <0>;
 508                         reg = <0x7120007c 0x3 0x7120007c 0x700 0x71300000 0x200>;       /* select reg and divider reg and enable reg */
 509                         clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>;
 510                         clock-output-names = "clk_i2c1";
 511                 };
 512
 513                 clk_i2c2: clk_i2c2 {
 514                         compatible = "sprd,composite-dev-clock";
 515                         #clock-cells = <0>;
 516                         reg = <0x71200080 0x3 0x71200080 0x700 0x71300000 0x400>;       /* select reg and divider reg and enable reg */
 517                         clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>;
 518                         clock-output-names = "clk_i2c2";
 519                 };
 520
 521                 clk_i2c3: clk_i2c3 {
 522                         compatible = "sprd,composite-dev-clock";
 523                         #clock-cells = <0>;
 524                         reg = <0x71200084 0x3 0x71200084 0x700 0x71300000 0x800>;       /* select reg and divider reg and enable reg */
 525                         clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>;
 526                         clock-output-names = "clk_i2c3";
 527                 };
 528
 529                 clk_i2c4: clk_i2c4 {
 530                         compatible = "sprd,composite-dev-clock";
 531                         #clock-cells = <0>;
 532                         reg = <0x71200088 0x3 0x71200088 0x700 0x71300000 0x1000>;      /* select reg and divider reg and enable reg */
 533                         clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>;
 534                         clock-output-names = "clk_i2c4";
 535                 };
 536
 537                 clk_spi0: clk_spi0 {
 538                         compatible = "sprd,composite-dev-clock";
 539                         #clock-cells = <0>;
 540                         reg = <0x7120008c 0x3 0x7120008c 0x700 0x71300000 0x20>;        /* select reg and divider reg and enable reg */
 541                         clocks = <&ext_26m>, <&clk_96m>, <&clk_153m6>, <&clk_192m>;
 542                         clock-output-names = "clk_spi0";
 543                 };
 544
 545                 clk_spi1: clk_spi1 {
 546                         compatible = "sprd,composite-dev-clock";
 547                         #clock-cells = <0>;
 548                         reg = <0x71200090 0x3 0x71200090 0x700 0x71300000 0x40>;        /* select reg and divider reg and enable reg */
 549                         clocks = <&ext_26m>, <&clk_96m>, <&clk_153m6>, <&clk_192m>;
 550                         clock-output-names = "clk_spi1";
 551                 };
 552
 553                 clk_spi2: clk_spi2 {
 554                         compatible = "sprd,composite-dev-clock";
 555                         #clock-cells = <0>;
 556                         reg = <0x71200094 0x3 0x71200094 0x700 0x71300000 0x80>;        /* select reg and divider reg and enable reg */
 557                         clocks = <&ext_26m>, <&clk_96m>, <&clk_153m6>, <&clk_192m>;
 558                         clock-output-names = "clk_spi2";
 559                 };
 560
 561                 clk_iis0: clk_iis0 {
 562                         compatible = "sprd,composite-dev-clock";
 563                         #clock-cells = <0>;
 564                         reg = <0x71200098 0x3 0x71200098 0x700 0x71300000 0x2>; /* select reg and divider reg and enable reg */
 565                         clocks = <&ext_26m>, <&clk_76m8>, <&clk_128m>;
 566                         clock-output-names = "clk_iis0";
 567                 };
 568
 569                 clk_iis1: clk_iis1 {
 570                         compatible = "sprd,composite-dev-clock";
 571                         #clock-cells = <0>;
 572                         reg = <0x7120009c 0x3 0x7120009c 0x700 0x71300000 0x4>; /* select reg and divider reg and enable reg */
 573                         clocks = <&ext_26m>, <&clk_76m8>, <&clk_128m>;
 574                         clock-output-names = "clk_iis1";
 575                 };
 576
 577                 clk_iis2: clk_iis2 {
 578                         compatible = "sprd,composite-dev-clock";
 579                         #clock-cells = <0>;
 580                         reg = <0x712000a0 0x3 0x712000a0 0x700 0x71300000 0x8>; /* select reg and divider reg and enable reg */
 581                         clocks = <&ext_26m>, <&clk_76m8>, <&clk_128m>;
 582                         clock-output-names = "clk_iis2";
 583                 };
 584
 585                 clk_iis3: clk_iis3 {
 586                         compatible = "sprd,composite-dev-clock";
 587                         #clock-cells = <0>;
 588                         reg = <0x712000a4 0x3 0x712000a4 0x700 0x71300000 0x10>;        /* select reg and divider reg and enable reg */
 589                         clocks = <&ext_26m>, <&clk_76m8>, <&clk_128m>;
 590                         clock-output-names = "clk_iis3";
 591                 };
 592
 593                 clk_gpu_axi: clk_gpu_axi {
 594                         compatible = "sprd,gate-clock";
 595                         #clock-cells = <0>;
 596                         reg = <0x402e0000 0x8000000 0x402b0021 0x2000000>;      /* enable reg and prepare reg */
 597                         clocks = <&clk_aon_apb>;
 598                         clock-output-names = "clk_gpu_axi";
 599                 };
 600
 601                 clk_gpu: clk_gpu {
 602                         compatible = "sprd,composite-dev-clock";
 603                         #clock-cells = <0>;
 604                         reg = <0x60100004 0x3 0x60100004 0xc>;  /* select reg and divider reg */
 605                         clocks = <&clk_208m>, <&clk_256m>, <&clk_300m>, <&clk_312m>;
 606                         clock-output-names = "clk_gpu";
 607                 };
 608
 609                 clk_ccir_in: clk_ccir_in {
 610                         compatible = "sprd,fixed-clock";
 611                         #clock-cells = <0>;
 612                         clock-frequency = <64000000>;
 613                         clock-output-names = "clk_ccir_in";
 614                 };
 615
 616                 clk_mm: clk_mm {
 617                         compatible = "sprd,gate-clock";
 618                         #clock-cells = <0>;
 619                         reg = <0x402e0000 0x2000000 0x402b001d 0x2000000>;      /* enable reg and prepare reg */
 620                         clocks = <&clk_aon_apb>;
 621                         clock-output-names = "clk_mm";
 622                 };
 623
 624                 clk_mm_ahb: clk_mm_ahb {
 625                         compatible = "sprd,muxed-clock";
 626                         #clock-cells = <0>;
 627                         reg = <0x60e00020 0x3>; /* select reg */
 628                         clocks = <&ext_26m>, <&clk_96m>, <&clk_128m>, <&clk_153m6>;
 629                         clock-output-names = "clk_mm_ahb";
 630                 };
 631
 632                 clk_mm_ckg: clk_mm_ckg {
 633                         compatible = "sprd,gate-clock";
 634                         #clock-cells = <0>;
 635                         reg = <0x60d00000 0x40>;        /* enable reg */
 636                         clocks = <&clk_mm_ahb>;
 637                         clock-output-names = "clk_mm_ckg";
 638                 };
 639
 640                 clk_jpg: clk_jpg {
 641                         compatible = "sprd,muxed-clock";
 642                         #clock-cells = <0>;
 643                         reg = <0x60e00038 0x3 0x60d00000 0x20>; /* select reg and enable reg */
 644                         clocks = <&clk_76m8>, <&clk_128m>, <&clk_192m>, <&clk_256m>;
 645                         clock-output-names = "clk_jpg";
 646                 };
 647
 648                 clk_csi: clk_csi {
 649                         compatible = "sprd,gate-clock";
 650                         #clock-cells = <0>;
 651                         reg = <0x60d00000 0x10>;        /* enable reg */
 652                         clocks = <&clk_mm_ahb>;
 653                         clock-output-names = "clk_csi";
 654                 };
 655
 656                 clk_vsp: clk_vsp {
 657                         compatible = "sprd,muxed-clock";
 658                         #clock-cells = <0>;
 659                         reg = <0x60e00030 0x3 0x60d00000 0x8>;  /* select reg and enable reg */
 660                         clocks = <&clk_76m8>, <&clk_128m>, <&clk_192m>, <&clk_256m>;
 661                         clock-output-names = "clk_vsp";
 662                 };
 663
 664                 clk_isp: clk_isp {
 665                         compatible = "sprd,muxed-clock";
 666                         #clock-cells = <0>;
 667                         reg = <0x60e00034 0x3 0x60d00000 0x4>;  /* select reg and enable reg */
 668                         clocks = <&clk_76m8>, <&clk_128m>, <&clk_192m>, <&clk_256m>;
 669                         clock-output-names = "clk_isp";
 670                 };
 671
 672                 clk_ccir: clk_ccir {
 673                         compatible = "sprd,muxed-clock";
 674                         #clock-cells = <0>;
 675                         reg = <0x60e00028 0x10000 0x60d00000 0x2>;      /* select reg and enable reg */
 676                         clocks = <&clk_24m>, <&clk_ccir_in>;
 677                         clock-output-names = "clk_ccir";
 678                 };
 679
 680                 clk_dcam: clk_dcam {
 681                         compatible = "sprd,muxed-clock";
 682                         #clock-cells = <0>;
 683                         reg = <0x60e0002c 0x3 0x60d00000 0x1>;  /* select reg and enable reg */
 684                         clocks = <&clk_76m8>, <&clk_128m>, <&clk_192m>, <&clk_256m>;
 685                         clock-output-names = "clk_dcam";
 686                 };
 687
 688                 clk_sensor: clk_sensor {
 689                         compatible = "sprd,composite-dev-clock";
 690                         #clock-cells = <0>;
 691                         reg = <0x60e00024 0x3 0x60e00024 0x700 0x60d00000 0x2>; /* select reg and divider reg and enable reg */
 692                         clocks = <&ext_26m>, <&clk_48m>, <&clk_76m8>, <&clk_96m>;
 693                         clock-output-names = "clk_sensor";
 694                 };
 695
 696                 clk_mm_axi: clk_mm_axi {
 697                         compatible = "sprd,gate-clock";
 698                         #clock-cells = <0>;
 699                         reg = <0x60d00008 0x80>;        /* enable reg */
 700                         clocks = <&clk_mm>;
 701                         clock-output-names = "clk_mm_axi";
 702                 };
 703
 704                 clk_mm_mtx_axi: clk_mm_mtx_axi {
 705                         compatible = "sprd,gate-clock";
 706                         #clock-cells = <0>;
 707                         reg = <0x60d00008 0x100>;       /* enable reg */
 708                         clocks = <&clk_mm_axi>;
 709                         clock-output-names = "clk_mm_mtx_axi";
 710                 };
 711
 712                 clk_jpg_axi_ckg: clk_jpg_axi_ckg {
 713                         compatible = "sprd,gate-clock";
 714                         #clock-cells = <0>;
 715                         reg = <0x60d00008 0x40>;        /* enable reg */
 716                         clocks = <&clk_mm_mtx_axi>;
 717                         clock-output-names = "clk_jpg_axi_ckg";
 718                 };
 719
 720                 clk_vsp_axi_ckg: clk_vsp_axi_ckg {
 721                         compatible = "sprd,gate-clock";
 722                         #clock-cells = <0>;
 723                         reg = <0x60d00008 0x20>;        /* enable reg */
 724                         clocks = <&clk_mm_mtx_axi>;
 725                         clock-output-names = "clk_vsp_axi_ckg";
 726                 };
 727
 728                 clk_isp_axi_ckg: clk_isp_axi_ckg {
 729                         compatible = "sprd,gate-clock";
 730                         #clock-cells = <0>;
 731                         reg = <0x60d00008 0x10>;        /* enable reg */
 732                         clocks = <&clk_mm_mtx_axi>;
 733                         clock-output-names = "clk_isp_axi_ckg";
 734                 };
 735
 736                 clk_dcam_axi_ckg: clk_dcam_axi_ckg {
 737                         compatible = "sprd,gate-clock";
 738                         #clock-cells = <0>;
 739                         reg = <0x60d00008 0x8>; /* enable reg */
 740                         clocks = <&clk_mm_mtx_axi>;
 741                         clock-output-names = "clk_dcam_axi_ckg";
 742                 };
 743
 744                 clk_sensor_ckg: clk_sensor_ckg {
 745                         compatible = "sprd,gate-clock";
 746                         #clock-cells = <0>;
 747                         reg = <0x60d00008 0x4>; /* enable reg */
 748                         clocks = <&clk_mm_mtx_axi>;
 749                         clock-output-names = "clk_sensor_ckg";
 750                 };
 751
 752                 clk_mipi_csi_ckg: clk_mipi_csi_ckg {
 753                         compatible = "sprd,gate-clock";
 754                         #clock-cells = <0>;
 755                         reg = <0x60d00008 0x2>; /* enable reg */
 756                         clocks = <&clk_mm_mtx_axi>;
 757                         clock-output-names = "clk_mipi_csi_ckg";
 758                 };
 759
 760                 clk_cphy_cfg_ckg: clk_cphy_cfg_ckg {
 761                         compatible = "sprd,gate-clock";
 762                         #clock-cells = <0>;
 763                         reg = <0x60d00008 0x1>; /* enable reg */
 764                         clocks = <&clk_mm_mtx_axi>;
 765                         clock-output-names = "clk_cphy_cfg_ckg";
 766                 };
 767
 768                 clk_aud: clk_aud {
 769                         compatible = "sprd,gate-clock";
 770                         #clock-cells = <0>;
 771                         reg = <0x402e0000 0x40000>;     /* enable reg */
 772                         clocks = <&ext_26m>;
 773                         clock-output-names = "clk_aud";
 774                 };
 775
 776                 clk_audif: clk_audif {
 777                         compatible = "sprd,muxed-clock";
 778                         #clock-cells = <0>;
 779                         reg = <0x402d002c 0x3 0x402e0000 0x20000>;      /* select reg and enable reg */
 780                         clocks = <&ext_26m>, <&clk_38m4>, <&clk_51m2>;
 781                         clock-output-names = "clk_audif";
 782                 };
 783
 784                 clk_vbc: clk_vbc {
 785                         compatible = "sprd,gate-clock";
 786                         #clock-cells = <0>;
 787                         reg = <0x402e0000 0x80000>;     /* enable reg */
 788                         clocks = <&ext_26m>;
 789                         clock-output-names = "clk_vbc";
 790                 };
 791
 792                 clk_fm_in: clk_fm_in {
 793                         compatible = "sprd,fixed-clock";
 794                         #clock-cells = <0>;
 795                         clock-frequency = <64000000>;
 796                         clock-output-names = "clk_fm_in";
 797                 };
 798
 799                 clk_fm: clk_fm {
 800                         compatible = "sprd,gate-clock";
 801                         #clock-cells = <0>;
 802                         reg = <0x402e0000 0x2>; /* enable reg */
 803                         clocks = <&clk_fm_in>;
 804                         clock-output-names = "clk_fm";
 805                 };
 806
 807                 clk_adi: clk_adi {
 808                         compatible = "sprd,muxed-clock";
 809                         #clock-cells = <0>;
 810                         reg = <0x402d0034 0x3 0x402e0000 0x10000>;      /* select reg and enable reg */
 811                         clocks = <&ext_26m>, <&clk_51m2>, <&clk_76m8>;
 812                         clock-output-names = "clk_adi";
 813                 };
 814
 815                 clk_aux0: clk_aux0 {
 816                         compatible = "sprd,composite-dev-clock";
 817                         #clock-cells = <0>;
 818                         reg = <0x402e0034 0x7 0x402e0034 0xf0000 0x402e0004 0x4>;       /* select reg and divider reg and enable reg */
 819                         clocks = <&ext_32k>, <&ext_26m>, <&ext_26m>, <&clk_48m>, <&clk_52m>, <&clk_51m2_w>, <&clk_37m5>, <&clk_40m_wf1>;
 820                         clock-output-names = "clk_aux0";
 821                 };
 822
 823                 clk_aux1: clk_aux1 {
 824                         compatible = "sprd,composite-dev-clock";
 825                         #clock-cells = <0>;
 826                         reg = <0x402e0034 0x70 0x402e0034 0xf00000 0x402e0004 0x8>;     /* select reg and divider reg and enable reg */
 827                         clocks = <&ext_32k>, <&ext_26m>, <&ext_26m>, <&clk_48m>, <&clk_52m>, <&clk_51m2_w>, <&clk_37m5>, <&clk_40m_wf1>;
 828                         clock-output-names = "clk_aux1";
 829                 };
 830
 831                 clk_aux2: clk_aux2 {
 832                         compatible = "sprd,composite-dev-clock";
 833                         #clock-cells = <0>;
 834                         reg = <0x402e0034 0x700 0x402e0034 0xf000000 0x402e0004 0x10>;  /* select reg and divider reg and enable reg */
 835                         clocks = <&ext_32k>, <&ext_26m>, <&ext_26m>, <&clk_48m>, <&clk_52m>, <&clk_51m2_w>, <&clk_37m5>, <&clk_40m_wf1>;
 836                         clock-output-names = "clk_aux2";
 837                 };
 838
 839                 clk_pwm0: clk_pwm0 {
 840                         compatible = "sprd,muxed-clock";
 841                         #clock-cells = <0>;
 842                         reg = <0x402d0038 0x1 0x402e0000 0x10>; /* select reg and enable reg */
 843                         clocks = <&ext_32k>, <&ext_26m>;
 844                         clock-output-names = "clk_pwm0";
 845                 };
 846
 847                 clk_pwm1: clk_pwm1 {
 848                         compatible = "sprd,muxed-clock";
 849                         #clock-cells = <0>;
 850                         reg = <0x402d003c 0x1 0x402e0000 0x20>; /* select reg and enable reg */
 851                         clocks = <&ext_32k>, <&ext_26m>;
 852                         clock-output-names = "clk_pwm1";
 853                 };
 854
 855                 clk_pwm2: clk_pwm2 {
 856                         compatible = "sprd,muxed-clock";
 857                         #clock-cells = <0>;
 858                         reg = <0x402d0040 0x1 0x402e0000 0x40>; /* select reg and enable reg */
 859                         clocks = <&ext_32k>, <&ext_26m>;
 860                         clock-output-names = "clk_pwm2";
 861                 };
 862
 863                 clk_pwm3: clk_pwm3 {
 864                         compatible = "sprd,muxed-clock";
 865                         #clock-cells = <0>;
 866                         reg = <0x402d0044 0x1 0x402e0000 0x80>; /* select reg and enable reg */
 867                         clocks = <&ext_32k>, <&ext_26m>;
 868                         clock-output-names = "clk_pwm3";
 869                 };
 870
 871                 clk_efuse: clk_efuse {
 872                         compatible = "sprd,gate-clock";
 873                         #clock-cells = <0>;
 874                         reg = <0x402e0000 0x2000>;      /* enable reg */
 875                         clocks = <&ext_26m>;
 876                         clock-output-names = "clk_efuse";
 877                 };
 878
 879                 clk_ca7_dap: clk_ca7_dap {
 880                         compatible = "sprd,muxed-clock";
 881                         #clock-cells = <0>;
 882                         reg = <0x402d0048 0x3 0x402e0000 0x40000000>;   /* select reg and enable reg */
 883                         clocks = <&ext_26m>, <&clk_76m8>, <&clk_128m>, <&clk_153m6>;
 884                         clock-output-names = "clk_ca7_dap";
 885                 };
 886
 887                 clk_ca7_ts: clk_ca7_ts {
 888                         compatible = "sprd,muxed-clock";
 889                         #clock-cells = <0>;
 890                         reg = <0x402d004c 0x3 0x402e0000 0x10000000>;   /* select reg and enable reg */
 891                         clocks = <&ext_32k>, <&ext_26m>, <&clk_128m>, <&clk_153m6>;
 892                         clock-output-names = "clk_ca7_ts";
 893                 };
 894
 895                 clk_mspi: clk_mspi {
 896                         compatible = "sprd,muxed-clock";
 897                         #clock-cells = <0>;
 898                         reg = <0x402d0050 0x3 0x402e0000 0x800000>;     /* select reg and enable reg */
 899                         clocks = <&clk_52m>, <&clk_76m8>, <&clk_96m>;
 900                         clock-output-names = "clk_mspi";
 901                 };
 902
 903                 clk_i2c: clk_i2c {
 904                         compatible = "sprd,muxed-clock";
 905                         #clock-cells = <0>;
 906                         reg = <0x402d0054 0x3 0x402e0000 0x80000000>;   /* select reg and enable reg */
 907                         clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>;
 908                         clock-output-names = "clk_i2c";
 909                 };
 910
 911                 clk_avs0: clk_avs0 {
 912                         compatible = "sprd,muxed-clock";
 913                         #clock-cells = <0>;
 914                         reg = <0x402d0058 0x3 0x402e0000 0x40>; /* select reg and enable reg */
 915                         clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>;
 916                         clock-output-names = "clk_avs0";
 917                 };
 918
 919                 clk_avs1: clk_avs1 {
 920                         compatible = "sprd,muxed-clock";
 921                         #clock-cells = <0>;
 922                         reg = <0x402d005c 0x3 0x402e0000 0x80>; /* select reg and enable reg */
 923                         clocks = <&ext_26m>, <&clk_48m>, <&clk_51m2>, <&clk_96m>;
 924                         clock-output-names = "clk_avs1";
 925                 };
 926
 927         };
 928
 929 };