2 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
46 #include "skeleton.dtsi"
47 #include <dt-bindings/dma/at91.h>
48 #include <dt-bindings/interrupt-controller/irq.h>
49 #include <dt-bindings/clock/at91.h>
52 model = "Atmel SAMA5D2 family SoC";
53 compatible = "atmel,sama5d2";
54 interrupt-parent = <&aic>;
69 compatible = "arm,cortex-a5";
71 next-level-cache = <&L2>;
76 compatible = "arm,cortex-a5-pmu";
77 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
81 compatible = "arm,coresight-etb10", "arm,primecell";
82 reg = <0x740000 0x1000>;
85 clock-names = "apb_pclk";
90 remote-endpoint = <&etm_out>;
96 compatible = "arm,coresight-etm3x", "arm,primecell";
97 reg = <0x73C000 0x1000>;
100 clock-names = "apb_pclk";
104 remote-endpoint = <&etb_in>;
110 reg = <0x20000000 0x20000000>;
114 slow_xtal: slow_xtal {
115 compatible = "fixed-clock";
117 clock-frequency = <0>;
120 main_xtal: main_xtal {
121 compatible = "fixed-clock";
123 clock-frequency = <0>;
127 ns_sram: sram@00200000 {
128 compatible = "mmio-sram";
129 reg = <0x00200000 0x20000>;
133 compatible = "simple-bus";
134 #address-cells = <1>;
138 nfc_sram: sram@00100000 {
139 compatible = "mmio-sram";
141 reg = <0x00100000 0x2400>;
144 usb0: gadget@00300000 {
145 #address-cells = <1>;
147 compatible = "atmel,sama5d3-udc";
148 reg = <0x00300000 0x100000
150 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
151 clocks = <&udphs_clk>, <&utmi>;
152 clock-names = "pclk", "hclk";
157 atmel,fifo-size = <64>;
158 atmel,nb-banks = <1>;
163 atmel,fifo-size = <1024>;
164 atmel,nb-banks = <3>;
171 atmel,fifo-size = <1024>;
172 atmel,nb-banks = <3>;
179 atmel,fifo-size = <1024>;
180 atmel,nb-banks = <2>;
187 atmel,fifo-size = <1024>;
188 atmel,nb-banks = <2>;
195 atmel,fifo-size = <1024>;
196 atmel,nb-banks = <2>;
203 atmel,fifo-size = <1024>;
204 atmel,nb-banks = <2>;
211 atmel,fifo-size = <1024>;
212 atmel,nb-banks = <2>;
219 atmel,fifo-size = <1024>;
220 atmel,nb-banks = <2>;
226 atmel,fifo-size = <1024>;
227 atmel,nb-banks = <2>;
233 atmel,fifo-size = <1024>;
234 atmel,nb-banks = <2>;
240 atmel,fifo-size = <1024>;
241 atmel,nb-banks = <2>;
247 atmel,fifo-size = <1024>;
248 atmel,nb-banks = <2>;
254 atmel,fifo-size = <1024>;
255 atmel,nb-banks = <2>;
261 atmel,fifo-size = <1024>;
262 atmel,nb-banks = <2>;
268 atmel,fifo-size = <1024>;
269 atmel,nb-banks = <2>;
274 usb1: ohci@00400000 {
275 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
276 reg = <0x00400000 0x100000>;
277 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
278 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
279 clock-names = "ohci_clk", "hclk", "uhpck";
283 usb2: ehci@00500000 {
284 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
285 reg = <0x00500000 0x100000>;
286 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
287 clocks = <&utmi>, <&uhphs_clk>;
288 clock-names = "usb_clk", "ehci_clk";
292 L2: cache-controller@00a00000 {
293 compatible = "arm,pl310-cache";
294 reg = <0x00a00000 0x1000>;
295 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
301 compatible = "atmel,sama5d3-ebi";
302 #address-cells = <2>;
305 reg = <0x10000000 0x10000000
306 0x40000000 0x30000000>;
307 ranges = <0x0 0x0 0x10000000 0x10000000
308 0x1 0x0 0x60000000 0x10000000
309 0x2 0x0 0x70000000 0x10000000
310 0x3 0x0 0x80000000 0x10000000>;
314 nand_controller: nand-controller {
315 compatible = "atmel,sama5d3-nand-controller";
316 atmel,nfc-sram = <&nfc_sram>;
317 atmel,nfc-io = <&nfc_io>;
318 ecc-engine = <&pmecc>;
319 #address-cells = <2>;
326 nand0: nand@80000000 {
327 compatible = "atmel,sama5d2-nand";
328 #address-cells = <1>;
331 reg = < /* EBI CS3 */
332 0x80000000 0x08000000
334 0xf8014070 0x00000490
335 /* SMC PMECC Error Location regs */
336 0xf8014500 0x00000200
337 /* ROM Galois tables */
338 0x00040000 0x00018000
340 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
341 atmel,nand-addr-offset = <21>;
342 atmel,nand-cmd-offset = <22>;
345 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
349 compatible = "atmel,sama5d3-nfc";
350 #address-cells = <1>;
352 reg = < /* NFC Command Registers */
353 0xc0000000 0x08000000
355 0xf8014000 0x00000070
357 0x00100000 0x00100000
359 clocks = <&hsmc_clk>;
364 sdmmc0: sdio-host@a0000000 {
365 compatible = "atmel,sama5d2-sdhci";
366 reg = <0xa0000000 0x300>;
367 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
368 clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
369 clock-names = "hclock", "multclk", "baseclk";
373 sdmmc1: sdio-host@b0000000 {
374 compatible = "atmel,sama5d2-sdhci";
375 reg = <0xb0000000 0x300>;
376 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
377 clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
378 clock-names = "hclock", "multclk", "baseclk";
382 nfc_io: nfc-io@c0000000 {
383 compatible = "atmel,sama5d3-nfc-io", "syscon";
384 reg = <0xc0000000 0x8000000>;
388 compatible = "simple-bus";
389 #address-cells = <1>;
393 hlcdc: hlcdc@f0000000 {
394 compatible = "atmel,sama5d2-hlcdc";
395 reg = <0xf0000000 0x2000>;
396 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
397 clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
398 clock-names = "periph_clk","sys_clk", "slow_clk";
401 hlcdc-display-controller {
402 compatible = "atmel,hlcdc-display-controller";
403 #address-cells = <1>;
407 #address-cells = <1>;
413 hlcdc_pwm: hlcdc-pwm {
414 compatible = "atmel,hlcdc-pwm";
419 ramc0: ramc@f000c000 {
420 compatible = "atmel,sama5d3-ddramc";
421 reg = <0xf000c000 0x200>;
422 clocks = <&ddrck>, <&mpddr_clk>;
423 clock-names = "ddrck", "mpddr";
426 dma0: dma-controller@f0010000 {
427 compatible = "atmel,sama5d4-dma";
428 reg = <0xf0010000 0x1000>;
429 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
431 clocks = <&dma0_clk>;
432 clock-names = "dma_clk";
435 /* Place dma1 here despite its address */
436 dma1: dma-controller@f0004000 {
437 compatible = "atmel,sama5d4-dma";
438 reg = <0xf0004000 0x1000>;
439 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
441 clocks = <&dma1_clk>;
442 clock-names = "dma_clk";
446 compatible = "atmel,sama5d2-pmc", "syscon";
447 reg = <0xf0014000 0x160>;
448 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
449 interrupt-controller;
450 #address-cells = <1>;
452 #interrupt-cells = <1>;
454 main_rc_osc: main_rc_osc {
455 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
457 interrupt-parent = <&pmc>;
458 interrupts = <AT91_PMC_MOSCRCS>;
459 clock-frequency = <12000000>;
460 clock-accuracy = <100000000>;
464 compatible = "atmel,at91rm9200-clk-main-osc";
466 interrupt-parent = <&pmc>;
467 interrupts = <AT91_PMC_MOSCS>;
468 clocks = <&main_xtal>;
472 compatible = "atmel,at91sam9x5-clk-main";
474 interrupt-parent = <&pmc>;
475 interrupts = <AT91_PMC_MOSCSELS>;
476 clocks = <&main_rc_osc &main_osc>;
480 compatible = "atmel,sama5d3-clk-pll";
482 interrupt-parent = <&pmc>;
483 interrupts = <AT91_PMC_LOCKA>;
486 atmel,clk-input-range = <12000000 12000000>;
487 #atmel,pll-clk-output-range-cells = <4>;
488 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
492 compatible = "atmel,at91sam9x5-clk-plldiv";
498 compatible = "atmel,at91sam9x5-clk-utmi";
500 interrupt-parent = <&pmc>;
501 interrupts = <AT91_PMC_LOCKU>;
506 compatible = "atmel,at91sam9x5-clk-master";
508 interrupt-parent = <&pmc>;
509 interrupts = <AT91_PMC_MCKRDY>;
510 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
511 atmel,clk-output-range = <124000000 166000000>;
512 atmel,clk-divisors = <1 2 4 3>;
517 compatible = "atmel,sama5d4-clk-h32mx";
522 compatible = "atmel,at91sam9x5-clk-usb";
524 clocks = <&plladiv>, <&utmi>;
528 compatible = "atmel,at91sam9x5-clk-programmable";
529 #address-cells = <1>;
531 interrupt-parent = <&pmc>;
532 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
537 interrupts = <AT91_PMC_PCKRDY(0)>;
543 interrupts = <AT91_PMC_PCKRDY(1)>;
549 interrupts = <AT91_PMC_PCKRDY(2)>;
554 compatible = "atmel,at91rm9200-clk-system";
555 #address-cells = <1>;
608 compatible = "atmel,at91sam9x5-clk-peripheral";
609 #address-cells = <1>;
613 macb0_clk: macb0_clk {
616 atmel,clk-output-range = <0 83000000>;
622 atmel,clk-output-range = <0 83000000>;
625 matrix1_clk: matrix1_clk {
638 atmel,clk-output-range = <0 83000000>;
644 atmel,clk-output-range = <0 83000000>;
650 atmel,clk-output-range = <0 83000000>;
656 atmel,clk-output-range = <0 83000000>;
662 atmel,clk-output-range = <0 83000000>;
668 atmel,clk-output-range = <0 83000000>;
671 uart0_clk: uart0_clk {
674 atmel,clk-output-range = <0 83000000>;
677 uart1_clk: uart1_clk {
680 atmel,clk-output-range = <0 83000000>;
683 uart2_clk: uart2_clk {
686 atmel,clk-output-range = <0 83000000>;
689 uart3_clk: uart3_clk {
692 atmel,clk-output-range = <0 83000000>;
695 uart4_clk: uart4_clk {
698 atmel,clk-output-range = <0 83000000>;
704 atmel,clk-output-range = <0 83000000>;
710 atmel,clk-output-range = <0 83000000>;
716 atmel,clk-output-range = <0 83000000>;
722 atmel,clk-output-range = <0 83000000>;
728 atmel,clk-output-range = <0 83000000>;
734 atmel,clk-output-range = <0 83000000>;
740 atmel,clk-output-range = <0 83000000>;
746 atmel,clk-output-range = <0 83000000>;
749 uhphs_clk: uhphs_clk {
752 atmel,clk-output-range = <0 83000000>;
755 udphs_clk: udphs_clk {
758 atmel,clk-output-range = <0 83000000>;
764 atmel,clk-output-range = <0 83000000>;
770 atmel,clk-output-range = <0 83000000>;
776 atmel,clk-output-range = <0 83000000>;
779 pdmic_clk: pdmic_clk {
782 atmel,clk-output-range = <0 83000000>;
785 securam_clk: securam_clk {
793 atmel,clk-output-range = <0 83000000>;
799 atmel,clk-output-range = <0 83000000>;
805 atmel,clk-output-range = <0 83000000>;
811 atmel,clk-output-range = <0 83000000>;
814 classd_clk: classd_clk {
817 atmel,clk-output-range = <0 83000000>;
822 compatible = "atmel,at91sam9x5-clk-peripheral";
823 #address-cells = <1>;
852 mpddr_clk: mpddr_clk {
857 matrix0_clk: matrix0_clk {
862 sdmmc0_hclk: sdmmc0_hclk {
867 sdmmc1_hclk: sdmmc1_hclk {
882 qspi0_clk: qspi0_clk {
887 qspi1_clk: qspi1_clk {
894 compatible = "atmel,sama5d2-clk-generated";
895 #address-cells = <1>;
897 interrupt-parent = <&pmc>;
898 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
900 sdmmc0_gclk: sdmmc0_gclk {
905 sdmmc1_gclk: sdmmc1_gclk {
910 tcb0_gclk: tcb0_gclk {
913 atmel,clk-output-range = <0 83000000>;
916 tcb1_gclk: tcb1_gclk {
919 atmel,clk-output-range = <0 83000000>;
925 atmel,clk-output-range = <0 83000000>;
928 pdmic_gclk: pdmic_gclk {
933 i2s0_gclk: i2s0_gclk {
938 i2s1_gclk: i2s1_gclk {
943 can0_gclk: can0_gclk {
946 atmel,clk-output-range = <0 80000000>;
949 can1_gclk: can1_gclk {
952 atmel,clk-output-range = <0 80000000>;
958 compatible = "atmel,at91sam9g46-sha";
959 reg = <0xf0028000 0x100>;
960 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
962 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
963 AT91_XDMAC_DT_PERID(30))>;
966 clock-names = "sha_clk";
971 compatible = "atmel,at91sam9g46-aes";
972 reg = <0xf002c000 0x100>;
973 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
975 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
976 AT91_XDMAC_DT_PERID(26))>,
978 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
979 AT91_XDMAC_DT_PERID(27))>;
980 dma-names = "tx", "rx";
982 clock-names = "aes_clk";
987 compatible = "atmel,at91rm9200-spi";
988 reg = <0xf8000000 0x100>;
989 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
991 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
992 AT91_XDMAC_DT_PERID(6))>,
994 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
995 AT91_XDMAC_DT_PERID(7))>;
996 dma-names = "tx", "rx";
997 clocks = <&spi0_clk>;
998 clock-names = "spi_clk";
999 atmel,fifo-size = <16>;
1000 #address-cells = <1>;
1002 status = "disabled";
1005 ssc0: ssc@f8004000 {
1006 compatible = "atmel,at91sam9g45-ssc";
1007 reg = <0xf8004000 0x4000>;
1008 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
1010 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1011 AT91_XDMAC_DT_PERID(21))>,
1013 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1014 AT91_XDMAC_DT_PERID(22))>;
1015 dma-names = "tx", "rx";
1016 clocks = <&ssc0_clk>;
1017 clock-names = "pclk";
1018 status = "disabled";
1021 macb0: ethernet@f8008000 {
1022 compatible = "atmel,sama5d2-gem";
1023 reg = <0xf8008000 0x1000>;
1024 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
1025 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
1026 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
1027 #address-cells = <1>;
1029 clocks = <&macb0_clk>, <&macb0_clk>;
1030 clock-names = "hclk", "pclk";
1031 status = "disabled";
1034 tcb0: timer@f800c000 {
1035 compatible = "atmel,at91sam9x5-tcb";
1036 reg = <0xf800c000 0x100>;
1037 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
1038 clocks = <&tcb0_clk>, <&clk32k>;
1039 clock-names = "t0_clk", "slow_clk";
1042 tcb1: timer@f8010000 {
1043 compatible = "atmel,at91sam9x5-tcb";
1044 reg = <0xf8010000 0x100>;
1045 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
1046 clocks = <&tcb1_clk>, <&clk32k>;
1047 clock-names = "t0_clk", "slow_clk";
1050 hsmc: hsmc@f8014000 {
1051 compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd";
1052 reg = <0xf8014000 0x1000>;
1053 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
1054 clocks = <&hsmc_clk>;
1055 #address-cells = <1>;
1059 pmecc: ecc-engine@ffffc070 {
1060 compatible = "atmel,sama5d2-pmecc";
1061 reg = <0xffffc070 0x490>,
1066 pdmic: pdmic@f8018000 {
1067 compatible = "atmel,sama5d2-pdmic";
1068 reg = <0xf8018000 0x124>;
1069 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
1071 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1072 | AT91_XDMAC_DT_PERID(50))>;
1074 clocks = <&pdmic_clk>, <&pdmic_gclk>;
1075 clock-names = "pclk", "gclk";
1076 status = "disabled";
1079 uart0: serial@f801c000 {
1080 compatible = "atmel,at91sam9260-usart";
1081 reg = <0xf801c000 0x100>;
1082 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
1084 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1085 AT91_XDMAC_DT_PERID(35))>,
1087 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1088 AT91_XDMAC_DT_PERID(36))>;
1089 dma-names = "tx", "rx";
1090 clocks = <&uart0_clk>;
1091 clock-names = "usart";
1092 status = "disabled";
1095 uart1: serial@f8020000 {
1096 compatible = "atmel,at91sam9260-usart";
1097 reg = <0xf8020000 0x100>;
1098 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
1100 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1101 AT91_XDMAC_DT_PERID(37))>,
1103 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1104 AT91_XDMAC_DT_PERID(38))>;
1105 dma-names = "tx", "rx";
1106 clocks = <&uart1_clk>;
1107 clock-names = "usart";
1108 status = "disabled";
1111 uart2: serial@f8024000 {
1112 compatible = "atmel,at91sam9260-usart";
1113 reg = <0xf8024000 0x100>;
1114 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
1116 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1117 AT91_XDMAC_DT_PERID(39))>,
1119 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1120 AT91_XDMAC_DT_PERID(40))>;
1121 dma-names = "tx", "rx";
1122 clocks = <&uart2_clk>;
1123 clock-names = "usart";
1124 status = "disabled";
1127 i2c0: i2c@f8028000 {
1128 compatible = "atmel,sama5d2-i2c";
1129 reg = <0xf8028000 0x100>;
1130 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
1132 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1133 AT91_XDMAC_DT_PERID(0))>,
1135 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1136 AT91_XDMAC_DT_PERID(1))>;
1137 dma-names = "tx", "rx";
1138 #address-cells = <1>;
1140 clocks = <&twi0_clk>;
1141 atmel,fifo-size = <16>;
1142 status = "disabled";
1146 compatible = "atmel,sama5d2-sfr", "syscon";
1147 reg = <0xf8030000 0x98>;
1150 flx0: flexcom@f8034000 {
1151 compatible = "atmel,sama5d2-flexcom";
1152 reg = <0xf8034000 0x200>;
1153 clocks = <&flx0_clk>;
1154 #address-cells = <1>;
1156 ranges = <0x0 0xf8034000 0x800>;
1157 status = "disabled";
1160 flx1: flexcom@f8038000 {
1161 compatible = "atmel,sama5d2-flexcom";
1162 reg = <0xf8038000 0x200>;
1163 clocks = <&flx1_clk>;
1164 #address-cells = <1>;
1166 ranges = <0x0 0xf8038000 0x800>;
1167 status = "disabled";
1170 securam: sram@f8044000 {
1171 compatible = "atmel,sama5d2-securam", "mmio-sram";
1172 reg = <0xf8044000 0x1420>;
1173 clocks = <&securam_clk>;
1174 #address-cells = <1>;
1176 ranges = <0 0xf8044000 0x1420>;
1180 compatible = "atmel,sama5d3-rstc";
1181 reg = <0xf8048000 0x10>;
1186 compatible = "atmel,sama5d2-shdwc";
1187 reg = <0xf8048010 0x10>;
1189 #address-cells = <1>;
1191 atmel,wakeup-rtc-timer;
1194 pit: timer@f8048030 {
1195 compatible = "atmel,at91sam9260-pit";
1196 reg = <0xf8048030 0x10>;
1197 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1202 compatible = "atmel,sama5d4-wdt";
1203 reg = <0xf8048040 0x10>;
1204 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1206 status = "disabled";
1209 clk32k: sckc@f8048050 {
1210 compatible = "atmel,sama5d4-sckc";
1211 reg = <0xf8048050 0x4>;
1213 clocks = <&slow_xtal>;
1218 compatible = "atmel,at91rm9200-rtc";
1219 reg = <0xf80480b0 0x30>;
1220 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
1224 can0: can@f8054000 {
1225 compatible = "bosch,m_can";
1226 reg = <0xf8054000 0x4000>, <0x210000 0x4000>;
1227 reg-names = "m_can", "message_ram";
1228 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>,
1229 <64 IRQ_TYPE_LEVEL_HIGH 7>;
1230 interrupt-names = "int0", "int1";
1231 clocks = <&can0_clk>, <&can0_gclk>;
1232 clock-names = "hclk", "cclk";
1233 assigned-clocks = <&can0_gclk>;
1234 assigned-clock-parents = <&utmi>;
1235 assigned-clock-rates = <40000000>;
1236 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
1237 status = "disabled";
1240 spi1: spi@fc000000 {
1241 compatible = "atmel,at91rm9200-spi";
1242 reg = <0xfc000000 0x100>;
1243 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
1245 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1246 AT91_XDMAC_DT_PERID(8))>,
1248 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1249 AT91_XDMAC_DT_PERID(9))>;
1250 dma-names = "tx", "rx";
1251 clocks = <&spi1_clk>;
1252 clock-names = "spi_clk";
1253 atmel,fifo-size = <16>;
1254 #address-cells = <1>;
1256 status = "disabled";
1259 uart3: serial@fc008000 {
1260 compatible = "atmel,at91sam9260-usart";
1261 reg = <0xfc008000 0x100>;
1262 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
1264 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1265 AT91_XDMAC_DT_PERID(41))>,
1267 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1268 AT91_XDMAC_DT_PERID(42))>;
1269 dma-names = "tx", "rx";
1270 clocks = <&uart3_clk>;
1271 clock-names = "usart";
1272 status = "disabled";
1275 uart4: serial@fc00c000 {
1276 compatible = "atmel,at91sam9260-usart";
1277 reg = <0xfc00c000 0x100>;
1279 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1280 AT91_XDMAC_DT_PERID(43))>,
1282 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1283 AT91_XDMAC_DT_PERID(44))>;
1284 dma-names = "tx", "rx";
1285 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
1286 clocks = <&uart4_clk>;
1287 clock-names = "usart";
1288 status = "disabled";
1291 flx2: flexcom@fc010000 {
1292 compatible = "atmel,sama5d2-flexcom";
1293 reg = <0xfc010000 0x200>;
1294 clocks = <&flx2_clk>;
1295 #address-cells = <1>;
1297 ranges = <0x0 0xfc010000 0x800>;
1298 status = "disabled";
1301 flx3: flexcom@fc014000 {
1302 compatible = "atmel,sama5d2-flexcom";
1303 reg = <0xfc014000 0x200>;
1304 clocks = <&flx3_clk>;
1305 #address-cells = <1>;
1307 ranges = <0x0 0xfc014000 0x800>;
1308 status = "disabled";
1311 flx4: flexcom@fc018000 {
1312 compatible = "atmel,sama5d2-flexcom";
1313 reg = <0xfc018000 0x200>;
1314 clocks = <&flx4_clk>;
1315 #address-cells = <1>;
1317 ranges = <0x0 0xfc018000 0x800>;
1318 status = "disabled";
1322 compatible = "atmel,at91sam9g45-trng";
1323 reg = <0xfc01c000 0x100>;
1324 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
1325 clocks = <&trng_clk>;
1328 aic: interrupt-controller@fc020000 {
1329 #interrupt-cells = <3>;
1330 compatible = "atmel,sama5d2-aic";
1331 interrupt-controller;
1332 reg = <0xfc020000 0x200>;
1333 atmel,external-irqs = <49>;
1336 i2c1: i2c@fc028000 {
1337 compatible = "atmel,sama5d2-i2c";
1338 reg = <0xfc028000 0x100>;
1339 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
1341 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1342 AT91_XDMAC_DT_PERID(2))>,
1344 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1345 AT91_XDMAC_DT_PERID(3))>;
1346 dma-names = "tx", "rx";
1347 #address-cells = <1>;
1349 clocks = <&twi1_clk>;
1350 atmel,fifo-size = <16>;
1351 status = "disabled";
1355 compatible = "atmel,sama5d2-adc";
1356 reg = <0xfc030000 0x100>;
1357 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
1358 clocks = <&adc_clk>;
1359 clock-names = "adc_clk";
1360 atmel,min-sample-rate-hz = <200000>;
1361 atmel,max-sample-rate-hz = <20000000>;
1362 atmel,startup-time-ms = <4>;
1363 status = "disabled";
1366 pioA: pinctrl@fc038000 {
1367 compatible = "atmel,sama5d2-pinctrl";
1368 reg = <0xfc038000 0x600>;
1369 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
1370 <68 IRQ_TYPE_LEVEL_HIGH 7>,
1371 <69 IRQ_TYPE_LEVEL_HIGH 7>,
1372 <70 IRQ_TYPE_LEVEL_HIGH 7>;
1373 interrupt-controller;
1374 #interrupt-cells = <2>;
1377 clocks = <&pioA_clk>;
1381 compatible = "atmel,sama5d2-secumod", "syscon";
1382 reg = <0xfc040000 0x100>;
1386 compatible = "atmel,at91sam9g46-tdes";
1387 reg = <0xfc044000 0x100>;
1388 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1390 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1391 AT91_XDMAC_DT_PERID(28))>,
1393 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1394 AT91_XDMAC_DT_PERID(29))>;
1395 dma-names = "tx", "rx";
1396 clocks = <&tdes_clk>;
1397 clock-names = "tdes_clk";
1401 can1: can@fc050000 {
1402 compatible = "bosch,m_can";
1403 reg = <0xfc050000 0x4000>, <0x210000 0x4000>;
1404 reg-names = "m_can", "message_ram";
1405 interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>,
1406 <65 IRQ_TYPE_LEVEL_HIGH 7>;
1407 interrupt-names = "int0", "int1";
1408 clocks = <&can1_clk>, <&can1_gclk>;
1409 clock-names = "hclk", "cclk";
1410 assigned-clocks = <&can1_gclk>;
1411 assigned-clock-parents = <&utmi>;
1412 assigned-clock-rates = <40000000>;
1413 bosch,mram-cfg = <0x1100 0 0 64 0 0 32 32>;
1414 status = "disabled";
1417 sfrbu: sfr@fc05c000 {
1418 compatible = "atmel,sama5d2-sfrbu", "syscon";
1419 reg = <0xfc05c000 0x20>;
1423 compatible = "atmel,sama5d2-chipid";
1424 reg = <0xfc069000 0x8>;