arch/arm/boot/dts/rockchip/rk3128.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <dt-bindings/clock/rk3128-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11
  12 / {
  13         compatible = "rockchip,rk3128";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         arm-pmu {
  19                 compatible = "arm,cortex-a7-pmu";
  20                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  21                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
  22                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
  23                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  24                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  25         };
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 cpu0: cpu@f00 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a7";
  34                         reg = <0xf00>;
  35                         clock-latency = <40000>;
  36                         clocks = <&cru ARMCLK>;
  37                         operating-points = <
  38                                 /* KHz    uV */
  39                                  816000 1000000
  40                         >;
  41                         #cooling-cells = <2>; /* min followed by max */
  42                 };
  43
  44                 cpu1: cpu@f01 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a7";
  47                         reg = <0xf01>;
  48                 };
  49
  50                 cpu2: cpu@f02 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a7";
  53                         reg = <0xf02>;
  54                 };
  55
  56                 cpu3: cpu@f03 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a7";
  59                         reg = <0xf03>;
  60                 };
  61         };
  62
  63         timer {
  64                 compatible = "arm,armv7-timer";
  65                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  66                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  67                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  68                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  69                 arm,cpu-registers-not-fw-configured;
  70                 clock-frequency = <24000000>;
  71         };
  72
  73         xin24m: oscillator {
  74                 compatible = "fixed-clock";
  75                 clock-frequency = <24000000>;
  76                 clock-output-names = "xin24m";
  77                 #clock-cells = <0>;
  78         };
  79
  80         pmu: syscon@100a0000 {
  81                 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
  82                 reg = <0x100a0000 0x1000>;
  83         };
  84
  85         gic: interrupt-controller@10139000 {
  86                 compatible = "arm,cortex-a7-gic";
  87                 reg = <0x10139000 0x1000>,
  88                       <0x1013a000 0x1000>,
  89                       <0x1013c000 0x2000>,
  90                       <0x1013e000 0x2000>;
  91                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  92                 interrupt-controller;
  93                 #interrupt-cells = <3>;
  94                 #address-cells = <0>;
  95         };
  96
  97         usb_otg: usb@10180000 {
  98                 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2";
  99                 reg = <0x10180000 0x40000>;
 100                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 101                 clocks = <&cru HCLK_OTG>;
 102                 clock-names = "otg";
 103                 dr_mode = "otg";
 104                 phys = <&usb2phy_otg>;
 105                 phy-names = "usb2-phy";
 106                 status = "disabled";
 107         };
 108
 109         usb_host_ehci: usb@101c0000 {
 110                 compatible = "generic-ehci";
 111                 reg = <0x101c0000 0x20000>;
 112                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 113                 phys = <&usb2phy_host>;
 114                 phy-names = "usb";
 115                 status = "disabled";
 116         };
 117
 118         usb_host_ohci: usb@101e0000 {
 119                 compatible = "generic-ohci";
 120                 reg = <0x101e0000 0x20000>;
 121                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 122                 phys = <&usb2phy_host>;
 123                 phy-names = "usb";
 124                 status = "disabled";
 125         };
 126
 127         sdmmc: mmc@10214000 {
 128                 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
 129                 reg = <0x10214000 0x4000>;
 130                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 131                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 132                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 133                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 134                 dmas = <&pdma 10>;
 135                 dma-names = "rx-tx";
 136                 fifo-depth = <256>;
 137                 max-frequency = <150000000>;
 138                 resets = <&cru SRST_SDMMC>;
 139                 reset-names = "reset";
 140                 status = "disabled";
 141         };
 142
 143         sdio: mmc@10218000 {
 144                 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
 145                 reg = <0x10218000 0x4000>;
 146                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 147                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 148                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 149                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 150                 dmas = <&pdma 11>;
 151                 dma-names = "rx-tx";
 152                 fifo-depth = <256>;
 153                 max-frequency = <150000000>;
 154                 resets = <&cru SRST_SDIO>;
 155                 reset-names = "reset";
 156                 status = "disabled";
 157         };
 158
 159         emmc: mmc@1021c000 {
 160                 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
 161                 reg = <0x1021c000 0x4000>;
 162                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 163                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 164                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 165                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 166                 dmas = <&pdma 12>;
 167                 dma-names = "rx-tx";
 168                 fifo-depth = <256>;
 169                 max-frequency = <150000000>;
 170                 resets = <&cru SRST_EMMC>;
 171                 reset-names = "reset";
 172                 status = "disabled";
 173         };
 174
 175         nfc: nand-controller@10500000 {
 176                 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc";
 177                 reg = <0x10500000 0x4000>;
 178                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 179                 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
 180                 clock-names = "ahb", "nfc";
 181                 pinctrl-names = "default";
 182                 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
 183                              &flash_dqs &flash_rdn &flash_rdy &flash_wrn>;
 184                 status = "disabled";
 185         };
 186
 187         cru: clock-controller@20000000 {
 188                 compatible = "rockchip,rk3128-cru";
 189                 reg = <0x20000000 0x1000>;
 190                 clocks = <&xin24m>;
 191                 clock-names = "xin24m";
 192                 rockchip,grf = <&grf>;
 193                 #clock-cells = <1>;
 194                 #reset-cells = <1>;
 195                 assigned-clocks = <&cru PLL_GPLL>;
 196                 assigned-clock-rates = <594000000>;
 197         };
 198
 199         grf: syscon@20008000 {
 200                 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd";
 201                 reg = <0x20008000 0x1000>;
 202                 #address-cells = <1>;
 203                 #size-cells = <1>;
 204
 205                 usb2phy: usb2phy@17c {
 206                         compatible = "rockchip,rk3128-usb2phy";
 207                         reg = <0x017c 0x0c>;
 208                         clocks = <&cru SCLK_OTGPHY0>;
 209                         clock-names = "phyclk";
 210                         clock-output-names = "usb480m_phy";
 211                         #clock-cells = <0>;
 212                         status = "disabled";
 213
 214                         usb2phy_host: host-port {
 215                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 216                                 interrupt-names = "linestate";
 217                                 #phy-cells = <0>;
 218                                 status = "disabled";
 219                         };
 220
 221                         usb2phy_otg: otg-port {
 222                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 223                                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 224                                              <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 225                                 interrupt-names = "otg-bvalid", "otg-id",
 226                                                   "linestate";
 227                                 #phy-cells = <0>;
 228                                 status = "disabled";
 229                         };
 230                 };
 231         };
 232
 233         timer0: timer@20044000 {
 234                 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
 235                 reg = <0x20044000 0x20>;
 236                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 237                 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
 238                 clock-names = "pclk", "timer";
 239         };
 240
 241         timer1: timer@20044020 {
 242                 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
 243                 reg = <0x20044020 0x20>;
 244                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 245                 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>;
 246                 clock-names = "pclk", "timer";
 247         };
 248
 249         timer2: timer@20044040 {
 250                 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
 251                 reg = <0x20044040 0x20>;
 252                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 253                 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>;
 254                 clock-names = "pclk", "timer";
 255         };
 256
 257         timer3: timer@20044060 {
 258                 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
 259                 reg = <0x20044060 0x20>;
 260                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 261                 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>;
 262                 clock-names = "pclk", "timer";
 263         };
 264
 265         timer4: timer@20044080 {
 266                 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
 267                 reg = <0x20044080 0x20>;
 268                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 269                 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>;
 270                 clock-names = "pclk", "timer";
 271         };
 272
 273         timer5: timer@200440a0 {
 274                 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
 275                 reg = <0x200440a0 0x20>;
 276                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 277                 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>;
 278                 clock-names = "pclk", "timer";
 279         };
 280
 281         watchdog: watchdog@2004c000 {
 282                 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt";
 283                 reg = <0x2004c000 0x100>;
 284                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 285                 clocks = <&cru PCLK_WDT>;
 286                 status = "disabled";
 287         };
 288
 289         pwm0: pwm@20050000 {
 290                 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
 291                 reg = <0x20050000 0x10>;
 292                 clocks = <&cru PCLK_PWM>;
 293                 pinctrl-names = "default";
 294                 pinctrl-0 = <&pwm0_pin>;
 295                 #pwm-cells = <3>;
 296                 status = "disabled";
 297         };
 298
 299         pwm1: pwm@20050010 {
 300                 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
 301                 reg = <0x20050010 0x10>;
 302                 clocks = <&cru PCLK_PWM>;
 303                 pinctrl-names = "default";
 304                 pinctrl-0 = <&pwm1_pin>;
 305                 #pwm-cells = <3>;
 306                 status = "disabled";
 307         };
 308
 309         pwm2: pwm@20050020 {
 310                 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
 311                 reg = <0x20050020 0x10>;
 312                 clocks = <&cru PCLK_PWM>;
 313                 pinctrl-names = "default";
 314                 pinctrl-0 = <&pwm2_pin>;
 315                 #pwm-cells = <3>;
 316                 status = "disabled";
 317         };
 318
 319         pwm3: pwm@20050030 {
 320                 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
 321                 reg = <0x20050030 0x10>;
 322                 clocks = <&cru PCLK_PWM>;
 323                 pinctrl-names = "default";
 324                 pinctrl-0 = <&pwm3_pin>;
 325                 #pwm-cells = <3>;
 326                 status = "disabled";
 327         };
 328
 329         i2c1: i2c@20056000 {
 330                 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
 331                 reg = <0x20056000 0x1000>;
 332                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 333                 clock-names = "i2c";
 334                 clocks = <&cru PCLK_I2C1>;
 335                 pinctrl-names = "default";
 336                 pinctrl-0 = <&i2c1_xfer>;
 337                 #address-cells = <1>;
 338                 #size-cells = <0>;
 339                 status = "disabled";
 340         };
 341
 342         i2c2: i2c@2005a000 {
 343                 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
 344                 reg = <0x2005a000 0x1000>;
 345                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 346                 clock-names = "i2c";
 347                 clocks = <&cru PCLK_I2C2>;
 348                 pinctrl-names = "default";
 349                 pinctrl-0 = <&i2c2_xfer>;
 350                 #address-cells = <1>;
 351                 #size-cells = <0>;
 352                 status = "disabled";
 353         };
 354
 355         i2c3: i2c@2005e000 {
 356                 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
 357                 reg = <0x2005e000 0x1000>;
 358                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 359                 clock-names = "i2c";
 360                 clocks = <&cru PCLK_I2C3>;
 361                 pinctrl-names = "default";
 362                 pinctrl-0 = <&i2c3_xfer>;
 363                 #address-cells = <1>;
 364                 #size-cells = <0>;
 365                 status = "disabled";
 366         };
 367
 368         uart0: serial@20060000 {
 369                 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
 370                 reg = <0x20060000 0x100>;
 371                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 372                 clock-frequency = <24000000>;
 373                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 374                 clock-names = "baudclk", "apb_pclk";
 375                 dmas = <&pdma 2>, <&pdma 3>;
 376                 dma-names = "tx", "rx";
 377                 pinctrl-names = "default";
 378                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 379                 reg-io-width = <4>;
 380                 reg-shift = <2>;
 381                 status = "disabled";
 382         };
 383
 384         uart1: serial@20064000 {
 385                 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
 386                 reg = <0x20064000 0x100>;
 387                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 388                 clock-frequency = <24000000>;
 389                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 390                 clock-names = "baudclk", "apb_pclk";
 391                 dmas = <&pdma 4>, <&pdma 5>;
 392                 dma-names = "tx", "rx";
 393                 pinctrl-names = "default";
 394                 pinctrl-0 = <&uart1_xfer>;
 395                 reg-io-width = <4>;
 396                 reg-shift = <2>;
 397                 status = "disabled";
 398         };
 399
 400         uart2: serial@20068000 {
 401                 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
 402                 reg = <0x20068000 0x100>;
 403                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 404                 clock-frequency = <24000000>;
 405                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 406                 clock-names = "baudclk", "apb_pclk";
 407                 dmas = <&pdma 6>, <&pdma 7>;
 408                 dma-names = "tx", "rx";
 409                 pinctrl-names = "default";
 410                 pinctrl-0 = <&uart2_xfer>;
 411                 reg-io-width = <4>;
 412                 reg-shift = <2>;
 413                 status = "disabled";
 414         };
 415
 416         saradc: saradc@2006c000 {
 417                 compatible = "rockchip,saradc";
 418                 reg = <0x2006c000 0x100>;
 419                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 420                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 421                 clock-names = "saradc", "apb_pclk";
 422                 resets = <&cru SRST_SARADC>;
 423                 reset-names = "saradc-apb";
 424                 #io-channel-cells = <1>;
 425                 status = "disabled";
 426         };
 427
 428         i2c0: i2c@20072000 {
 429                 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
 430                 reg = <0x20072000 0x1000>;
 431                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 432                 clock-names = "i2c";
 433                 clocks = <&cru PCLK_I2C0>;
 434                 pinctrl-names = "default";
 435                 pinctrl-0 = <&i2c0_xfer>;
 436                 #address-cells = <1>;
 437                 #size-cells = <0>;
 438                 status = "disabled";
 439         };
 440
 441         spi0: spi@20074000 {
 442                 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi";
 443                 reg = <0x20074000 0x1000>;
 444                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 445                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 446                 clock-names = "spiclk", "apb_pclk";
 447                 dmas = <&pdma 8>, <&pdma 9>;
 448                 dma-names = "tx", "rx";
 449                 pinctrl-names = "default";
 450                 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>;
 451                 #address-cells = <1>;
 452                 #size-cells = <0>;
 453                 status = "disabled";
 454         };
 455
 456         pdma: dma-controller@20078000 {
 457                 compatible = "arm,pl330", "arm,primecell";
 458                 reg = <0x20078000 0x4000>;
 459                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 460                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 461                 arm,pl330-broken-no-flushp;
 462                 arm,pl330-periph-burst;
 463                 clocks = <&cru ACLK_DMAC>;
 464                 clock-names = "apb_pclk";
 465                 #dma-cells = <1>;
 466         };
 467
 468         pinctrl: pinctrl {
 469                 compatible = "rockchip,rk3128-pinctrl";
 470                 rockchip,grf = <&grf>;
 471                 #address-cells = <1>;
 472                 #size-cells = <1>;
 473                 ranges;
 474
 475                 gpio0: gpio@2007c000 {
 476                         compatible = "rockchip,gpio-bank";
 477                         reg = <0x2007c000 0x100>;
 478                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 479                         clocks = <&cru PCLK_GPIO0>;
 480                         gpio-controller;
 481                         #gpio-cells = <2>;
 482                         interrupt-controller;
 483                         #interrupt-cells = <2>;
 484                 };
 485
 486                 gpio1: gpio@20080000 {
 487                         compatible = "rockchip,gpio-bank";
 488                         reg = <0x20080000 0x100>;
 489                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 490                         clocks = <&cru PCLK_GPIO1>;
 491                         gpio-controller;
 492                         #gpio-cells = <2>;
 493                         interrupt-controller;
 494                         #interrupt-cells = <2>;
 495                 };
 496
 497                 gpio2: gpio@20084000 {
 498                         compatible = "rockchip,gpio-bank";
 499                         reg = <0x20084000 0x100>;
 500                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 501                         clocks = <&cru PCLK_GPIO2>;
 502                         gpio-controller;
 503                         #gpio-cells = <2>;
 504                         interrupt-controller;
 505                         #interrupt-cells = <2>;
 506                 };
 507
 508                 gpio3: gpio@20088000 {
 509                         compatible = "rockchip,gpio-bank";
 510                         reg = <0x20088000 0x100>;
 511                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 512                         clocks = <&cru PCLK_GPIO3>;
 513                         gpio-controller;
 514                         #gpio-cells = <2>;
 515                         interrupt-controller;
 516                         #interrupt-cells = <2>;
 517                 };
 518
 519                 pcfg_pull_default: pcfg-pull-default {
 520                         bias-pull-pin-default;
 521                 };
 522
 523                 pcfg_pull_none: pcfg-pull-none {
 524                         bias-disable;
 525                 };
 526
 527                 emmc {
 528                         emmc_clk: emmc-clk {
 529                                 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
 530                         };
 531
 532                         emmc_cmd: emmc-cmd {
 533                                 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>;
 534                         };
 535
 536                         emmc_cmd1: emmc-cmd1 {
 537                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>;
 538                         };
 539
 540                         emmc_pwr: emmc-pwr {
 541                                 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>;
 542                         };
 543
 544                         emmc_bus1: emmc-bus1 {
 545                                 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>;
 546                         };
 547
 548                         emmc_bus4: emmc-bus4 {
 549                                 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
 550                                                 <1 RK_PD1 2 &pcfg_pull_default>,
 551                                                 <1 RK_PD2 2 &pcfg_pull_default>,
 552                                                 <1 RK_PD3 2 &pcfg_pull_default>;
 553                         };
 554
 555                         emmc_bus8: emmc-bus8 {
 556                                 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
 557                                                 <1 RK_PD1 2 &pcfg_pull_default>,
 558                                                 <1 RK_PD2 2 &pcfg_pull_default>,
 559                                                 <1 RK_PD3 2 &pcfg_pull_default>,
 560                                                 <1 RK_PD4 2 &pcfg_pull_default>,
 561                                                 <1 RK_PD5 2 &pcfg_pull_default>,
 562                                                 <1 RK_PD6 2 &pcfg_pull_default>,
 563                                                 <1 RK_PD7 2 &pcfg_pull_default>;
 564                         };
 565                 };
 566
 567                 gmac {
 568                         rgmii_pins: rgmii-pins {
 569                                 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
 570                                                 <2 RK_PB1 3 &pcfg_pull_default>,
 571                                                 <2 RK_PB3 3 &pcfg_pull_default>,
 572                                                 <2 RK_PB4 3 &pcfg_pull_default>,
 573                                                 <2 RK_PB5 3 &pcfg_pull_default>,
 574                                                 <2 RK_PB6 3 &pcfg_pull_default>,
 575                                                 <2 RK_PC0 3 &pcfg_pull_default>,
 576                                                 <2 RK_PC1 3 &pcfg_pull_default>,
 577                                                 <2 RK_PC2 3 &pcfg_pull_default>,
 578                                                 <2 RK_PC3 3 &pcfg_pull_default>,
 579                                                 <2 RK_PD1 3 &pcfg_pull_default>,
 580                                                 <2 RK_PC4 4 &pcfg_pull_default>,
 581                                                 <2 RK_PC5 4 &pcfg_pull_default>,
 582                                                 <2 RK_PC6 4 &pcfg_pull_default>,
 583                                                 <2 RK_PC7 4 &pcfg_pull_default>;
 584                         };
 585
 586                         rmii_pins: rmii-pins {
 587                                 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
 588                                                 <2 RK_PB4 3 &pcfg_pull_default>,
 589                                                 <2 RK_PB5 3 &pcfg_pull_default>,
 590                                                 <2 RK_PB6 3 &pcfg_pull_default>,
 591                                                 <2 RK_PB7 3 &pcfg_pull_default>,
 592                                                 <2 RK_PC0 3 &pcfg_pull_default>,
 593                                                 <2 RK_PC1 3 &pcfg_pull_default>,
 594                                                 <2 RK_PC2 3 &pcfg_pull_default>,
 595                                                 <2 RK_PC3 3 &pcfg_pull_default>,
 596                                                 <2 RK_PD1 3 &pcfg_pull_default>;
 597                         };
 598                 };
 599
 600                 hdmi {
 601                         hdmii2c_xfer: hdmii2c-xfer {
 602                                 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
 603                                                 <0 RK_PA7 2 &pcfg_pull_none>;
 604                         };
 605
 606                         hdmi_hpd: hdmi-hpd {
 607                                 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
 608                         };
 609
 610                         hdmi_cec: hdmi-cec {
 611                                 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
 612                         };
 613                 };
 614
 615                 i2c0 {
 616                         i2c0_xfer: i2c0-xfer {
 617                                 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
 618                                                 <0 RK_PA1 1 &pcfg_pull_none>;
 619                         };
 620                 };
 621
 622                 i2c1 {
 623                         i2c1_xfer: i2c1-xfer {
 624                                 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
 625                                                 <0 RK_PA3 1 &pcfg_pull_none>;
 626                         };
 627                 };
 628
 629                 i2c2 {
 630                         i2c2_xfer: i2c2-xfer {
 631                                 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,
 632                                                 <2 RK_PC5 3 &pcfg_pull_none>;
 633                         };
 634                 };
 635
 636                 i2c3 {
 637                         i2c3_xfer: i2c3-xfer {
 638                                 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
 639                                                 <0 RK_PA7 1 &pcfg_pull_none>;
 640                         };
 641                 };
 642
 643                 i2s {
 644                         i2s_bus: i2s-bus {
 645                                 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
 646                                                 <0 RK_PB1 1 &pcfg_pull_none>,
 647                                                 <0 RK_PB3 1 &pcfg_pull_none>,
 648                                                 <0 RK_PB4 1 &pcfg_pull_none>,
 649                                                 <0 RK_PB5 1 &pcfg_pull_none>,
 650                                                 <0 RK_PB6 1 &pcfg_pull_none>;
 651                         };
 652
 653                         i2s1_bus: i2s1-bus {
 654                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>,
 655                                                 <1 RK_PA1 1 &pcfg_pull_none>,
 656                                                 <1 RK_PA2 1 &pcfg_pull_none>,
 657                                                 <1 RK_PA3 1 &pcfg_pull_none>,
 658                                                 <1 RK_PA4 1 &pcfg_pull_none>,
 659                                                 <1 RK_PA5 1 &pcfg_pull_none>;
 660                         };
 661                 };
 662
 663                 lcdc {
 664                         lcdc_dclk: lcdc-dclk {
 665                                 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>;
 666                         };
 667
 668                         lcdc_den: lcdc-den {
 669                                 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>;
 670                         };
 671
 672                         lcdc_hsync: lcdc-hsync {
 673                                 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
 674                         };
 675
 676                         lcdc_vsync: lcdc-vsync {
 677                                 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>;
 678                         };
 679
 680                         lcdc_rgb24: lcdc-rgb24 {
 681                                 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
 682                                                 <2 RK_PB5 1 &pcfg_pull_none>,
 683                                                 <2 RK_PB6 1 &pcfg_pull_none>,
 684                                                 <2 RK_PB7 1 &pcfg_pull_none>,
 685                                                 <2 RK_PC0 1 &pcfg_pull_none>,
 686                                                 <2 RK_PC1 1 &pcfg_pull_none>,
 687                                                 <2 RK_PC2 1 &pcfg_pull_none>,
 688                                                 <2 RK_PC3 1 &pcfg_pull_none>,
 689                                                 <2 RK_PC4 1 &pcfg_pull_none>,
 690                                                 <2 RK_PC5 1 &pcfg_pull_none>,
 691                                                 <2 RK_PC6 1 &pcfg_pull_none>,
 692                                                 <2 RK_PC7 1 &pcfg_pull_none>,
 693                                                 <2 RK_PD0 1 &pcfg_pull_none>,
 694                                                 <2 RK_PD1 1 &pcfg_pull_none>;
 695                         };
 696                 };
 697
 698                 nfc {
 699                         flash_ale: flash-ale {
 700                                 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>;
 701                         };
 702
 703                         flash_cle: flash-cle {
 704                                 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>;
 705                         };
 706
 707                         flash_wrn: flash-wrn {
 708                                 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
 709                         };
 710
 711                         flash_rdn: flash-rdn {
 712                                 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>;
 713                         };
 714
 715                         flash_rdy: flash-rdy {
 716                                 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
 717                         };
 718
 719                         flash_cs0: flash-cs0 {
 720                                 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
 721                         };
 722
 723                         flash_dqs: flash-dqs {
 724                                 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>;
 725                         };
 726
 727                         flash_bus8: flash-bus8 {
 728                                 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
 729                                                 <1 RK_PD1 1 &pcfg_pull_none>,
 730                                                 <1 RK_PD2 1 &pcfg_pull_none>,
 731                                                 <1 RK_PD3 1 &pcfg_pull_none>,
 732                                                 <1 RK_PD4 1 &pcfg_pull_none>,
 733                                                 <1 RK_PD5 1 &pcfg_pull_none>,
 734                                                 <1 RK_PD6 1 &pcfg_pull_none>,
 735                                                 <1 RK_PD7 1 &pcfg_pull_none>;
 736                         };
 737                 };
 738
 739                 pwm0 {
 740                         pwm0_pin: pwm0-pin {
 741                                 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>;
 742                         };
 743                 };
 744
 745                 pwm1 {
 746                         pwm1_pin: pwm1-pin {
 747                                 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
 748                         };
 749                 };
 750
 751                 pwm2 {
 752                         pwm2_pin: pwm2-pin {
 753                                 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
 754                         };
 755                 };
 756
 757                 pwm3 {
 758                         pwm3_pin: pwm3-pin {
 759                                 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>;
 760                         };
 761                 };
 762
 763                 sdio {
 764                         sdio_clk: sdio-clk {
 765                                 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>;
 766                         };
 767
 768                         sdio_cmd: sdio-cmd {
 769                                 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>;
 770                         };
 771
 772                         sdio_pwren: sdio-pwren {
 773                                 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>;
 774                         };
 775
 776                         sdio_bus4: sdio-bus4 {
 777                                 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>,
 778                                                 <1 RK_PA2 2 &pcfg_pull_default>,
 779                                                 <1 RK_PA4 2 &pcfg_pull_default>,
 780                                                 <1 RK_PA5 2 &pcfg_pull_default>;
 781                         };
 782                 };
 783
 784                 sdmmc {
 785                         sdmmc_clk: sdmmc-clk {
 786                                 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
 787                         };
 788
 789                         sdmmc_cmd: sdmmc-cmd {
 790                                 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
 791                         };
 792
 793                         sdmmc_wp: sdmmc-wp {
 794                                 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
 795                         };
 796
 797                         sdmmc_pwren: sdmmc-pwren {
 798                                 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>;
 799                         };
 800
 801                         sdmmc_bus4: sdmmc-bus4 {
 802                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
 803                                                 <1 RK_PC3 1 &pcfg_pull_default>,
 804                                                 <1 RK_PC4 1 &pcfg_pull_default>,
 805                                                 <1 RK_PC5 1 &pcfg_pull_default>;
 806                         };
 807                 };
 808
 809                 spdif {
 810                         spdif_tx: spdif-tx {
 811                                 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
 812                         };
 813                 };
 814
 815                 spi0 {
 816                         spi0_clk: spi0-clk {
 817                                 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>;
 818                         };
 819
 820                         spi0_cs0: spi0-cs0 {
 821                                 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>;
 822                         };
 823
 824                         spi0_tx: spi0-tx {
 825                                 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>;
 826                         };
 827
 828                         spi0_rx: spi0-rx {
 829                                 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>;
 830                         };
 831
 832                         spi0_cs1: spi0-cs1 {
 833                                 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>;
 834                         };
 835
 836                         spi1_clk: spi1-clk {
 837                                 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
 838                         };
 839
 840                         spi1_cs0: spi1-cs0 {
 841                                 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
 842                         };
 843
 844                         spi1_tx: spi1-tx {
 845                                 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
 846                         };
 847
 848                         spi1_rx: spi1-rx {
 849                                 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
 850                         };
 851
 852                         spi1_cs1: spi1-cs1 {
 853                                 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
 854                         };
 855
 856                         spi2_clk: spi2-clk {
 857                                 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>;
 858                         };
 859
 860                         spi2_cs0: spi2-cs0 {
 861                                 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>;
 862                         };
 863
 864                         spi2_tx: spi2-tx {
 865                                 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>;
 866                         };
 867
 868                         spi2_rx: spi2-rx {
 869                                 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>;
 870                         };
 871                 };
 872
 873                 uart0 {
 874                         uart0_xfer: uart0-xfer {
 875                                 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>,
 876                                                 <2 RK_PD3 2 &pcfg_pull_none>;
 877                         };
 878
 879                         uart0_cts: uart0-cts {
 880                                 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>;
 881                         };
 882
 883                         uart0_rts: uart0-rts {
 884                                 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>;
 885                         };
 886                 };
 887
 888                 uart1 {
 889                         uart1_xfer: uart1-xfer {
 890                                 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>,
 891                                                 <1 RK_PB2 2 &pcfg_pull_default>;
 892                         };
 893
 894                         uart1_cts: uart1-cts {
 895                                 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
 896                         };
 897
 898                         uart1_rts: uart1-rts {
 899                                 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
 900                         };
 901                 };
 902
 903                 uart2 {
 904                         uart2_xfer: uart2-xfer {
 905                                 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
 906                                                 <1 RK_PC3 2 &pcfg_pull_none>;
 907                         };
 908
 909                         uart2_cts: uart2-cts {
 910                                 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
 911                         };
 912
 913                         uart2_rts: uart2-rts {
 914                                 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
 915                         };
 916                 };
 917         };
 918 };