arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include "skeleton.dtsi"
  49
  50 / {
  51         compatible = "rockchip,rk3288";
  52
  53         interrupt-parent = <&gic>;
  54
  55         aliases {
  56                 ethernet0 = &gmac;
  57                 i2c0 = &i2c0;
  58                 i2c1 = &i2c1;
  59                 i2c2 = &i2c2;
  60                 i2c3 = &i2c3;
  61                 i2c4 = &i2c4;
  62                 i2c5 = &i2c5;
  63                 mshc0 = &emmc;
  64                 mshc1 = &sdmmc;
  65                 mshc2 = &sdio0;
  66                 mshc3 = &sdio1;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71                 serial4 = &uart4;
  72                 spi0 = &spi0;
  73                 spi1 = &spi1;
  74                 spi2 = &spi2;
  75         };
  76
  77         arm-pmu {
  78                 compatible = "arm,cortex-a12-pmu";
  79                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  80                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  82                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  83                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  84         };
  85
  86         cpus {
  87                 #address-cells = <1>;
  88                 #size-cells = <0>;
  89                 enable-method = "rockchip,rk3066-smp";
  90                 rockchip,pmu = <&pmu>;
  91
  92                 cpu0: cpu@500 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a12";
  95                         reg = <0x500>;
  96                         resets = <&cru SRST_CORE0>;
  97                         operating-points = <
  98                                 /* KHz    uV */
  99                                 1608000 1350000
 100                                 1512000 1300000
 101                                 1416000 1200000
 102                                 1200000 1100000
 103                                 1008000 1050000
 104                                  816000 1000000
 105                                  696000  950000
 106                                  600000  900000
 107                                  408000  900000
 108                                  312000  900000
 109                                  216000  900000
 110                                  126000  900000
 111                         >;
 112                         #cooling-cells = <2>; /* min followed by max */
 113                         clock-latency = <40000>;
 114                         clocks = <&cru ARMCLK>;
 115                 };
 116                 cpu1: cpu@501 {
 117                         device_type = "cpu";
 118                         compatible = "arm,cortex-a12";
 119                         reg = <0x501>;
 120                         resets = <&cru SRST_CORE1>;
 121                 };
 122                 cpu2: cpu@502 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a12";
 125                         reg = <0x502>;
 126                         resets = <&cru SRST_CORE2>;
 127                 };
 128                 cpu3: cpu@503 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a12";
 131                         reg = <0x503>;
 132                         resets = <&cru SRST_CORE3>;
 133                 };
 134         };
 135
 136         amba {
 137                 compatible = "simple-bus";
 138                 #address-cells = <1>;
 139                 #size-cells = <1>;
 140                 ranges;
 141
 142                 dmac_peri: dma-controller@ff250000 {
 143                         compatible = "arm,pl330", "arm,primecell";
 144                         reg = <0xff250000 0x4000>;
 145                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 146                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 147                         #dma-cells = <1>;
 148                         arm,pl330-broken-no-flushp;
 149                         clocks = <&cru ACLK_DMAC2>;
 150                         clock-names = "apb_pclk";
 151                 };
 152
 153                 dmac_bus_ns: dma-controller@ff600000 {
 154                         compatible = "arm,pl330", "arm,primecell";
 155                         reg = <0xff600000 0x4000>;
 156                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 157                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 158                         #dma-cells = <1>;
 159                         arm,pl330-broken-no-flushp;
 160                         clocks = <&cru ACLK_DMAC1>;
 161                         clock-names = "apb_pclk";
 162                         status = "disabled";
 163                 };
 164
 165                 dmac_bus_s: dma-controller@ffb20000 {
 166                         compatible = "arm,pl330", "arm,primecell";
 167                         reg = <0xffb20000 0x4000>;
 168                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 169                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 170                         #dma-cells = <1>;
 171                         arm,pl330-broken-no-flushp;
 172                         clocks = <&cru ACLK_DMAC1>;
 173                         clock-names = "apb_pclk";
 174                 };
 175         };
 176
 177         reserved-memory {
 178                 #address-cells = <1>;
 179                 #size-cells = <1>;
 180                 ranges;
 181
 182                 /*
 183                  * The rk3288 cannot use the memory area above 0xfe000000
 184                  * for dma operations for some reason. While there is
 185                  * probably a better solution available somewhere, we
 186                  * haven't found it yet and while devices with 2GB of ram
 187                  * are not affected, this issue prevents 4GB from booting.
 188                  * So to make these devices at least bootable, block
 189                  * this area for the time being until the real solution
 190                  * is found.
 191                  */
 192                 dma-unusable@fe000000 {
 193                         reg = <0xfe000000 0x1000000>;
 194                 };
 195         };
 196
 197         xin24m: oscillator {
 198                 compatible = "fixed-clock";
 199                 clock-frequency = <24000000>;
 200                 clock-output-names = "xin24m";
 201                 #clock-cells = <0>;
 202         };
 203
 204         timer {
 205                 compatible = "arm,armv7-timer";
 206                 arm,cpu-registers-not-fw-configured;
 207                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 208                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 209                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 210                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 211                 clock-frequency = <24000000>;
 212         };
 213
 214         timer: timer@ff810000 {
 215                 compatible = "rockchip,rk3288-timer";
 216                 reg = <0xff810000 0x20>;
 217                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 218                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 219                 clock-names = "timer", "pclk";
 220         };
 221
 222         display-subsystem {
 223                 compatible = "rockchip,display-subsystem";
 224                 ports = <&vopl_out>, <&vopb_out>;
 225         };
 226
 227         sdmmc: dwmmc@ff0c0000 {
 228                 compatible = "rockchip,rk3288-dw-mshc";
 229                 clock-freq-min-max = <400000 150000000>;
 230                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 231                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 232                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 233                 fifo-depth = <0x100>;
 234                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 235                 reg = <0xff0c0000 0x4000>;
 236                 status = "disabled";
 237         };
 238
 239         sdio0: dwmmc@ff0d0000 {
 240                 compatible = "rockchip,rk3288-dw-mshc";
 241                 clock-freq-min-max = <400000 150000000>;
 242                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 243                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 244                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 245                 fifo-depth = <0x100>;
 246                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 247                 reg = <0xff0d0000 0x4000>;
 248                 status = "disabled";
 249         };
 250
 251         sdio1: dwmmc@ff0e0000 {
 252                 compatible = "rockchip,rk3288-dw-mshc";
 253                 clock-freq-min-max = <400000 150000000>;
 254                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 255                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 256                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 257                 fifo-depth = <0x100>;
 258                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 259                 reg = <0xff0e0000 0x4000>;
 260                 status = "disabled";
 261         };
 262
 263         emmc: dwmmc@ff0f0000 {
 264                 compatible = "rockchip,rk3288-dw-mshc";
 265                 clock-freq-min-max = <400000 150000000>;
 266                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 267                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 268                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 269                 fifo-depth = <0x100>;
 270                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 271                 reg = <0xff0f0000 0x4000>;
 272                 status = "disabled";
 273         };
 274
 275         saradc: saradc@ff100000 {
 276                 compatible = "rockchip,saradc";
 277                 reg = <0xff100000 0x100>;
 278                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 279                 #io-channel-cells = <1>;
 280                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 281                 clock-names = "saradc", "apb_pclk";
 282                 status = "disabled";
 283         };
 284
 285         spi0: spi@ff110000 {
 286                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 287                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 288                 clock-names = "spiclk", "apb_pclk";
 289                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 290                 dma-names = "tx", "rx";
 291                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 292                 pinctrl-names = "default";
 293                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 294                 reg = <0xff110000 0x1000>;
 295                 #address-cells = <1>;
 296                 #size-cells = <0>;
 297                 status = "disabled";
 298         };
 299
 300         spi1: spi@ff120000 {
 301                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 302                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 303                 clock-names = "spiclk", "apb_pclk";
 304                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 305                 dma-names = "tx", "rx";
 306                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 307                 pinctrl-names = "default";
 308                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 309                 reg = <0xff120000 0x1000>;
 310                 #address-cells = <1>;
 311                 #size-cells = <0>;
 312                 status = "disabled";
 313         };
 314
 315         spi2: spi@ff130000 {
 316                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 317                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 318                 clock-names = "spiclk", "apb_pclk";
 319                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 320                 dma-names = "tx", "rx";
 321                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 322                 pinctrl-names = "default";
 323                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 324                 reg = <0xff130000 0x1000>;
 325                 #address-cells = <1>;
 326                 #size-cells = <0>;
 327                 status = "disabled";
 328         };
 329
 330         i2c1: i2c@ff140000 {
 331                 compatible = "rockchip,rk3288-i2c";
 332                 reg = <0xff140000 0x1000>;
 333                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 334                 #address-cells = <1>;
 335                 #size-cells = <0>;
 336                 clock-names = "i2c";
 337                 clocks = <&cru PCLK_I2C1>;
 338                 pinctrl-names = "default";
 339                 pinctrl-0 = <&i2c1_xfer>;
 340                 status = "disabled";
 341         };
 342
 343         i2c3: i2c@ff150000 {
 344                 compatible = "rockchip,rk3288-i2c";
 345                 reg = <0xff150000 0x1000>;
 346                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 347                 #address-cells = <1>;
 348                 #size-cells = <0>;
 349                 clock-names = "i2c";
 350                 clocks = <&cru PCLK_I2C3>;
 351                 pinctrl-names = "default";
 352                 pinctrl-0 = <&i2c3_xfer>;
 353                 status = "disabled";
 354         };
 355
 356         i2c4: i2c@ff160000 {
 357                 compatible = "rockchip,rk3288-i2c";
 358                 reg = <0xff160000 0x1000>;
 359                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 360                 #address-cells = <1>;
 361                 #size-cells = <0>;
 362                 clock-names = "i2c";
 363                 clocks = <&cru PCLK_I2C4>;
 364                 pinctrl-names = "default";
 365                 pinctrl-0 = <&i2c4_xfer>;
 366                 status = "disabled";
 367         };
 368
 369         i2c5: i2c@ff170000 {
 370                 compatible = "rockchip,rk3288-i2c";
 371                 reg = <0xff170000 0x1000>;
 372                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 373                 #address-cells = <1>;
 374                 #size-cells = <0>;
 375                 clock-names = "i2c";
 376                 clocks = <&cru PCLK_I2C5>;
 377                 pinctrl-names = "default";
 378                 pinctrl-0 = <&i2c5_xfer>;
 379                 status = "disabled";
 380         };
 381
 382         uart0: serial@ff180000 {
 383                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 384                 reg = <0xff180000 0x100>;
 385                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 386                 reg-shift = <2>;
 387                 reg-io-width = <4>;
 388                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 389                 clock-names = "baudclk", "apb_pclk";
 390                 pinctrl-names = "default";
 391                 pinctrl-0 = <&uart0_xfer>;
 392                 status = "disabled";
 393         };
 394
 395         uart1: serial@ff190000 {
 396                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 397                 reg = <0xff190000 0x100>;
 398                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 399                 reg-shift = <2>;
 400                 reg-io-width = <4>;
 401                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 402                 clock-names = "baudclk", "apb_pclk";
 403                 pinctrl-names = "default";
 404                 pinctrl-0 = <&uart1_xfer>;
 405                 status = "disabled";
 406         };
 407
 408         uart2: serial@ff690000 {
 409                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 410                 reg = <0xff690000 0x100>;
 411                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 412                 reg-shift = <2>;
 413                 reg-io-width = <4>;
 414                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 415                 clock-names = "baudclk", "apb_pclk";
 416                 pinctrl-names = "default";
 417                 pinctrl-0 = <&uart2_xfer>;
 418                 status = "disabled";
 419         };
 420
 421         uart3: serial@ff1b0000 {
 422                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 423                 reg = <0xff1b0000 0x100>;
 424                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 425                 reg-shift = <2>;
 426                 reg-io-width = <4>;
 427                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 428                 clock-names = "baudclk", "apb_pclk";
 429                 pinctrl-names = "default";
 430                 pinctrl-0 = <&uart3_xfer>;
 431                 status = "disabled";
 432         };
 433
 434         uart4: serial@ff1c0000 {
 435                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 436                 reg = <0xff1c0000 0x100>;
 437                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 438                 reg-shift = <2>;
 439                 reg-io-width = <4>;
 440                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 441                 clock-names = "baudclk", "apb_pclk";
 442                 pinctrl-names = "default";
 443                 pinctrl-0 = <&uart4_xfer>;
 444                 status = "disabled";
 445         };
 446
 447         thermal-zones {
 448                 reserve_thermal: reserve_thermal {
 449                         polling-delay-passive = <1000>; /* milliseconds */
 450                         polling-delay = <5000>; /* milliseconds */
 451
 452                         thermal-sensors = <&tsadc 0>;
 453                 };
 454
 455                 cpu_thermal: cpu_thermal {
 456                         polling-delay-passive = <100>; /* milliseconds */
 457                         polling-delay = <5000>; /* milliseconds */
 458
 459                         thermal-sensors = <&tsadc 1>;
 460
 461                         trips {
 462                                 cpu_alert0: cpu_alert0 {
 463                                         temperature = <70000>; /* millicelsius */
 464                                         hysteresis = <2000>; /* millicelsius */
 465                                         type = "passive";
 466                                 };
 467                                 cpu_alert1: cpu_alert1 {
 468                                         temperature = <75000>; /* millicelsius */
 469                                         hysteresis = <2000>; /* millicelsius */
 470                                         type = "passive";
 471                                 };
 472                                 cpu_crit: cpu_crit {
 473                                         temperature = <90000>; /* millicelsius */
 474                                         hysteresis = <2000>; /* millicelsius */
 475                                         type = "critical";
 476                                 };
 477                         };
 478
 479                         cooling-maps {
 480                                 map0 {
 481                                         trip = <&cpu_alert0>;
 482                                         cooling-device =
 483                                                 <&cpu0 THERMAL_NO_LIMIT 6>;
 484                                 };
 485                                 map1 {
 486                                         trip = <&cpu_alert1>;
 487                                         cooling-device =
 488                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 489                                 };
 490                         };
 491                 };
 492
 493                 gpu_thermal: gpu_thermal {
 494                         polling-delay-passive = <100>; /* milliseconds */
 495                         polling-delay = <5000>; /* milliseconds */
 496
 497                         thermal-sensors = <&tsadc 2>;
 498
 499                         trips {
 500                                 gpu_alert0: gpu_alert0 {
 501                                         temperature = <70000>; /* millicelsius */
 502                                         hysteresis = <2000>; /* millicelsius */
 503                                         type = "passive";
 504                                 };
 505                                 gpu_crit: gpu_crit {
 506                                         temperature = <90000>; /* millicelsius */
 507                                         hysteresis = <2000>; /* millicelsius */
 508                                         type = "critical";
 509                                 };
 510                         };
 511
 512                         cooling-maps {
 513                                 map0 {
 514                                         trip = <&gpu_alert0>;
 515                                         cooling-device =
 516                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 517                                 };
 518                         };
 519                 };
 520         };
 521
 522         tsadc: tsadc@ff280000 {
 523                 compatible = "rockchip,rk3288-tsadc";
 524                 reg = <0xff280000 0x100>;
 525                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 526                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 527                 clock-names = "tsadc", "apb_pclk";
 528                 resets = <&cru SRST_TSADC>;
 529                 reset-names = "tsadc-apb";
 530                 pinctrl-names = "init", "default", "sleep";
 531                 pinctrl-0 = <&otp_gpio>;
 532                 pinctrl-1 = <&otp_out>;
 533                 pinctrl-2 = <&otp_gpio>;
 534                 #thermal-sensor-cells = <1>;
 535                 rockchip,hw-tshut-temp = <95000>;
 536                 status = "disabled";
 537         };
 538
 539         gmac: ethernet@ff290000 {
 540                 compatible = "rockchip,rk3288-gmac";
 541                 reg = <0xff290000 0x10000>;
 542                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 543                                 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 544                 interrupt-names = "macirq", "eth_wake_irq";
 545                 rockchip,grf = <&grf>;
 546                 clocks = <&cru SCLK_MAC>,
 547                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 548                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 549                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 550                 clock-names = "stmmaceth",
 551                         "mac_clk_rx", "mac_clk_tx",
 552                         "clk_mac_ref", "clk_mac_refout",
 553                         "aclk_mac", "pclk_mac";
 554                 resets = <&cru SRST_MAC>;
 555                 reset-names = "stmmaceth";
 556                 status = "disabled";
 557         };
 558
 559         usb_host0_ehci: usb@ff500000 {
 560                 compatible = "generic-ehci";
 561                 reg = <0xff500000 0x100>;
 562                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 563                 clocks = <&cru HCLK_USBHOST0>;
 564                 clock-names = "usbhost";
 565                 phys = <&usbphy1>;
 566                 phy-names = "usb";
 567                 status = "disabled";
 568         };
 569
 570         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 571
 572         usb_host1: usb@ff540000 {
 573                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 574                                 "snps,dwc2";
 575                 reg = <0xff540000 0x40000>;
 576                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 577                 clocks = <&cru HCLK_USBHOST1>;
 578                 clock-names = "otg";
 579                 dr_mode = "host";
 580                 phys = <&usbphy2>;
 581                 phy-names = "usb2-phy";
 582                 status = "disabled";
 583         };
 584
 585         usb_otg: usb@ff580000 {
 586                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 587                                 "snps,dwc2";
 588                 reg = <0xff580000 0x40000>;
 589                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 590                 clocks = <&cru HCLK_OTG0>;
 591                 clock-names = "otg";
 592                 dr_mode = "otg";
 593                 g-np-tx-fifo-size = <16>;
 594                 g-rx-fifo-size = <275>;
 595                 g-tx-fifo-size = <256 128 128 64 64 32>;
 596                 g-use-dma;
 597                 phys = <&usbphy0>;
 598                 phy-names = "usb2-phy";
 599                 status = "disabled";
 600         };
 601
 602         usb_hsic: usb@ff5c0000 {
 603                 compatible = "generic-ehci";
 604                 reg = <0xff5c0000 0x100>;
 605                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 606                 clocks = <&cru HCLK_HSIC>;
 607                 clock-names = "usbhost";
 608                 status = "disabled";
 609         };
 610
 611         i2c0: i2c@ff650000 {
 612                 compatible = "rockchip,rk3288-i2c";
 613                 reg = <0xff650000 0x1000>;
 614                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 615                 #address-cells = <1>;
 616                 #size-cells = <0>;
 617                 clock-names = "i2c";
 618                 clocks = <&cru PCLK_I2C0>;
 619                 pinctrl-names = "default";
 620                 pinctrl-0 = <&i2c0_xfer>;
 621                 status = "disabled";
 622         };
 623
 624         i2c2: i2c@ff660000 {
 625                 compatible = "rockchip,rk3288-i2c";
 626                 reg = <0xff660000 0x1000>;
 627                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 628                 #address-cells = <1>;
 629                 #size-cells = <0>;
 630                 clock-names = "i2c";
 631                 clocks = <&cru PCLK_I2C2>;
 632                 pinctrl-names = "default";
 633                 pinctrl-0 = <&i2c2_xfer>;
 634                 status = "disabled";
 635         };
 636
 637         pwm0: pwm@ff680000 {
 638                 compatible = "rockchip,rk3288-pwm";
 639                 reg = <0xff680000 0x10>;
 640                 #pwm-cells = <3>;
 641                 pinctrl-names = "default";
 642                 pinctrl-0 = <&pwm0_pin>;
 643                 clocks = <&cru PCLK_PWM>;
 644                 clock-names = "pwm";
 645                 status = "disabled";
 646         };
 647
 648         pwm1: pwm@ff680010 {
 649                 compatible = "rockchip,rk3288-pwm";
 650                 reg = <0xff680010 0x10>;
 651                 #pwm-cells = <3>;
 652                 pinctrl-names = "default";
 653                 pinctrl-0 = <&pwm1_pin>;
 654                 clocks = <&cru PCLK_PWM>;
 655                 clock-names = "pwm";
 656                 status = "disabled";
 657         };
 658
 659         pwm2: pwm@ff680020 {
 660                 compatible = "rockchip,rk3288-pwm";
 661                 reg = <0xff680020 0x10>;
 662                 #pwm-cells = <3>;
 663                 pinctrl-names = "default";
 664                 pinctrl-0 = <&pwm2_pin>;
 665                 clocks = <&cru PCLK_PWM>;
 666                 clock-names = "pwm";
 667                 status = "disabled";
 668         };
 669
 670         pwm3: pwm@ff680030 {
 671                 compatible = "rockchip,rk3288-pwm";
 672                 reg = <0xff680030 0x10>;
 673                 #pwm-cells = <2>;
 674                 pinctrl-names = "default";
 675                 pinctrl-0 = <&pwm3_pin>;
 676                 clocks = <&cru PCLK_PWM>;
 677                 clock-names = "pwm";
 678                 status = "disabled";
 679         };
 680
 681         bus_intmem@ff700000 {
 682                 compatible = "mmio-sram";
 683                 reg = <0xff700000 0x18000>;
 684                 #address-cells = <1>;
 685                 #size-cells = <1>;
 686                 ranges = <0 0xff700000 0x18000>;
 687                 smp-sram@0 {
 688                         compatible = "rockchip,rk3066-smp-sram";
 689                         reg = <0x00 0x10>;
 690                 };
 691         };
 692
 693         sram@ff720000 {
 694                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 695                 reg = <0xff720000 0x1000>;
 696         };
 697
 698         pmu: power-management@ff730000 {
 699                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 700                 reg = <0xff730000 0x100>;
 701
 702                 power: power-controller {
 703                         compatible = "rockchip,rk3288-power-controller";
 704                         #power-domain-cells = <1>;
 705                         #address-cells = <1>;
 706                         #size-cells = <0>;
 707
 708                         assigned-clocks = <&cru SCLK_EDP_24M>;
 709                         assigned-clock-parents = <&xin24m>;
 710
 711                         /*
 712                          * Note: Although SCLK_* are the working clocks
 713                          * of device without including on the NOC, needed for
 714                          * synchronous reset.
 715                          *
 716                          * The clocks on the which NOC:
 717                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 718                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 719                          * ACLK_RGA is on ACLK_RGA_NIU.
 720                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 721                          *
 722                          * Which clock are device clocks:
 723                          *      clocks          devices
 724                          *      *_IEP           IEP:Image Enhancement Processor
 725                          *      *_ISP           ISP:Image Signal Processing
 726                          *      *_VIP           VIP:Video Input Processor
 727                          *      *_VOP*          VOP:Visual Output Processor
 728                          *      *_RGA           RGA
 729                          *      *_EDP*          EDP
 730                          *      *_LVDS_*        LVDS
 731                          *      *_HDMI          HDMI
 732                          *      *_MIPI_*        MIPI
 733                          */
 734                         pd_vio@RK3288_PD_VIO {
 735                                 reg = <RK3288_PD_VIO>;
 736                                 clocks = <&cru ACLK_IEP>,
 737                                          <&cru ACLK_ISP>,
 738                                          <&cru ACLK_RGA>,
 739                                          <&cru ACLK_VIP>,
 740                                          <&cru ACLK_VOP0>,
 741                                          <&cru ACLK_VOP1>,
 742                                          <&cru DCLK_VOP0>,
 743                                          <&cru DCLK_VOP1>,
 744                                          <&cru HCLK_IEP>,
 745                                          <&cru HCLK_ISP>,
 746                                          <&cru HCLK_RGA>,
 747                                          <&cru HCLK_VIP>,
 748                                          <&cru HCLK_VOP0>,
 749                                          <&cru HCLK_VOP1>,
 750                                          <&cru PCLK_EDP_CTRL>,
 751                                          <&cru PCLK_HDMI_CTRL>,
 752                                          <&cru PCLK_LVDS_PHY>,
 753                                          <&cru PCLK_MIPI_CSI>,
 754                                          <&cru PCLK_MIPI_DSI0>,
 755                                          <&cru PCLK_MIPI_DSI1>,
 756                                          <&cru SCLK_EDP_24M>,
 757                                          <&cru SCLK_EDP>,
 758                                          <&cru SCLK_ISP_JPE>,
 759                                          <&cru SCLK_ISP>,
 760                                          <&cru SCLK_RGA>;
 761                         };
 762
 763                         /*
 764                          * Note: The following 3 are HEVC(H.265) clocks,
 765                          * and on the ACLK_HEVC_NIU (NOC).
 766                          */
 767                         pd_hevc@RK3288_PD_HEVC {
 768                                 reg = <RK3288_PD_HEVC>;
 769                                 clocks = <&cru ACLK_HEVC>,
 770                                          <&cru SCLK_HEVC_CABAC>,
 771                                          <&cru SCLK_HEVC_CORE>;
 772                         };
 773
 774                         /*
 775                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 776                          * (video endecoder & decoder) clocks that on the
 777                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 778                          */
 779                         pd_video@RK3288_PD_VIDEO {
 780                                 reg = <RK3288_PD_VIDEO>;
 781                                 clocks = <&cru ACLK_VCODEC>,
 782                                          <&cru HCLK_VCODEC>;
 783                         };
 784
 785                         /*
 786                          * Note: ACLK_GPU is the GPU clock,
 787                          * and on the ACLK_GPU_NIU (NOC).
 788                          */
 789                         pd_gpu@RK3288_PD_GPU {
 790                                 reg = <RK3288_PD_GPU>;
 791                                 clocks = <&cru ACLK_GPU>;
 792                         };
 793                 };
 794         };
 795
 796         sgrf: syscon@ff740000 {
 797                 compatible = "rockchip,rk3288-sgrf", "syscon";
 798                 reg = <0xff740000 0x1000>;
 799         };
 800
 801         cru: clock-controller@ff760000 {
 802                 compatible = "rockchip,rk3288-cru";
 803                 reg = <0xff760000 0x1000>;
 804                 rockchip,grf = <&grf>;
 805                 #clock-cells = <1>;
 806                 #reset-cells = <1>;
 807                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 808                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 809                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 810                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 811                                   <&cru PCLK_PERI>;
 812                 assigned-clock-rates = <594000000>, <400000000>,
 813                                        <500000000>, <300000000>,
 814                                        <150000000>, <75000000>,
 815                                        <300000000>, <150000000>,
 816                                        <75000000>;
 817         };
 818
 819         grf: syscon@ff770000 {
 820                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 821                 reg = <0xff770000 0x1000>;
 822
 823                 edp_phy: edp-phy {
 824                         compatible = "rockchip,rk3288-dp-phy";
 825                         clocks = <&cru SCLK_EDP_24M>;
 826                         clock-names = "24m";
 827                         #phy-cells = <0>;
 828                         status = "disabled";
 829                 };
 830
 831                 io_domains: io-domains {
 832                         compatible = "rockchip,rk3288-io-voltage-domain";
 833                         status = "disabled";
 834                 };
 835         };
 836
 837         wdt: watchdog@ff800000 {
 838                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 839                 reg = <0xff800000 0x100>;
 840                 clocks = <&cru PCLK_WDT>;
 841                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 842                 status = "disabled";
 843         };
 844
 845         spdif: sound@ff88b0000 {
 846                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 847                 reg = <0xff8b0000 0x10000>;
 848                 #sound-dai-cells = <0>;
 849                 clock-names = "hclk", "mclk";
 850                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 851                 dmas = <&dmac_bus_s 3>;
 852                 dma-names = "tx";
 853                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 854                 pinctrl-names = "default";
 855                 pinctrl-0 = <&spdif_tx>;
 856                 rockchip,grf = <&grf>;
 857                 status = "disabled";
 858         };
 859
 860         i2s: i2s@ff890000 {
 861                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 862                 reg = <0xff890000 0x10000>;
 863                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 864                 #address-cells = <1>;
 865                 #size-cells = <0>;
 866                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 867                 dma-names = "tx", "rx";
 868                 clock-names = "i2s_hclk", "i2s_clk";
 869                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 870                 pinctrl-names = "default";
 871                 pinctrl-0 = <&i2s0_bus>;
 872                 rockchip,playback-channels = <8>;
 873                 rockchip,capture-channels = <2>;
 874                 status = "disabled";
 875         };
 876
 877         crypto: cypto-controller@ff8a0000 {
 878                 compatible = "rockchip,rk3288-crypto";
 879                 reg = <0xff8a0000 0x4000>;
 880                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 881                 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
 882                          <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
 883                 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
 884                 resets = <&cru SRST_CRYPTO>;
 885                 reset-names = "crypto-rst";
 886                 status = "okay";
 887         };
 888
 889         vopb: vop@ff930000 {
 890                 compatible = "rockchip,rk3288-vop";
 891                 reg = <0xff930000 0x19c>;
 892                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 893                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 894                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 895                 power-domains = <&power RK3288_PD_VIO>;
 896                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 897                 reset-names = "axi", "ahb", "dclk";
 898                 iommus = <&vopb_mmu>;
 899                 status = "disabled";
 900
 901                 vopb_out: port {
 902                         #address-cells = <1>;
 903                         #size-cells = <0>;
 904
 905                         vopb_out_hdmi: endpoint@0 {
 906                                 reg = <0>;
 907                                 remote-endpoint = <&hdmi_in_vopb>;
 908                         };
 909
 910                         vopb_out_edp: endpoint@1 {
 911                                 reg = <1>;
 912                                 remote-endpoint = <&edp_in_vopb>;
 913                         };
 914
 915                         vopb_out_mipi: endpoint@2 {
 916                                 reg = <2>;
 917                                 remote-endpoint = <&mipi_in_vopb>;
 918                         };
 919                 };
 920         };
 921
 922         vopb_mmu: iommu@ff930300 {
 923                 compatible = "rockchip,iommu";
 924                 reg = <0xff930300 0x100>;
 925                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 926                 interrupt-names = "vopb_mmu";
 927                 power-domains = <&power RK3288_PD_VIO>;
 928                 #iommu-cells = <0>;
 929                 status = "disabled";
 930         };
 931
 932         vopl: vop@ff940000 {
 933                 compatible = "rockchip,rk3288-vop";
 934                 reg = <0xff940000 0x19c>;
 935                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 936                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 937                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 938                 power-domains = <&power RK3288_PD_VIO>;
 939                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 940                 reset-names = "axi", "ahb", "dclk";
 941                 iommus = <&vopl_mmu>;
 942                 status = "disabled";
 943
 944                 vopl_out: port {
 945                         #address-cells = <1>;
 946                         #size-cells = <0>;
 947
 948                         vopl_out_hdmi: endpoint@0 {
 949                                 reg = <0>;
 950                                 remote-endpoint = <&hdmi_in_vopl>;
 951                         };
 952
 953                         vopl_out_edp: endpoint@1 {
 954                                 reg = <1>;
 955                                 remote-endpoint = <&edp_in_vopl>;
 956                         };
 957
 958                         vopl_out_mipi: endpoint@2 {
 959                                 reg = <2>;
 960                                 remote-endpoint = <&mipi_in_vopl>;
 961                         };
 962                 };
 963         };
 964
 965         vopl_mmu: iommu@ff940300 {
 966                 compatible = "rockchip,iommu";
 967                 reg = <0xff940300 0x100>;
 968                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 969                 interrupt-names = "vopl_mmu";
 970                 power-domains = <&power RK3288_PD_VIO>;
 971                 #iommu-cells = <0>;
 972                 status = "disabled";
 973         };
 974
 975         mipi_dsi: mipi@ff960000 {
 976                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
 977                 reg = <0xff960000 0x4000>;
 978                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 979                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
 980                 clock-names = "ref", "pclk";
 981                 power-domains = <&power RK3288_PD_VIO>;
 982                 rockchip,grf = <&grf>;
 983                 #address-cells = <1>;
 984                 #size-cells = <0>;
 985                 status = "disabled";
 986
 987                 ports {
 988                         mipi_in: port {
 989                                 #address-cells = <1>;
 990                                 #size-cells = <0>;
 991                                 mipi_in_vopb: endpoint@0 {
 992                                         reg = <0>;
 993                                         remote-endpoint = <&vopb_out_mipi>;
 994                                 };
 995                                 mipi_in_vopl: endpoint@1 {
 996                                         reg = <1>;
 997                                         remote-endpoint = <&vopl_out_mipi>;
 998                                 };
 999                         };
1000                 };
1001         };
1002
1003         edp: dp@ff970000 {
1004                 compatible = "rockchip,rk3288-dp";
1005                 reg = <0xff970000 0x4000>;
1006                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1007                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1008                 clock-names = "dp", "pclk";
1009                 phys = <&edp_phy>;
1010                 phy-names = "dp";
1011                 resets = <&cru SRST_EDP>;
1012                 reset-names = "dp";
1013                 rockchip,grf = <&grf>;
1014                 status = "disabled";
1015
1016                 ports {
1017                         #address-cells = <1>;
1018                         #size-cells = <0>;
1019                         edp_in: port@0 {
1020                                 reg = <0>;
1021                                 #address-cells = <1>;
1022                                 #size-cells = <0>;
1023                                 edp_in_vopb: endpoint@0 {
1024                                         reg = <0>;
1025                                         remote-endpoint = <&vopb_out_edp>;
1026                                 };
1027                                 edp_in_vopl: endpoint@1 {
1028                                         reg = <1>;
1029                                         remote-endpoint = <&vopl_out_edp>;
1030                                 };
1031                         };
1032                 };
1033         };
1034
1035         hdmi: hdmi@ff980000 {
1036                 compatible = "rockchip,rk3288-dw-hdmi";
1037                 reg = <0xff980000 0x20000>;
1038                 reg-io-width = <4>;
1039                 rockchip,grf = <&grf>;
1040                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1041                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1042                 clock-names = "iahb", "isfr";
1043                 power-domains = <&power RK3288_PD_VIO>;
1044                 status = "disabled";
1045
1046                 ports {
1047                         hdmi_in: port {
1048                                 #address-cells = <1>;
1049                                 #size-cells = <0>;
1050                                 hdmi_in_vopb: endpoint@0 {
1051                                         reg = <0>;
1052                                         remote-endpoint = <&vopb_out_hdmi>;
1053                                 };
1054                                 hdmi_in_vopl: endpoint@1 {
1055                                         reg = <1>;
1056                                         remote-endpoint = <&vopl_out_hdmi>;
1057                                 };
1058                         };
1059                 };
1060         };
1061
1062         gic: interrupt-controller@ffc01000 {
1063                 compatible = "arm,gic-400";
1064                 interrupt-controller;
1065                 #interrupt-cells = <3>;
1066                 #address-cells = <0>;
1067
1068                 reg = <0xffc01000 0x1000>,
1069                       <0xffc02000 0x1000>,
1070                       <0xffc04000 0x2000>,
1071                       <0xffc06000 0x2000>;
1072                 interrupts = <GIC_PPI 9 0xf04>;
1073         };
1074
1075         efuse: efuse@ffb40000 {
1076                 compatible = "rockchip,rockchip-efuse";
1077                 reg = <0xffb40000 0x20>;
1078                 #address-cells = <1>;
1079                 #size-cells = <1>;
1080                 clocks = <&cru PCLK_EFUSE256>;
1081                 clock-names = "pclk_efuse";
1082
1083                 cpu_leakage: cpu_leakage@17 {
1084                         reg = <0x17 0x1>;
1085                 };
1086         };
1087
1088         usbphy: phy {
1089                 compatible = "rockchip,rk3288-usb-phy";
1090                 rockchip,grf = <&grf>;
1091                 #address-cells = <1>;
1092                 #size-cells = <0>;
1093                 status = "disabled";
1094
1095                 usbphy0: usb-phy@320 {
1096                         #phy-cells = <0>;
1097                         reg = <0x320>;
1098                         clocks = <&cru SCLK_OTGPHY0>;
1099                         clock-names = "phyclk";
1100                         #clock-cells = <0>;
1101                 };
1102
1103                 usbphy1: usb-phy@334 {
1104                         #phy-cells = <0>;
1105                         reg = <0x334>;
1106                         clocks = <&cru SCLK_OTGPHY1>;
1107                         clock-names = "phyclk";
1108                         #clock-cells = <0>;
1109                 };
1110
1111                 usbphy2: usb-phy@348 {
1112                         #phy-cells = <0>;
1113                         reg = <0x348>;
1114                         clocks = <&cru SCLK_OTGPHY2>;
1115                         clock-names = "phyclk";
1116                         #clock-cells = <0>;
1117                 };
1118         };
1119
1120         pinctrl: pinctrl {
1121                 compatible = "rockchip,rk3288-pinctrl";
1122                 rockchip,grf = <&grf>;
1123                 rockchip,pmu = <&pmu>;
1124                 #address-cells = <1>;
1125                 #size-cells = <1>;
1126                 ranges;
1127
1128                 gpio0: gpio0@ff750000 {
1129                         compatible = "rockchip,gpio-bank";
1130                         reg =   <0xff750000 0x100>;
1131                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1132                         clocks = <&cru PCLK_GPIO0>;
1133
1134                         gpio-controller;
1135                         #gpio-cells = <2>;
1136
1137                         interrupt-controller;
1138                         #interrupt-cells = <2>;
1139                 };
1140
1141                 gpio1: gpio1@ff780000 {
1142                         compatible = "rockchip,gpio-bank";
1143                         reg = <0xff780000 0x100>;
1144                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1145                         clocks = <&cru PCLK_GPIO1>;
1146
1147                         gpio-controller;
1148                         #gpio-cells = <2>;
1149
1150                         interrupt-controller;
1151                         #interrupt-cells = <2>;
1152                 };
1153
1154                 gpio2: gpio2@ff790000 {
1155                         compatible = "rockchip,gpio-bank";
1156                         reg = <0xff790000 0x100>;
1157                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1158                         clocks = <&cru PCLK_GPIO2>;
1159
1160                         gpio-controller;
1161                         #gpio-cells = <2>;
1162
1163                         interrupt-controller;
1164                         #interrupt-cells = <2>;
1165                 };
1166
1167                 gpio3: gpio3@ff7a0000 {
1168                         compatible = "rockchip,gpio-bank";
1169                         reg = <0xff7a0000 0x100>;
1170                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1171                         clocks = <&cru PCLK_GPIO3>;
1172
1173                         gpio-controller;
1174                         #gpio-cells = <2>;
1175
1176                         interrupt-controller;
1177                         #interrupt-cells = <2>;
1178                 };
1179
1180                 gpio4: gpio4@ff7b0000 {
1181                         compatible = "rockchip,gpio-bank";
1182                         reg = <0xff7b0000 0x100>;
1183                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1184                         clocks = <&cru PCLK_GPIO4>;
1185
1186                         gpio-controller;
1187                         #gpio-cells = <2>;
1188
1189                         interrupt-controller;
1190                         #interrupt-cells = <2>;
1191                 };
1192
1193                 gpio5: gpio5@ff7c0000 {
1194                         compatible = "rockchip,gpio-bank";
1195                         reg = <0xff7c0000 0x100>;
1196                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1197                         clocks = <&cru PCLK_GPIO5>;
1198
1199                         gpio-controller;
1200                         #gpio-cells = <2>;
1201
1202                         interrupt-controller;
1203                         #interrupt-cells = <2>;
1204                 };
1205
1206                 gpio6: gpio6@ff7d0000 {
1207                         compatible = "rockchip,gpio-bank";
1208                         reg = <0xff7d0000 0x100>;
1209                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1210                         clocks = <&cru PCLK_GPIO6>;
1211
1212                         gpio-controller;
1213                         #gpio-cells = <2>;
1214
1215                         interrupt-controller;
1216                         #interrupt-cells = <2>;
1217                 };
1218
1219                 gpio7: gpio7@ff7e0000 {
1220                         compatible = "rockchip,gpio-bank";
1221                         reg = <0xff7e0000 0x100>;
1222                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1223                         clocks = <&cru PCLK_GPIO7>;
1224
1225                         gpio-controller;
1226                         #gpio-cells = <2>;
1227
1228                         interrupt-controller;
1229                         #interrupt-cells = <2>;
1230                 };
1231
1232                 gpio8: gpio8@ff7f0000 {
1233                         compatible = "rockchip,gpio-bank";
1234                         reg = <0xff7f0000 0x100>;
1235                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1236                         clocks = <&cru PCLK_GPIO8>;
1237
1238                         gpio-controller;
1239                         #gpio-cells = <2>;
1240
1241                         interrupt-controller;
1242                         #interrupt-cells = <2>;
1243                 };
1244
1245                 hdmi {
1246                         hdmi_ddc: hdmi-ddc {
1247                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1248                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1249                         };
1250                 };
1251
1252                 pcfg_pull_up: pcfg-pull-up {
1253                         bias-pull-up;
1254                 };
1255
1256                 pcfg_pull_down: pcfg-pull-down {
1257                         bias-pull-down;
1258                 };
1259
1260                 pcfg_pull_none: pcfg-pull-none {
1261                         bias-disable;
1262                 };
1263
1264                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1265                         bias-disable;
1266                         drive-strength = <12>;
1267                 };
1268
1269                 sleep {
1270                         global_pwroff: global-pwroff {
1271                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1272                         };
1273
1274                         ddrio_pwroff: ddrio-pwroff {
1275                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1276                         };
1277
1278                         ddr0_retention: ddr0-retention {
1279                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1280                         };
1281
1282                         ddr1_retention: ddr1-retention {
1283                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1284                         };
1285                 };
1286
1287                 edp {
1288                         edp_hpd: edp-hpd {
1289                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1290                         };
1291                 };
1292
1293                 i2c0 {
1294                         i2c0_xfer: i2c0-xfer {
1295                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1296                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1297                         };
1298                 };
1299
1300                 i2c1 {
1301                         i2c1_xfer: i2c1-xfer {
1302                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1303                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1304                         };
1305                 };
1306
1307                 i2c2 {
1308                         i2c2_xfer: i2c2-xfer {
1309                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1310                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1311                         };
1312                 };
1313
1314                 i2c3 {
1315                         i2c3_xfer: i2c3-xfer {
1316                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1317                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1318                         };
1319                 };
1320
1321                 i2c4 {
1322                         i2c4_xfer: i2c4-xfer {
1323                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1324                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1325                         };
1326                 };
1327
1328                 i2c5 {
1329                         i2c5_xfer: i2c5-xfer {
1330                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1331                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1332                         };
1333                 };
1334
1335                 i2s0 {
1336                         i2s0_bus: i2s0-bus {
1337                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1338                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1339                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1340                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1341                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1342                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1343                         };
1344                 };
1345
1346                 sdmmc {
1347                         sdmmc_clk: sdmmc-clk {
1348                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1349                         };
1350
1351                         sdmmc_cmd: sdmmc-cmd {
1352                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1353                         };
1354
1355                         sdmmc_cd: sdmmc-cd {
1356                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1357                         };
1358
1359                         sdmmc_bus1: sdmmc-bus1 {
1360                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1361                         };
1362
1363                         sdmmc_bus4: sdmmc-bus4 {
1364                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1365                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1366                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1367                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1368                         };
1369                 };
1370
1371                 sdio0 {
1372                         sdio0_bus1: sdio0-bus1 {
1373                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1374                         };
1375
1376                         sdio0_bus4: sdio0-bus4 {
1377                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1378                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1379                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1380                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1381                         };
1382
1383                         sdio0_cmd: sdio0-cmd {
1384                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1385                         };
1386
1387                         sdio0_clk: sdio0-clk {
1388                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1389                         };
1390
1391                         sdio0_cd: sdio0-cd {
1392                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1393                         };
1394
1395                         sdio0_wp: sdio0-wp {
1396                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1397                         };
1398
1399                         sdio0_pwr: sdio0-pwr {
1400                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1401                         };
1402
1403                         sdio0_bkpwr: sdio0-bkpwr {
1404                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1405                         };
1406
1407                         sdio0_int: sdio0-int {
1408                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1409                         };
1410                 };
1411
1412                 sdio1 {
1413                         sdio1_bus1: sdio1-bus1 {
1414                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1415                         };
1416
1417                         sdio1_bus4: sdio1-bus4 {
1418                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1419                                                 <3 25 4 &pcfg_pull_up>,
1420                                                 <3 26 4 &pcfg_pull_up>,
1421                                                 <3 27 4 &pcfg_pull_up>;
1422                         };
1423
1424                         sdio1_cd: sdio1-cd {
1425                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1426                         };
1427
1428                         sdio1_wp: sdio1-wp {
1429                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1430                         };
1431
1432                         sdio1_bkpwr: sdio1-bkpwr {
1433                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1434                         };
1435
1436                         sdio1_int: sdio1-int {
1437                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1438                         };
1439
1440                         sdio1_cmd: sdio1-cmd {
1441                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1442                         };
1443
1444                         sdio1_clk: sdio1-clk {
1445                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1446                         };
1447
1448                         sdio1_pwr: sdio1-pwr {
1449                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1450                         };
1451                 };
1452
1453                 emmc {
1454                         emmc_clk: emmc-clk {
1455                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1456                         };
1457
1458                         emmc_cmd: emmc-cmd {
1459                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1460                         };
1461
1462                         emmc_pwr: emmc-pwr {
1463                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1464                         };
1465
1466                         emmc_bus1: emmc-bus1 {
1467                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1468                         };
1469
1470                         emmc_bus4: emmc-bus4 {
1471                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1472                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1473                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1474                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1475                         };
1476
1477                         emmc_bus8: emmc-bus8 {
1478                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1479                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1480                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1481                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1482                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1483                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1484                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1485                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1486                         };
1487                 };
1488
1489                 spi0 {
1490                         spi0_clk: spi0-clk {
1491                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1492                         };
1493                         spi0_cs0: spi0-cs0 {
1494                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1495                         };
1496                         spi0_tx: spi0-tx {
1497                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1498                         };
1499                         spi0_rx: spi0-rx {
1500                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1501                         };
1502                         spi0_cs1: spi0-cs1 {
1503                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1504                         };
1505                 };
1506                 spi1 {
1507                         spi1_clk: spi1-clk {
1508                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1509                         };
1510                         spi1_cs0: spi1-cs0 {
1511                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1512                         };
1513                         spi1_rx: spi1-rx {
1514                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1515                         };
1516                         spi1_tx: spi1-tx {
1517                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1518                         };
1519                 };
1520
1521                 spi2 {
1522                         spi2_cs1: spi2-cs1 {
1523                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1524                         };
1525                         spi2_clk: spi2-clk {
1526                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1527                         };
1528                         spi2_cs0: spi2-cs0 {
1529                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1530                         };
1531                         spi2_rx: spi2-rx {
1532                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1533                         };
1534                         spi2_tx: spi2-tx {
1535                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1536                         };
1537                 };
1538
1539                 uart0 {
1540                         uart0_xfer: uart0-xfer {
1541                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1542                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1543                         };
1544
1545                         uart0_cts: uart0-cts {
1546                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1547                         };
1548
1549                         uart0_rts: uart0-rts {
1550                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1551                         };
1552                 };
1553
1554                 uart1 {
1555                         uart1_xfer: uart1-xfer {
1556                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1557                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1558                         };
1559
1560                         uart1_cts: uart1-cts {
1561                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1562                         };
1563
1564                         uart1_rts: uart1-rts {
1565                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1566                         };
1567                 };
1568
1569                 uart2 {
1570                         uart2_xfer: uart2-xfer {
1571                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1572                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1573                         };
1574                         /* no rts / cts for uart2 */
1575                 };
1576
1577                 uart3 {
1578                         uart3_xfer: uart3-xfer {
1579                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1580                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1581                         };
1582
1583                         uart3_cts: uart3-cts {
1584                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1585                         };
1586
1587                         uart3_rts: uart3-rts {
1588                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1589                         };
1590                 };
1591
1592                 uart4 {
1593                         uart4_xfer: uart4-xfer {
1594                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1595                                                 <5 13 3 &pcfg_pull_none>;
1596                         };
1597
1598                         uart4_cts: uart4-cts {
1599                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1600                         };
1601
1602                         uart4_rts: uart4-rts {
1603                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1604                         };
1605                 };
1606
1607                 tsadc {
1608                         otp_gpio: otp-gpio {
1609                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1610                         };
1611
1612                         otp_out: otp-out {
1613                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1614                         };
1615                 };
1616
1617                 pwm0 {
1618                         pwm0_pin: pwm0-pin {
1619                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1620                         };
1621                 };
1622
1623                 pwm1 {
1624                         pwm1_pin: pwm1-pin {
1625                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1626                         };
1627                 };
1628
1629                 pwm2 {
1630                         pwm2_pin: pwm2-pin {
1631                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1632                         };
1633                 };
1634
1635                 pwm3 {
1636                         pwm3_pin: pwm3-pin {
1637                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1638                         };
1639                 };
1640
1641                 gmac {
1642                         rgmii_pins: rgmii-pins {
1643                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1644                                                 <3 31 3 &pcfg_pull_none>,
1645                                                 <3 26 3 &pcfg_pull_none>,
1646                                                 <3 27 3 &pcfg_pull_none>,
1647                                                 <3 28 3 &pcfg_pull_none_12ma>,
1648                                                 <3 29 3 &pcfg_pull_none_12ma>,
1649                                                 <3 24 3 &pcfg_pull_none_12ma>,
1650                                                 <3 25 3 &pcfg_pull_none_12ma>,
1651                                                 <4 0 3 &pcfg_pull_none>,
1652                                                 <4 5 3 &pcfg_pull_none>,
1653                                                 <4 6 3 &pcfg_pull_none>,
1654                                                 <4 9 3 &pcfg_pull_none_12ma>,
1655                                                 <4 4 3 &pcfg_pull_none_12ma>,
1656                                                 <4 1 3 &pcfg_pull_none>,
1657                                                 <4 3 3 &pcfg_pull_none>;
1658                         };
1659
1660                         rmii_pins: rmii-pins {
1661                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1662                                                 <3 31 3 &pcfg_pull_none>,
1663                                                 <3 28 3 &pcfg_pull_none>,
1664                                                 <3 29 3 &pcfg_pull_none>,
1665                                                 <4 0 3 &pcfg_pull_none>,
1666                                                 <4 5 3 &pcfg_pull_none>,
1667                                                 <4 4 3 &pcfg_pull_none>,
1668                                                 <4 1 3 &pcfg_pull_none>,
1669                                                 <4 2 3 &pcfg_pull_none>,
1670                                                 <4 3 3 &pcfg_pull_none>;
1671                         };
1672                 };
1673
1674                 spdif {
1675                         spdif_tx: spdif-tx {
1676                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1677                         };
1678                 };
1679         };
1680 };