arch/arm/boot/dts/rk3288.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/interrupt-controller/irq.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/pinctrl/rockchip.h>
   7 #include <dt-bindings/clock/rk3288-cru.h>
   8 #include <dt-bindings/power/rk3288-power.h>
   9 #include <dt-bindings/thermal/thermal.h>
  10 #include <dt-bindings/power/rk3288-power.h>
  11 #include <dt-bindings/soc/rockchip,boot-mode.h>
  12
  13 / {
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         compatible = "rockchip,rk3288";
  18
  19         interrupt-parent = <&gic>;
  20
  21         aliases {
  22                 ethernet0 = &gmac;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 mshc0 = &emmc;
  30                 mshc1 = &sdmmc;
  31                 mshc2 = &sdio0;
  32                 mshc3 = &sdio1;
  33                 serial0 = &uart0;
  34                 serial1 = &uart1;
  35                 serial2 = &uart2;
  36                 serial3 = &uart3;
  37                 serial4 = &uart4;
  38                 spi0 = &spi0;
  39                 spi1 = &spi1;
  40                 spi2 = &spi2;
  41         };
  42
  43         arm-pmu {
  44                 compatible = "arm,cortex-a12-pmu";
  45                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  46                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  47                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  48                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  49                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  50         };
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55                 enable-method = "rockchip,rk3066-smp";
  56                 rockchip,pmu = <&pmu>;
  57
  58                 cpu0: cpu@500 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a12";
  61                         reg = <0x500>;
  62                         resets = <&cru SRST_CORE0>;
  63                         operating-points-v2 = <&cpu_opp_table>;
  64                         #cooling-cells = <2>; /* min followed by max */
  65                         clock-latency = <40000>;
  66                         clocks = <&cru ARMCLK>;
  67                         dynamic-power-coefficient = <370>;
  68                 };
  69                 cpu1: cpu@501 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a12";
  72                         reg = <0x501>;
  73                         resets = <&cru SRST_CORE1>;
  74                         operating-points-v2 = <&cpu_opp_table>;
  75                         #cooling-cells = <2>; /* min followed by max */
  76                         clock-latency = <40000>;
  77                         clocks = <&cru ARMCLK>;
  78                         dynamic-power-coefficient = <370>;
  79                 };
  80                 cpu2: cpu@502 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a12";
  83                         reg = <0x502>;
  84                         resets = <&cru SRST_CORE2>;
  85                         operating-points-v2 = <&cpu_opp_table>;
  86                         #cooling-cells = <2>; /* min followed by max */
  87                         clock-latency = <40000>;
  88                         clocks = <&cru ARMCLK>;
  89                         dynamic-power-coefficient = <370>;
  90                 };
  91                 cpu3: cpu@503 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a12";
  94                         reg = <0x503>;
  95                         resets = <&cru SRST_CORE3>;
  96                         operating-points-v2 = <&cpu_opp_table>;
  97                         #cooling-cells = <2>; /* min followed by max */
  98                         clock-latency = <40000>;
  99                         clocks = <&cru ARMCLK>;
 100                         dynamic-power-coefficient = <370>;
 101                 };
 102         };
 103
 104         cpu_opp_table: cpu-opp-table {
 105                 compatible = "operating-points-v2";
 106                 opp-shared;
 107
 108                 opp-126000000 {
 109                         opp-hz = /bits/ 64 <126000000>;
 110                         opp-microvolt = <900000>;
 111                 };
 112                 opp-216000000 {
 113                         opp-hz = /bits/ 64 <216000000>;
 114                         opp-microvolt = <900000>;
 115                 };
 116                 opp-312000000 {
 117                         opp-hz = /bits/ 64 <312000000>;
 118                         opp-microvolt = <900000>;
 119                 };
 120                 opp-408000000 {
 121                         opp-hz = /bits/ 64 <408000000>;
 122                         opp-microvolt = <900000>;
 123                 };
 124                 opp-600000000 {
 125                         opp-hz = /bits/ 64 <600000000>;
 126                         opp-microvolt = <900000>;
 127                 };
 128                 opp-696000000 {
 129                         opp-hz = /bits/ 64 <696000000>;
 130                         opp-microvolt = <950000>;
 131                 };
 132                 opp-816000000 {
 133                         opp-hz = /bits/ 64 <816000000>;
 134                         opp-microvolt = <1000000>;
 135                 };
 136                 opp-1008000000 {
 137                         opp-hz = /bits/ 64 <1008000000>;
 138                         opp-microvolt = <1050000>;
 139                 };
 140                 opp-1200000000 {
 141                         opp-hz = /bits/ 64 <1200000000>;
 142                         opp-microvolt = <1100000>;
 143                 };
 144                 opp-1416000000 {
 145                         opp-hz = /bits/ 64 <1416000000>;
 146                         opp-microvolt = <1200000>;
 147                 };
 148                 opp-1512000000 {
 149                         opp-hz = /bits/ 64 <1512000000>;
 150                         opp-microvolt = <1300000>;
 151                 };
 152                 opp-1608000000 {
 153                         opp-hz = /bits/ 64 <1608000000>;
 154                         opp-microvolt = <1350000>;
 155                 };
 156         };
 157
 158         amba {
 159                 compatible = "simple-bus";
 160                 #address-cells = <2>;
 161                 #size-cells = <2>;
 162                 ranges;
 163
 164                 dmac_peri: dma-controller@ff250000 {
 165                         compatible = "arm,pl330", "arm,primecell";
 166                         reg = <0x0 0xff250000 0x0 0x4000>;
 167                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 168                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 169                         #dma-cells = <1>;
 170                         arm,pl330-broken-no-flushp;
 171                         clocks = <&cru ACLK_DMAC2>;
 172                         clock-names = "apb_pclk";
 173                 };
 174
 175                 dmac_bus_ns: dma-controller@ff600000 {
 176                         compatible = "arm,pl330", "arm,primecell";
 177                         reg = <0x0 0xff600000 0x0 0x4000>;
 178                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 179                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 180                         #dma-cells = <1>;
 181                         arm,pl330-broken-no-flushp;
 182                         clocks = <&cru ACLK_DMAC1>;
 183                         clock-names = "apb_pclk";
 184                         status = "disabled";
 185                 };
 186
 187                 dmac_bus_s: dma-controller@ffb20000 {
 188                         compatible = "arm,pl330", "arm,primecell";
 189                         reg = <0x0 0xffb20000 0x0 0x4000>;
 190                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 191                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 192                         #dma-cells = <1>;
 193                         arm,pl330-broken-no-flushp;
 194                         clocks = <&cru ACLK_DMAC1>;
 195                         clock-names = "apb_pclk";
 196                 };
 197         };
 198
 199         reserved-memory {
 200                 #address-cells = <2>;
 201                 #size-cells = <2>;
 202                 ranges;
 203
 204                 /*
 205                  * The rk3288 cannot use the memory area above 0xfe000000
 206                  * for dma operations for some reason. While there is
 207                  * probably a better solution available somewhere, we
 208                  * haven't found it yet and while devices with 2GB of ram
 209                  * are not affected, this issue prevents 4GB from booting.
 210                  * So to make these devices at least bootable, block
 211                  * this area for the time being until the real solution
 212                  * is found.
 213                  */
 214                 dma-unusable@fe000000 {
 215                         reg = <0x0 0xfe000000 0x0 0x1000000>;
 216                 };
 217         };
 218
 219         xin24m: oscillator {
 220                 compatible = "fixed-clock";
 221                 clock-frequency = <24000000>;
 222                 clock-output-names = "xin24m";
 223                 #clock-cells = <0>;
 224         };
 225
 226         timer {
 227                 compatible = "arm,armv7-timer";
 228                 arm,cpu-registers-not-fw-configured;
 229                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 230                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 231                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 232                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 233                 clock-frequency = <24000000>;
 234                 arm,no-tick-in-suspend;
 235         };
 236
 237         timer: timer@ff810000 {
 238                 compatible = "rockchip,rk3288-timer";
 239                 reg = <0x0 0xff810000 0x0 0x20>;
 240                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 241                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 242                 clock-names = "timer", "pclk";
 243         };
 244
 245         display-subsystem {
 246                 compatible = "rockchip,display-subsystem";
 247                 ports = <&vopl_out>, <&vopb_out>;
 248         };
 249
 250         sdmmc: dwmmc@ff0c0000 {
 251                 compatible = "rockchip,rk3288-dw-mshc";
 252                 max-frequency = <150000000>;
 253                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 254                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 255                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 256                 fifo-depth = <0x100>;
 257                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 258                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 259                 resets = <&cru SRST_MMC0>;
 260                 reset-names = "reset";
 261                 status = "disabled";
 262         };
 263
 264         sdio0: dwmmc@ff0d0000 {
 265                 compatible = "rockchip,rk3288-dw-mshc";
 266                 max-frequency = <150000000>;
 267                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 268                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 269                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 270                 fifo-depth = <0x100>;
 271                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 272                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 273                 resets = <&cru SRST_SDIO0>;
 274                 reset-names = "reset";
 275                 status = "disabled";
 276         };
 277
 278         sdio1: dwmmc@ff0e0000 {
 279                 compatible = "rockchip,rk3288-dw-mshc";
 280                 max-frequency = <150000000>;
 281                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 282                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 283                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 284                 fifo-depth = <0x100>;
 285                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 286                 reg = <0x0 0xff0e0000 0x0 0x4000>;
 287                 resets = <&cru SRST_SDIO1>;
 288                 reset-names = "reset";
 289                 status = "disabled";
 290         };
 291
 292         emmc: dwmmc@ff0f0000 {
 293                 compatible = "rockchip,rk3288-dw-mshc";
 294                 max-frequency = <150000000>;
 295                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 296                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 297                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 298                 fifo-depth = <0x100>;
 299                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 300                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 301                 resets = <&cru SRST_EMMC>;
 302                 reset-names = "reset";
 303                 status = "disabled";
 304         };
 305
 306         saradc: saradc@ff100000 {
 307                 compatible = "rockchip,saradc";
 308                 reg = <0x0 0xff100000 0x0 0x100>;
 309                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 310                 #io-channel-cells = <1>;
 311                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 312                 clock-names = "saradc", "apb_pclk";
 313                 resets = <&cru SRST_SARADC>;
 314                 reset-names = "saradc-apb";
 315                 status = "disabled";
 316         };
 317
 318         spi0: spi@ff110000 {
 319                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 320                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 321                 clock-names = "spiclk", "apb_pclk";
 322                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 323                 dma-names = "tx", "rx";
 324                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 325                 pinctrl-names = "default";
 326                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 327                 reg = <0x0 0xff110000 0x0 0x1000>;
 328                 #address-cells = <1>;
 329                 #size-cells = <0>;
 330                 status = "disabled";
 331         };
 332
 333         spi1: spi@ff120000 {
 334                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 335                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 336                 clock-names = "spiclk", "apb_pclk";
 337                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 338                 dma-names = "tx", "rx";
 339                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 340                 pinctrl-names = "default";
 341                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 342                 reg = <0x0 0xff120000 0x0 0x1000>;
 343                 #address-cells = <1>;
 344                 #size-cells = <0>;
 345                 status = "disabled";
 346         };
 347
 348         spi2: spi@ff130000 {
 349                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 350                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 351                 clock-names = "spiclk", "apb_pclk";
 352                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 353                 dma-names = "tx", "rx";
 354                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 355                 pinctrl-names = "default";
 356                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 357                 reg = <0x0 0xff130000 0x0 0x1000>;
 358                 #address-cells = <1>;
 359                 #size-cells = <0>;
 360                 status = "disabled";
 361         };
 362
 363         i2c1: i2c@ff140000 {
 364                 compatible = "rockchip,rk3288-i2c";
 365                 reg = <0x0 0xff140000 0x0 0x1000>;
 366                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 367                 #address-cells = <1>;
 368                 #size-cells = <0>;
 369                 clock-names = "i2c";
 370                 clocks = <&cru PCLK_I2C1>;
 371                 pinctrl-names = "default";
 372                 pinctrl-0 = <&i2c1_xfer>;
 373                 status = "disabled";
 374         };
 375
 376         i2c3: i2c@ff150000 {
 377                 compatible = "rockchip,rk3288-i2c";
 378                 reg = <0x0 0xff150000 0x0 0x1000>;
 379                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 380                 #address-cells = <1>;
 381                 #size-cells = <0>;
 382                 clock-names = "i2c";
 383                 clocks = <&cru PCLK_I2C3>;
 384                 pinctrl-names = "default";
 385                 pinctrl-0 = <&i2c3_xfer>;
 386                 status = "disabled";
 387         };
 388
 389         i2c4: i2c@ff160000 {
 390                 compatible = "rockchip,rk3288-i2c";
 391                 reg = <0x0 0xff160000 0x0 0x1000>;
 392                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 393                 #address-cells = <1>;
 394                 #size-cells = <0>;
 395                 clock-names = "i2c";
 396                 clocks = <&cru PCLK_I2C4>;
 397                 pinctrl-names = "default";
 398                 pinctrl-0 = <&i2c4_xfer>;
 399                 status = "disabled";
 400         };
 401
 402         i2c5: i2c@ff170000 {
 403                 compatible = "rockchip,rk3288-i2c";
 404                 reg = <0x0 0xff170000 0x0 0x1000>;
 405                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 406                 #address-cells = <1>;
 407                 #size-cells = <0>;
 408                 clock-names = "i2c";
 409                 clocks = <&cru PCLK_I2C5>;
 410                 pinctrl-names = "default";
 411                 pinctrl-0 = <&i2c5_xfer>;
 412                 status = "disabled";
 413         };
 414
 415         uart0: serial@ff180000 {
 416                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 417                 reg = <0x0 0xff180000 0x0 0x100>;
 418                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 419                 reg-shift = <2>;
 420                 reg-io-width = <4>;
 421                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 422                 clock-names = "baudclk", "apb_pclk";
 423                 pinctrl-names = "default";
 424                 pinctrl-0 = <&uart0_xfer>;
 425                 status = "disabled";
 426         };
 427
 428         uart1: serial@ff190000 {
 429                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 430                 reg = <0x0 0xff190000 0x0 0x100>;
 431                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 432                 reg-shift = <2>;
 433                 reg-io-width = <4>;
 434                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 435                 clock-names = "baudclk", "apb_pclk";
 436                 pinctrl-names = "default";
 437                 pinctrl-0 = <&uart1_xfer>;
 438                 status = "disabled";
 439         };
 440
 441         uart2: serial@ff690000 {
 442                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 443                 reg = <0x0 0xff690000 0x0 0x100>;
 444                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 445                 reg-shift = <2>;
 446                 reg-io-width = <4>;
 447                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 448                 clock-names = "baudclk", "apb_pclk";
 449                 pinctrl-names = "default";
 450                 pinctrl-0 = <&uart2_xfer>;
 451                 status = "disabled";
 452         };
 453
 454         uart3: serial@ff1b0000 {
 455                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 456                 reg = <0x0 0xff1b0000 0x0 0x100>;
 457                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 458                 reg-shift = <2>;
 459                 reg-io-width = <4>;
 460                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 461                 clock-names = "baudclk", "apb_pclk";
 462                 pinctrl-names = "default";
 463                 pinctrl-0 = <&uart3_xfer>;
 464                 status = "disabled";
 465         };
 466
 467         uart4: serial@ff1c0000 {
 468                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 469                 reg = <0x0 0xff1c0000 0x0 0x100>;
 470                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 471                 reg-shift = <2>;
 472                 reg-io-width = <4>;
 473                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 474                 clock-names = "baudclk", "apb_pclk";
 475                 pinctrl-names = "default";
 476                 pinctrl-0 = <&uart4_xfer>;
 477                 status = "disabled";
 478         };
 479
 480         thermal-zones {
 481                 reserve_thermal: reserve_thermal {
 482                         polling-delay-passive = <1000>; /* milliseconds */
 483                         polling-delay = <5000>; /* milliseconds */
 484
 485                         thermal-sensors = <&tsadc 0>;
 486                 };
 487
 488                 cpu_thermal: cpu_thermal {
 489                         polling-delay-passive = <100>; /* milliseconds */
 490                         polling-delay = <5000>; /* milliseconds */
 491
 492                         thermal-sensors = <&tsadc 1>;
 493
 494                         trips {
 495                                 cpu_alert0: cpu_alert0 {
 496                                         temperature = <70000>; /* millicelsius */
 497                                         hysteresis = <2000>; /* millicelsius */
 498                                         type = "passive";
 499                                 };
 500                                 cpu_alert1: cpu_alert1 {
 501                                         temperature = <75000>; /* millicelsius */
 502                                         hysteresis = <2000>; /* millicelsius */
 503                                         type = "passive";
 504                                 };
 505                                 cpu_crit: cpu_crit {
 506                                         temperature = <90000>; /* millicelsius */
 507                                         hysteresis = <2000>; /* millicelsius */
 508                                         type = "critical";
 509                                 };
 510                         };
 511
 512                         cooling-maps {
 513                                 map0 {
 514                                         trip = <&cpu_alert0>;
 515                                         cooling-device =
 516                                                 <&cpu0 THERMAL_NO_LIMIT 6>,
 517                                                 <&cpu1 THERMAL_NO_LIMIT 6>,
 518                                                 <&cpu2 THERMAL_NO_LIMIT 6>,
 519                                                 <&cpu3 THERMAL_NO_LIMIT 6>;
 520                                 };
 521                                 map1 {
 522                                         trip = <&cpu_alert1>;
 523                                         cooling-device =
 524                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 525                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 526                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 527                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 528                                 };
 529                         };
 530                 };
 531
 532                 gpu_thermal: gpu_thermal {
 533                         polling-delay-passive = <100>; /* milliseconds */
 534                         polling-delay = <5000>; /* milliseconds */
 535
 536                         thermal-sensors = <&tsadc 2>;
 537
 538                         trips {
 539                                 gpu_alert0: gpu_alert0 {
 540                                         temperature = <70000>; /* millicelsius */
 541                                         hysteresis = <2000>; /* millicelsius */
 542                                         type = "passive";
 543                                 };
 544                                 gpu_crit: gpu_crit {
 545                                         temperature = <90000>; /* millicelsius */
 546                                         hysteresis = <2000>; /* millicelsius */
 547                                         type = "critical";
 548                                 };
 549                         };
 550
 551                         cooling-maps {
 552                                 map0 {
 553                                         trip = <&gpu_alert0>;
 554                                         cooling-device =
 555                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 556                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 557                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 558                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 559                                 };
 560                         };
 561                 };
 562         };
 563
 564         tsadc: tsadc@ff280000 {
 565                 compatible = "rockchip,rk3288-tsadc";
 566                 reg = <0x0 0xff280000 0x0 0x100>;
 567                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 568                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 569                 clock-names = "tsadc", "apb_pclk";
 570                 resets = <&cru SRST_TSADC>;
 571                 reset-names = "tsadc-apb";
 572                 pinctrl-names = "init", "default", "sleep";
 573                 pinctrl-0 = <&otp_gpio>;
 574                 pinctrl-1 = <&otp_out>;
 575                 pinctrl-2 = <&otp_gpio>;
 576                 #thermal-sensor-cells = <1>;
 577                 rockchip,grf = <&grf>;
 578                 rockchip,hw-tshut-temp = <95000>;
 579                 status = "disabled";
 580         };
 581
 582         gmac: ethernet@ff290000 {
 583                 compatible = "rockchip,rk3288-gmac";
 584                 reg = <0x0 0xff290000 0x0 0x10000>;
 585                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 586                                 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 587                 interrupt-names = "macirq", "eth_wake_irq";
 588                 rockchip,grf = <&grf>;
 589                 clocks = <&cru SCLK_MAC>,
 590                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 591                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 592                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 593                 clock-names = "stmmaceth",
 594                         "mac_clk_rx", "mac_clk_tx",
 595                         "clk_mac_ref", "clk_mac_refout",
 596                         "aclk_mac", "pclk_mac";
 597                 resets = <&cru SRST_MAC>;
 598                 reset-names = "stmmaceth";
 599                 status = "disabled";
 600         };
 601
 602         usb_host0_ehci: usb@ff500000 {
 603                 compatible = "generic-ehci";
 604                 reg = <0x0 0xff500000 0x0 0x100>;
 605                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 606                 clocks = <&cru HCLK_USBHOST0>;
 607                 clock-names = "usbhost";
 608                 phys = <&usbphy1>;
 609                 phy-names = "usb";
 610                 status = "disabled";
 611         };
 612
 613         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 614
 615         usb_host1: usb@ff540000 {
 616                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 617                                 "snps,dwc2";
 618                 reg = <0x0 0xff540000 0x0 0x40000>;
 619                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 620                 clocks = <&cru HCLK_USBHOST1>;
 621                 clock-names = "otg";
 622                 dr_mode = "host";
 623                 phys = <&usbphy2>;
 624                 phy-names = "usb2-phy";
 625                 snps,reset-phy-on-wake;
 626                 status = "disabled";
 627         };
 628
 629         usb_otg: usb@ff580000 {
 630                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 631                                 "snps,dwc2";
 632                 reg = <0x0 0xff580000 0x0 0x40000>;
 633                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 634                 clocks = <&cru HCLK_OTG0>;
 635                 clock-names = "otg";
 636                 dr_mode = "otg";
 637                 g-np-tx-fifo-size = <16>;
 638                 g-rx-fifo-size = <275>;
 639                 g-tx-fifo-size = <256 128 128 64 64 32>;
 640                 phys = <&usbphy0>;
 641                 phy-names = "usb2-phy";
 642                 status = "disabled";
 643         };
 644
 645         usb_hsic: usb@ff5c0000 {
 646                 compatible = "generic-ehci";
 647                 reg = <0x0 0xff5c0000 0x0 0x100>;
 648                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 649                 clocks = <&cru HCLK_HSIC>;
 650                 clock-names = "usbhost";
 651                 status = "disabled";
 652         };
 653
 654         i2c0: i2c@ff650000 {
 655                 compatible = "rockchip,rk3288-i2c";
 656                 reg = <0x0 0xff650000 0x0 0x1000>;
 657                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 658                 #address-cells = <1>;
 659                 #size-cells = <0>;
 660                 clock-names = "i2c";
 661                 clocks = <&cru PCLK_I2C0>;
 662                 pinctrl-names = "default";
 663                 pinctrl-0 = <&i2c0_xfer>;
 664                 status = "disabled";
 665         };
 666
 667         i2c2: i2c@ff660000 {
 668                 compatible = "rockchip,rk3288-i2c";
 669                 reg = <0x0 0xff660000 0x0 0x1000>;
 670                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 671                 #address-cells = <1>;
 672                 #size-cells = <0>;
 673                 clock-names = "i2c";
 674                 clocks = <&cru PCLK_I2C2>;
 675                 pinctrl-names = "default";
 676                 pinctrl-0 = <&i2c2_xfer>;
 677                 status = "disabled";
 678         };
 679
 680         pwm0: pwm@ff680000 {
 681                 compatible = "rockchip,rk3288-pwm";
 682                 reg = <0x0 0xff680000 0x0 0x10>;
 683                 #pwm-cells = <3>;
 684                 pinctrl-names = "default";
 685                 pinctrl-0 = <&pwm0_pin>;
 686                 clocks = <&cru PCLK_RKPWM>;
 687                 clock-names = "pwm";
 688                 status = "disabled";
 689         };
 690
 691         pwm1: pwm@ff680010 {
 692                 compatible = "rockchip,rk3288-pwm";
 693                 reg = <0x0 0xff680010 0x0 0x10>;
 694                 #pwm-cells = <3>;
 695                 pinctrl-names = "default";
 696                 pinctrl-0 = <&pwm1_pin>;
 697                 clocks = <&cru PCLK_RKPWM>;
 698                 clock-names = "pwm";
 699                 status = "disabled";
 700         };
 701
 702         pwm2: pwm@ff680020 {
 703                 compatible = "rockchip,rk3288-pwm";
 704                 reg = <0x0 0xff680020 0x0 0x10>;
 705                 #pwm-cells = <3>;
 706                 pinctrl-names = "default";
 707                 pinctrl-0 = <&pwm2_pin>;
 708                 clocks = <&cru PCLK_RKPWM>;
 709                 clock-names = "pwm";
 710                 status = "disabled";
 711         };
 712
 713         pwm3: pwm@ff680030 {
 714                 compatible = "rockchip,rk3288-pwm";
 715                 reg = <0x0 0xff680030 0x0 0x10>;
 716                 #pwm-cells = <2>;
 717                 pinctrl-names = "default";
 718                 pinctrl-0 = <&pwm3_pin>;
 719                 clocks = <&cru PCLK_RKPWM>;
 720                 clock-names = "pwm";
 721                 status = "disabled";
 722         };
 723
 724         bus_intmem@ff700000 {
 725                 compatible = "mmio-sram";
 726                 reg = <0x0 0xff700000 0x0 0x18000>;
 727                 #address-cells = <1>;
 728                 #size-cells = <1>;
 729                 ranges = <0 0x0 0xff700000 0x18000>;
 730                 smp-sram@0 {
 731                         compatible = "rockchip,rk3066-smp-sram";
 732                         reg = <0x00 0x10>;
 733                 };
 734         };
 735
 736         sram@ff720000 {
 737                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 738                 reg = <0x0 0xff720000 0x0 0x1000>;
 739         };
 740
 741         pmu: power-management@ff730000 {
 742                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 743                 reg = <0x0 0xff730000 0x0 0x100>;
 744
 745                 power: power-controller {
 746                         compatible = "rockchip,rk3288-power-controller";
 747                         #power-domain-cells = <1>;
 748                         #address-cells = <1>;
 749                         #size-cells = <0>;
 750
 751                         assigned-clocks = <&cru SCLK_EDP_24M>;
 752                         assigned-clock-parents = <&xin24m>;
 753
 754                         /*
 755                          * Note: Although SCLK_* are the working clocks
 756                          * of device without including on the NOC, needed for
 757                          * synchronous reset.
 758                          *
 759                          * The clocks on the which NOC:
 760                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 761                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 762                          * ACLK_RGA is on ACLK_RGA_NIU.
 763                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 764                          *
 765                          * Which clock are device clocks:
 766                          *      clocks          devices
 767                          *      *_IEP           IEP:Image Enhancement Processor
 768                          *      *_ISP           ISP:Image Signal Processing
 769                          *      *_VIP           VIP:Video Input Processor
 770                          *      *_VOP*          VOP:Visual Output Processor
 771                          *      *_RGA           RGA
 772                          *      *_EDP*          EDP
 773                          *      *_LVDS_*        LVDS
 774                          *      *_HDMI          HDMI
 775                          *      *_MIPI_*        MIPI
 776                          */
 777                         pd_vio@RK3288_PD_VIO {
 778                                 reg = <RK3288_PD_VIO>;
 779                                 clocks = <&cru ACLK_IEP>,
 780                                          <&cru ACLK_ISP>,
 781                                          <&cru ACLK_RGA>,
 782                                          <&cru ACLK_VIP>,
 783                                          <&cru ACLK_VOP0>,
 784                                          <&cru ACLK_VOP1>,
 785                                          <&cru DCLK_VOP0>,
 786                                          <&cru DCLK_VOP1>,
 787                                          <&cru HCLK_IEP>,
 788                                          <&cru HCLK_ISP>,
 789                                          <&cru HCLK_RGA>,
 790                                          <&cru HCLK_VIP>,
 791                                          <&cru HCLK_VOP0>,
 792                                          <&cru HCLK_VOP1>,
 793                                          <&cru PCLK_EDP_CTRL>,
 794                                          <&cru PCLK_HDMI_CTRL>,
 795                                          <&cru PCLK_LVDS_PHY>,
 796                                          <&cru PCLK_MIPI_CSI>,
 797                                          <&cru PCLK_MIPI_DSI0>,
 798                                          <&cru PCLK_MIPI_DSI1>,
 799                                          <&cru SCLK_EDP_24M>,
 800                                          <&cru SCLK_EDP>,
 801                                          <&cru SCLK_ISP_JPE>,
 802                                          <&cru SCLK_ISP>,
 803                                          <&cru SCLK_RGA>;
 804                                 pm_qos = <&qos_vio0_iep>,
 805                                          <&qos_vio1_vop>,
 806                                          <&qos_vio1_isp_w0>,
 807                                          <&qos_vio1_isp_w1>,
 808                                          <&qos_vio0_vop>,
 809                                          <&qos_vio0_vip>,
 810                                          <&qos_vio2_rga_r>,
 811                                          <&qos_vio2_rga_w>,
 812                                          <&qos_vio1_isp_r>;
 813                         };
 814
 815                         /*
 816                          * Note: The following 3 are HEVC(H.265) clocks,
 817                          * and on the ACLK_HEVC_NIU (NOC).
 818                          */
 819                         pd_hevc@RK3288_PD_HEVC {
 820                                 reg = <RK3288_PD_HEVC>;
 821                                 clocks = <&cru ACLK_HEVC>,
 822                                          <&cru SCLK_HEVC_CABAC>,
 823                                          <&cru SCLK_HEVC_CORE>;
 824                                 pm_qos = <&qos_hevc_r>,
 825                                          <&qos_hevc_w>;
 826                         };
 827
 828                         /*
 829                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 830                          * (video endecoder & decoder) clocks that on the
 831                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 832                          */
 833                         pd_video@RK3288_PD_VIDEO {
 834                                 reg = <RK3288_PD_VIDEO>;
 835                                 clocks = <&cru ACLK_VCODEC>,
 836                                          <&cru HCLK_VCODEC>;
 837                                 pm_qos = <&qos_video>;
 838                         };
 839
 840                         /*
 841                          * Note: ACLK_GPU is the GPU clock,
 842                          * and on the ACLK_GPU_NIU (NOC).
 843                          */
 844                         pd_gpu@RK3288_PD_GPU {
 845                                 reg = <RK3288_PD_GPU>;
 846                                 clocks = <&cru ACLK_GPU>;
 847                                 pm_qos = <&qos_gpu_r>,
 848                                          <&qos_gpu_w>;
 849                         };
 850                 };
 851
 852                 reboot-mode {
 853                         compatible = "syscon-reboot-mode";
 854                         offset = <0x94>;
 855                         mode-normal = <BOOT_NORMAL>;
 856                         mode-recovery = <BOOT_RECOVERY>;
 857                         mode-bootloader = <BOOT_FASTBOOT>;
 858                         mode-loader = <BOOT_BL_DOWNLOAD>;
 859                 };
 860         };
 861
 862         sgrf: syscon@ff740000 {
 863                 compatible = "rockchip,rk3288-sgrf", "syscon";
 864                 reg = <0x0 0xff740000 0x0 0x1000>;
 865         };
 866
 867         cru: clock-controller@ff760000 {
 868                 compatible = "rockchip,rk3288-cru";
 869                 reg = <0x0 0xff760000 0x0 0x1000>;
 870                 rockchip,grf = <&grf>;
 871                 #clock-cells = <1>;
 872                 #reset-cells = <1>;
 873                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 874                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 875                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 876                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 877                                   <&cru PCLK_PERI>;
 878                 assigned-clock-rates = <594000000>, <400000000>,
 879                                        <500000000>, <300000000>,
 880                                        <150000000>, <75000000>,
 881                                        <300000000>, <150000000>,
 882                                        <75000000>;
 883         };
 884
 885         grf: syscon@ff770000 {
 886                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 887                 reg = <0x0 0xff770000 0x0 0x1000>;
 888
 889                 edp_phy: edp-phy {
 890                         compatible = "rockchip,rk3288-dp-phy";
 891                         clocks = <&cru SCLK_EDP_24M>;
 892                         clock-names = "24m";
 893                         #phy-cells = <0>;
 894                         status = "disabled";
 895                 };
 896
 897                 io_domains: io-domains {
 898                         compatible = "rockchip,rk3288-io-voltage-domain";
 899                         status = "disabled";
 900                 };
 901
 902                 usbphy: usbphy {
 903                         compatible = "rockchip,rk3288-usb-phy";
 904                         #address-cells = <1>;
 905                         #size-cells = <0>;
 906                         status = "disabled";
 907
 908                         usbphy0: usb-phy@320 {
 909                                 #phy-cells = <0>;
 910                                 reg = <0x320>;
 911                                 clocks = <&cru SCLK_OTGPHY0>;
 912                                 clock-names = "phyclk";
 913                                 #clock-cells = <0>;
 914                                 resets = <&cru SRST_USBOTG_PHY>;
 915                                 reset-names = "phy-reset";
 916                         };
 917
 918                         usbphy1: usb-phy@334 {
 919                                 #phy-cells = <0>;
 920                                 reg = <0x334>;
 921                                 clocks = <&cru SCLK_OTGPHY1>;
 922                                 clock-names = "phyclk";
 923                                 #clock-cells = <0>;
 924                                 resets = <&cru SRST_USBHOST0_PHY>;
 925                                 reset-names = "phy-reset";
 926                         };
 927
 928                         usbphy2: usb-phy@348 {
 929                                 #phy-cells = <0>;
 930                                 reg = <0x348>;
 931                                 clocks = <&cru SCLK_OTGPHY2>;
 932                                 clock-names = "phyclk";
 933                                 #clock-cells = <0>;
 934                                 resets = <&cru SRST_USBHOST1_PHY>;
 935                                 reset-names = "phy-reset";
 936                         };
 937                 };
 938         };
 939
 940         wdt: watchdog@ff800000 {
 941                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 942                 reg = <0x0 0xff800000 0x0 0x100>;
 943                 clocks = <&cru PCLK_WDT>;
 944                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 945                 status = "disabled";
 946         };
 947
 948         spdif: sound@ff88b0000 {
 949                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 950                 reg = <0x0 0xff8b0000 0x0 0x10000>;
 951                 #sound-dai-cells = <0>;
 952                 clock-names = "hclk", "mclk";
 953                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 954                 dmas = <&dmac_bus_s 3>;
 955                 dma-names = "tx";
 956                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 957                 pinctrl-names = "default";
 958                 pinctrl-0 = <&spdif_tx>;
 959                 rockchip,grf = <&grf>;
 960                 status = "disabled";
 961         };
 962
 963         i2s: i2s@ff890000 {
 964                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 965                 reg = <0x0 0xff890000 0x0 0x10000>;
 966                 #sound-dai-cells = <0>;
 967                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 968                 #address-cells = <1>;
 969                 #size-cells = <0>;
 970                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 971                 dma-names = "tx", "rx";
 972                 clock-names = "i2s_hclk", "i2s_clk";
 973                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 974                 pinctrl-names = "default";
 975                 pinctrl-0 = <&i2s0_bus>;
 976                 rockchip,playback-channels = <8>;
 977                 rockchip,capture-channels = <2>;
 978                 status = "disabled";
 979         };
 980
 981         crypto: cypto-controller@ff8a0000 {
 982                 compatible = "rockchip,rk3288-crypto";
 983                 reg = <0x0 0xff8a0000 0x0 0x4000>;
 984                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 985                 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
 986                          <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
 987                 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
 988                 resets = <&cru SRST_CRYPTO>;
 989                 reset-names = "crypto-rst";
 990                 status = "okay";
 991         };
 992
 993         iep_mmu: iommu@ff900800 {
 994                 compatible = "rockchip,iommu";
 995                 reg = <0x0 0xff900800 0x0 0x40>;
 996                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 997                 interrupt-names = "iep_mmu";
 998                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 999                 clock-names = "aclk", "iface";
1000                 #iommu-cells = <0>;
1001                 status = "disabled";
1002         };
1003
1004         isp_mmu: iommu@ff914000 {
1005                 compatible = "rockchip,iommu";
1006                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1007                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1008                 interrupt-names = "isp_mmu";
1009                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1010                 clock-names = "aclk", "iface";
1011                 #iommu-cells = <0>;
1012                 rockchip,disable-mmu-reset;
1013                 status = "disabled";
1014         };
1015
1016         rga: rga@ff920000 {
1017                 compatible = "rockchip,rk3288-rga";
1018                 reg = <0x0 0xff920000 0x0 0x180>;
1019                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1020                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1021                 clock-names = "aclk", "hclk", "sclk";
1022                 power-domains = <&power RK3288_PD_VIO>;
1023                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1024                 reset-names = "core", "axi", "ahb";
1025         };
1026
1027         vopb: vop@ff930000 {
1028                 compatible = "rockchip,rk3288-vop";
1029                 reg = <0x0 0xff930000 0x0 0x19c>;
1030                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1031                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1032                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1033                 power-domains = <&power RK3288_PD_VIO>;
1034                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1035                 reset-names = "axi", "ahb", "dclk";
1036                 iommus = <&vopb_mmu>;
1037                 status = "disabled";
1038
1039                 vopb_out: port {
1040                         #address-cells = <1>;
1041                         #size-cells = <0>;
1042
1043                         vopb_out_hdmi: endpoint@0 {
1044                                 reg = <0>;
1045                                 remote-endpoint = <&hdmi_in_vopb>;
1046                         };
1047
1048                         vopb_out_edp: endpoint@1 {
1049                                 reg = <1>;
1050                                 remote-endpoint = <&edp_in_vopb>;
1051                         };
1052
1053                         vopb_out_mipi: endpoint@2 {
1054                                 reg = <2>;
1055                                 remote-endpoint = <&mipi_in_vopb>;
1056                         };
1057
1058                         vopb_out_lvds: endpoint@3 {
1059                                 reg = <3>;
1060                                 remote-endpoint = <&lvds_in_vopb>;
1061                         };
1062                 };
1063         };
1064
1065         vopb_mmu: iommu@ff930300 {
1066                 compatible = "rockchip,iommu";
1067                 reg = <0x0 0xff930300 0x0 0x100>;
1068                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1069                 interrupt-names = "vopb_mmu";
1070                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1071                 clock-names = "aclk", "iface";
1072                 power-domains = <&power RK3288_PD_VIO>;
1073                 #iommu-cells = <0>;
1074                 status = "disabled";
1075         };
1076
1077         vopl: vop@ff940000 {
1078                 compatible = "rockchip,rk3288-vop";
1079                 reg = <0x0 0xff940000 0x0 0x19c>;
1080                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1081                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1082                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1083                 power-domains = <&power RK3288_PD_VIO>;
1084                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1085                 reset-names = "axi", "ahb", "dclk";
1086                 iommus = <&vopl_mmu>;
1087                 status = "disabled";
1088
1089                 vopl_out: port {
1090                         #address-cells = <1>;
1091                         #size-cells = <0>;
1092
1093                         vopl_out_hdmi: endpoint@0 {
1094                                 reg = <0>;
1095                                 remote-endpoint = <&hdmi_in_vopl>;
1096                         };
1097
1098                         vopl_out_edp: endpoint@1 {
1099                                 reg = <1>;
1100                                 remote-endpoint = <&edp_in_vopl>;
1101                         };
1102
1103                         vopl_out_mipi: endpoint@2 {
1104                                 reg = <2>;
1105                                 remote-endpoint = <&mipi_in_vopl>;
1106                         };
1107
1108                         vopl_out_lvds: endpoint@3 {
1109                                 reg = <3>;
1110                                 remote-endpoint = <&lvds_in_vopl>;
1111                         };
1112                 };
1113         };
1114
1115         vopl_mmu: iommu@ff940300 {
1116                 compatible = "rockchip,iommu";
1117                 reg = <0x0 0xff940300 0x0 0x100>;
1118                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1119                 interrupt-names = "vopl_mmu";
1120                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1121                 clock-names = "aclk", "iface";
1122                 power-domains = <&power RK3288_PD_VIO>;
1123                 #iommu-cells = <0>;
1124                 status = "disabled";
1125         };
1126
1127         mipi_dsi: mipi@ff960000 {
1128                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1129                 reg = <0x0 0xff960000 0x0 0x4000>;
1130                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1131                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1132                 clock-names = "ref", "pclk";
1133                 power-domains = <&power RK3288_PD_VIO>;
1134                 rockchip,grf = <&grf>;
1135                 status = "disabled";
1136
1137                 ports {
1138                         mipi_in: port {
1139                                 #address-cells = <1>;
1140                                 #size-cells = <0>;
1141                                 mipi_in_vopb: endpoint@0 {
1142                                         reg = <0>;
1143                                         remote-endpoint = <&vopb_out_mipi>;
1144                                 };
1145                                 mipi_in_vopl: endpoint@1 {
1146                                         reg = <1>;
1147                                         remote-endpoint = <&vopl_out_mipi>;
1148                                 };
1149                         };
1150                 };
1151         };
1152
1153         lvds: lvds@ff96c000 {
1154                 compatible = "rockchip,rk3288-lvds";
1155                 reg = <0x0 0xff96c000 0x0 0x4000>;
1156                 clocks = <&cru PCLK_LVDS_PHY>;
1157                 clock-names = "pclk_lvds";
1158                 pinctrl-names = "lcdc";
1159                 pinctrl-0 = <&lcdc_ctl>;
1160                 power-domains = <&power RK3288_PD_VIO>;
1161                 rockchip,grf = <&grf>;
1162                 status = "disabled";
1163
1164                 ports {
1165                         #address-cells = <1>;
1166                         #size-cells = <0>;
1167
1168                         lvds_in: port@0 {
1169                                 reg = <0>;
1170
1171                                 #address-cells = <1>;
1172                                 #size-cells = <0>;
1173
1174                                 lvds_in_vopb: endpoint@0 {
1175                                         reg = <0>;
1176                                         remote-endpoint = <&vopb_out_lvds>;
1177                                 };
1178                                 lvds_in_vopl: endpoint@1 {
1179                                         reg = <1>;
1180                                         remote-endpoint = <&vopl_out_lvds>;
1181                                 };
1182                         };
1183                 };
1184         };
1185
1186         edp: dp@ff970000 {
1187                 compatible = "rockchip,rk3288-dp";
1188                 reg = <0x0 0xff970000 0x0 0x4000>;
1189                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1190                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1191                 clock-names = "dp", "pclk";
1192                 phys = <&edp_phy>;
1193                 phy-names = "dp";
1194                 resets = <&cru SRST_EDP>;
1195                 reset-names = "dp";
1196                 rockchip,grf = <&grf>;
1197                 status = "disabled";
1198
1199                 ports {
1200                         #address-cells = <1>;
1201                         #size-cells = <0>;
1202                         edp_in: port@0 {
1203                                 reg = <0>;
1204                                 #address-cells = <1>;
1205                                 #size-cells = <0>;
1206                                 edp_in_vopb: endpoint@0 {
1207                                         reg = <0>;
1208                                         remote-endpoint = <&vopb_out_edp>;
1209                                 };
1210                                 edp_in_vopl: endpoint@1 {
1211                                         reg = <1>;
1212                                         remote-endpoint = <&vopl_out_edp>;
1213                                 };
1214                         };
1215                 };
1216         };
1217
1218         hdmi: hdmi@ff980000 {
1219                 compatible = "rockchip,rk3288-dw-hdmi";
1220                 reg = <0x0 0xff980000 0x0 0x20000>;
1221                 reg-io-width = <4>;
1222                 #sound-dai-cells = <0>;
1223                 rockchip,grf = <&grf>;
1224                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1225                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1226                 clock-names = "iahb", "isfr", "cec";
1227                 power-domains = <&power RK3288_PD_VIO>;
1228                 status = "disabled";
1229
1230                 ports {
1231                         hdmi_in: port {
1232                                 #address-cells = <1>;
1233                                 #size-cells = <0>;
1234                                 hdmi_in_vopb: endpoint@0 {
1235                                         reg = <0>;
1236                                         remote-endpoint = <&vopb_out_hdmi>;
1237                                 };
1238                                 hdmi_in_vopl: endpoint@1 {
1239                                         reg = <1>;
1240                                         remote-endpoint = <&vopl_out_hdmi>;
1241                                 };
1242                         };
1243                 };
1244         };
1245
1246         vpu: video-codec@ff9a0000 {
1247                 compatible = "rockchip,rk3288-vpu";
1248                 reg = <0x0 0xff9a0000 0x0 0x800>;
1249                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1250                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1251                 interrupt-names = "vepu", "vdpu";
1252                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1253                 clock-names = "aclk", "hclk";
1254                 iommus = <&vpu_mmu>;
1255                 power-domains = <&power RK3288_PD_VIDEO>;
1256         };
1257
1258         vpu_mmu: iommu@ff9a0800 {
1259                 compatible = "rockchip,iommu";
1260                 reg = <0x0 0xff9a0800 0x0 0x100>;
1261                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1262                 interrupt-names = "vpu_mmu";
1263                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1264                 clock-names = "aclk", "iface";
1265                 #iommu-cells = <0>;
1266                 power-domains = <&power RK3288_PD_VIDEO>;
1267         };
1268
1269         hevc_mmu: iommu@ff9c0440 {
1270                 compatible = "rockchip,iommu";
1271                 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
1272                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1273                 interrupt-names = "hevc_mmu";
1274                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
1275                 clock-names = "aclk", "iface";
1276                 #iommu-cells = <0>;
1277                 status = "disabled";
1278         };
1279
1280         gpu: gpu@ffa30000 {
1281                 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1282                 reg = <0x0 0xffa30000 0x0 0x10000>;
1283                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1284                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1285                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1286                 interrupt-names = "job", "mmu", "gpu";
1287                 clocks = <&cru ACLK_GPU>;
1288                 operating-points-v2 = <&gpu_opp_table>;
1289                 power-domains = <&power RK3288_PD_GPU>;
1290                 status = "disabled";
1291         };
1292
1293         gpu_opp_table: gpu-opp-table {
1294                 compatible = "operating-points-v2";
1295
1296                 opp-100000000 {
1297                         opp-hz = /bits/ 64 <100000000>;
1298                         opp-microvolt = <950000>;
1299                 };
1300                 opp-200000000 {
1301                         opp-hz = /bits/ 64 <200000000>;
1302                         opp-microvolt = <950000>;
1303                 };
1304                 opp-300000000 {
1305                         opp-hz = /bits/ 64 <300000000>;
1306                         opp-microvolt = <1000000>;
1307                 };
1308                 opp-400000000 {
1309                         opp-hz = /bits/ 64 <400000000>;
1310                         opp-microvolt = <1100000>;
1311                 };
1312                 opp-500000000 {
1313                         opp-hz = /bits/ 64 <500000000>;
1314                         opp-microvolt = <1200000>;
1315                 };
1316                 opp-600000000 {
1317                         opp-hz = /bits/ 64 <600000000>;
1318                         opp-microvolt = <1250000>;
1319                 };
1320         };
1321
1322         qos_gpu_r: qos@ffaa0000 {
1323                 compatible = "syscon";
1324                 reg = <0x0 0xffaa0000 0x0 0x20>;
1325         };
1326
1327         qos_gpu_w: qos@ffaa0080 {
1328                 compatible = "syscon";
1329                 reg = <0x0 0xffaa0080 0x0 0x20>;
1330         };
1331
1332         qos_vio1_vop: qos@ffad0000 {
1333                 compatible = "syscon";
1334                 reg = <0x0 0xffad0000 0x0 0x20>;
1335         };
1336
1337         qos_vio1_isp_w0: qos@ffad0100 {
1338                 compatible = "syscon";
1339                 reg = <0x0 0xffad0100 0x0 0x20>;
1340         };
1341
1342         qos_vio1_isp_w1: qos@ffad0180 {
1343                 compatible = "syscon";
1344                 reg = <0x0 0xffad0180 0x0 0x20>;
1345         };
1346
1347         qos_vio0_vop: qos@ffad0400 {
1348                 compatible = "syscon";
1349                 reg = <0x0 0xffad0400 0x0 0x20>;
1350         };
1351
1352         qos_vio0_vip: qos@ffad0480 {
1353                 compatible = "syscon";
1354                 reg = <0x0 0xffad0480 0x0 0x20>;
1355         };
1356
1357         qos_vio0_iep: qos@ffad0500 {
1358                 compatible = "syscon";
1359                 reg = <0x0 0xffad0500 0x0 0x20>;
1360         };
1361
1362         qos_vio2_rga_r: qos@ffad0800 {
1363                 compatible = "syscon";
1364                 reg = <0x0 0xffad0800 0x0 0x20>;
1365         };
1366
1367         qos_vio2_rga_w: qos@ffad0880 {
1368                 compatible = "syscon";
1369                 reg = <0x0 0xffad0880 0x0 0x20>;
1370         };
1371
1372         qos_vio1_isp_r: qos@ffad0900 {
1373                 compatible = "syscon";
1374                 reg = <0x0 0xffad0900 0x0 0x20>;
1375         };
1376
1377         qos_video: qos@ffae0000 {
1378                 compatible = "syscon";
1379                 reg = <0x0 0xffae0000 0x0 0x20>;
1380         };
1381
1382         qos_hevc_r: qos@ffaf0000 {
1383                 compatible = "syscon";
1384                 reg = <0x0 0xffaf0000 0x0 0x20>;
1385         };
1386
1387         qos_hevc_w: qos@ffaf0080 {
1388                 compatible = "syscon";
1389                 reg = <0x0 0xffaf0080 0x0 0x20>;
1390         };
1391
1392         efuse: efuse@ffb40000 {
1393                 compatible = "rockchip,rk3288-efuse";
1394                 reg = <0x0 0xffb40000 0x0 0x20>;
1395                 #address-cells = <1>;
1396                 #size-cells = <1>;
1397                 clocks = <&cru PCLK_EFUSE256>;
1398                 clock-names = "pclk_efuse";
1399
1400                 cpu_leakage: cpu_leakage@17 {
1401                         reg = <0x17 0x1>;
1402                 };
1403         };
1404
1405         gic: interrupt-controller@ffc01000 {
1406                 compatible = "arm,gic-400";
1407                 interrupt-controller;
1408                 #interrupt-cells = <3>;
1409                 #address-cells = <0>;
1410
1411                 reg = <0x0 0xffc01000 0x0 0x1000>,
1412                       <0x0 0xffc02000 0x0 0x2000>,
1413                       <0x0 0xffc04000 0x0 0x2000>,
1414                       <0x0 0xffc06000 0x0 0x2000>;
1415                 interrupts = <GIC_PPI 9 0xf04>;
1416         };
1417
1418         pinctrl: pinctrl {
1419                 compatible = "rockchip,rk3288-pinctrl";
1420                 rockchip,grf = <&grf>;
1421                 rockchip,pmu = <&pmu>;
1422                 #address-cells = <2>;
1423                 #size-cells = <2>;
1424                 ranges;
1425
1426                 gpio0: gpio0@ff750000 {
1427                         compatible = "rockchip,gpio-bank";
1428                         reg = <0x0 0xff750000 0x0 0x100>;
1429                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1430                         clocks = <&cru PCLK_GPIO0>;
1431
1432                         gpio-controller;
1433                         #gpio-cells = <2>;
1434
1435                         interrupt-controller;
1436                         #interrupt-cells = <2>;
1437                 };
1438
1439                 gpio1: gpio1@ff780000 {
1440                         compatible = "rockchip,gpio-bank";
1441                         reg = <0x0 0xff780000 0x0 0x100>;
1442                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1443                         clocks = <&cru PCLK_GPIO1>;
1444
1445                         gpio-controller;
1446                         #gpio-cells = <2>;
1447
1448                         interrupt-controller;
1449                         #interrupt-cells = <2>;
1450                 };
1451
1452                 gpio2: gpio2@ff790000 {
1453                         compatible = "rockchip,gpio-bank";
1454                         reg = <0x0 0xff790000 0x0 0x100>;
1455                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1456                         clocks = <&cru PCLK_GPIO2>;
1457
1458                         gpio-controller;
1459                         #gpio-cells = <2>;
1460
1461                         interrupt-controller;
1462                         #interrupt-cells = <2>;
1463                 };
1464
1465                 gpio3: gpio3@ff7a0000 {
1466                         compatible = "rockchip,gpio-bank";
1467                         reg = <0x0 0xff7a0000 0x0 0x100>;
1468                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1469                         clocks = <&cru PCLK_GPIO3>;
1470
1471                         gpio-controller;
1472                         #gpio-cells = <2>;
1473
1474                         interrupt-controller;
1475                         #interrupt-cells = <2>;
1476                 };
1477
1478                 gpio4: gpio4@ff7b0000 {
1479                         compatible = "rockchip,gpio-bank";
1480                         reg = <0x0 0xff7b0000 0x0 0x100>;
1481                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1482                         clocks = <&cru PCLK_GPIO4>;
1483
1484                         gpio-controller;
1485                         #gpio-cells = <2>;
1486
1487                         interrupt-controller;
1488                         #interrupt-cells = <2>;
1489                 };
1490
1491                 gpio5: gpio5@ff7c0000 {
1492                         compatible = "rockchip,gpio-bank";
1493                         reg = <0x0 0xff7c0000 0x0 0x100>;
1494                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1495                         clocks = <&cru PCLK_GPIO5>;
1496
1497                         gpio-controller;
1498                         #gpio-cells = <2>;
1499
1500                         interrupt-controller;
1501                         #interrupt-cells = <2>;
1502                 };
1503
1504                 gpio6: gpio6@ff7d0000 {
1505                         compatible = "rockchip,gpio-bank";
1506                         reg = <0x0 0xff7d0000 0x0 0x100>;
1507                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1508                         clocks = <&cru PCLK_GPIO6>;
1509
1510                         gpio-controller;
1511                         #gpio-cells = <2>;
1512
1513                         interrupt-controller;
1514                         #interrupt-cells = <2>;
1515                 };
1516
1517                 gpio7: gpio7@ff7e0000 {
1518                         compatible = "rockchip,gpio-bank";
1519                         reg = <0x0 0xff7e0000 0x0 0x100>;
1520                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1521                         clocks = <&cru PCLK_GPIO7>;
1522
1523                         gpio-controller;
1524                         #gpio-cells = <2>;
1525
1526                         interrupt-controller;
1527                         #interrupt-cells = <2>;
1528                 };
1529
1530                 gpio8: gpio8@ff7f0000 {
1531                         compatible = "rockchip,gpio-bank";
1532                         reg = <0x0 0xff7f0000 0x0 0x100>;
1533                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1534                         clocks = <&cru PCLK_GPIO8>;
1535
1536                         gpio-controller;
1537                         #gpio-cells = <2>;
1538
1539                         interrupt-controller;
1540                         #interrupt-cells = <2>;
1541                 };
1542
1543                 hdmi {
1544                         hdmi_cec_c0: hdmi-cec-c0 {
1545                                 rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>;
1546                         };
1547
1548                         hdmi_cec_c7: hdmi-cec-c7 {
1549                                 rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>;
1550                         };
1551
1552                         hdmi_ddc: hdmi-ddc {
1553                                 rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>,
1554                                                 <7 RK_PC4 2 &pcfg_pull_none>;
1555                         };
1556                 };
1557
1558                 pcfg_pull_up: pcfg-pull-up {
1559                         bias-pull-up;
1560                 };
1561
1562                 pcfg_pull_down: pcfg-pull-down {
1563                         bias-pull-down;
1564                 };
1565
1566                 pcfg_pull_none: pcfg-pull-none {
1567                         bias-disable;
1568                 };
1569
1570                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1571                         bias-disable;
1572                         drive-strength = <12>;
1573                 };
1574
1575                 sleep {
1576                         global_pwroff: global-pwroff {
1577                                 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
1578                         };
1579
1580                         ddrio_pwroff: ddrio-pwroff {
1581                                 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
1582                         };
1583
1584                         ddr0_retention: ddr0-retention {
1585                                 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>;
1586                         };
1587
1588                         ddr1_retention: ddr1-retention {
1589                                 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
1590                         };
1591                 };
1592
1593                 edp {
1594                         edp_hpd: edp-hpd {
1595                                 rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>;
1596                         };
1597                 };
1598
1599                 i2c0 {
1600                         i2c0_xfer: i2c0-xfer {
1601                                 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>,
1602                                                 <0 RK_PC0 1 &pcfg_pull_none>;
1603                         };
1604                 };
1605
1606                 i2c1 {
1607                         i2c1_xfer: i2c1-xfer {
1608                                 rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>,
1609                                                 <8 RK_PA5 1 &pcfg_pull_none>;
1610                         };
1611                 };
1612
1613                 i2c2 {
1614                         i2c2_xfer: i2c2-xfer {
1615                                 rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>,
1616                                                 <6 RK_PB2 1 &pcfg_pull_none>;
1617                         };
1618                 };
1619
1620                 i2c3 {
1621                         i2c3_xfer: i2c3-xfer {
1622                                 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>,
1623                                                 <2 RK_PC1 1 &pcfg_pull_none>;
1624                         };
1625                 };
1626
1627                 i2c4 {
1628                         i2c4_xfer: i2c4-xfer {
1629                                 rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>,
1630                                                 <7 RK_PC2 1 &pcfg_pull_none>;
1631                         };
1632                 };
1633
1634                 i2c5 {
1635                         i2c5_xfer: i2c5-xfer {
1636                                 rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>,
1637                                                 <7 RK_PC4 1 &pcfg_pull_none>;
1638                         };
1639                 };
1640
1641                 i2s0 {
1642                         i2s0_bus: i2s0-bus {
1643                                 rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>,
1644                                                 <6 RK_PA1 1 &pcfg_pull_none>,
1645                                                 <6 RK_PA2 1 &pcfg_pull_none>,
1646                                                 <6 RK_PA3 1 &pcfg_pull_none>,
1647                                                 <6 RK_PA4 1 &pcfg_pull_none>,
1648                                                 <6 RK_PB0 1 &pcfg_pull_none>;
1649                         };
1650                 };
1651
1652                 lcdc {
1653                         lcdc_ctl: lcdc-ctl {
1654                                 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
1655                                                 <1 RK_PD1 1 &pcfg_pull_none>,
1656                                                 <1 RK_PD2 1 &pcfg_pull_none>,
1657                                                 <1 RK_PD3 1 &pcfg_pull_none>;
1658                         };
1659                 };
1660
1661                 sdmmc {
1662                         sdmmc_clk: sdmmc-clk {
1663                                 rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>;
1664                         };
1665
1666                         sdmmc_cmd: sdmmc-cmd {
1667                                 rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>;
1668                         };
1669
1670                         sdmmc_cd: sdmmc-cd {
1671                                 rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>;
1672                         };
1673
1674                         sdmmc_bus1: sdmmc-bus1 {
1675                                 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>;
1676                         };
1677
1678                         sdmmc_bus4: sdmmc-bus4 {
1679                                 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>,
1680                                                 <6 RK_PC1 1 &pcfg_pull_up>,
1681                                                 <6 RK_PC2 1 &pcfg_pull_up>,
1682                                                 <6 RK_PC3 1 &pcfg_pull_up>;
1683                         };
1684                 };
1685
1686                 sdio0 {
1687                         sdio0_bus1: sdio0-bus1 {
1688                                 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>;
1689                         };
1690
1691                         sdio0_bus4: sdio0-bus4 {
1692                                 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>,
1693                                                 <4 RK_PC5 1 &pcfg_pull_up>,
1694                                                 <4 RK_PC6 1 &pcfg_pull_up>,
1695                                                 <4 RK_PC7 1 &pcfg_pull_up>;
1696                         };
1697
1698                         sdio0_cmd: sdio0-cmd {
1699                                 rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>;
1700                         };
1701
1702                         sdio0_clk: sdio0-clk {
1703                                 rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>;
1704                         };
1705
1706                         sdio0_cd: sdio0-cd {
1707                                 rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>;
1708                         };
1709
1710                         sdio0_wp: sdio0-wp {
1711                                 rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>;
1712                         };
1713
1714                         sdio0_pwr: sdio0-pwr {
1715                                 rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>;
1716                         };
1717
1718                         sdio0_bkpwr: sdio0-bkpwr {
1719                                 rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>;
1720                         };
1721
1722                         sdio0_int: sdio0-int {
1723                                 rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>;
1724                         };
1725                 };
1726
1727                 sdio1 {
1728                         sdio1_bus1: sdio1-bus1 {
1729                                 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>;
1730                         };
1731
1732                         sdio1_bus4: sdio1-bus4 {
1733                                 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>,
1734                                                 <3 RK_PD1 4 &pcfg_pull_up>,
1735                                                 <3 RK_PD2 4 &pcfg_pull_up>,
1736                                                 <3 RK_PD3 4 &pcfg_pull_up>;
1737                         };
1738
1739                         sdio1_cd: sdio1-cd {
1740                                 rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>;
1741                         };
1742
1743                         sdio1_wp: sdio1-wp {
1744                                 rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>;
1745                         };
1746
1747                         sdio1_bkpwr: sdio1-bkpwr {
1748                                 rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>;
1749                         };
1750
1751                         sdio1_int: sdio1-int {
1752                                 rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>;
1753                         };
1754
1755                         sdio1_cmd: sdio1-cmd {
1756                                 rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>;
1757                         };
1758
1759                         sdio1_clk: sdio1-clk {
1760                                 rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>;
1761                         };
1762
1763                         sdio1_pwr: sdio1-pwr {
1764                                 rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>;
1765                         };
1766                 };
1767
1768                 emmc {
1769                         emmc_clk: emmc-clk {
1770                                 rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>;
1771                         };
1772
1773                         emmc_cmd: emmc-cmd {
1774                                 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>;
1775                         };
1776
1777                         emmc_pwr: emmc-pwr {
1778                                 rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>;
1779                         };
1780
1781                         emmc_bus1: emmc-bus1 {
1782                                 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>;
1783                         };
1784
1785                         emmc_bus4: emmc-bus4 {
1786                                 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
1787                                                 <3 RK_PA1 2 &pcfg_pull_up>,
1788                                                 <3 RK_PA2 2 &pcfg_pull_up>,
1789                                                 <3 RK_PA3 2 &pcfg_pull_up>;
1790                         };
1791
1792                         emmc_bus8: emmc-bus8 {
1793                                 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
1794                                                 <3 RK_PA1 2 &pcfg_pull_up>,
1795                                                 <3 RK_PA2 2 &pcfg_pull_up>,
1796                                                 <3 RK_PA3 2 &pcfg_pull_up>,
1797                                                 <3 RK_PA4 2 &pcfg_pull_up>,
1798                                                 <3 RK_PA5 2 &pcfg_pull_up>,
1799                                                 <3 RK_PA6 2 &pcfg_pull_up>,
1800                                                 <3 RK_PA7 2 &pcfg_pull_up>;
1801                         };
1802                 };
1803
1804                 spi0 {
1805                         spi0_clk: spi0-clk {
1806                                 rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>;
1807                         };
1808                         spi0_cs0: spi0-cs0 {
1809                                 rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>;
1810                         };
1811                         spi0_tx: spi0-tx {
1812                                 rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>;
1813                         };
1814                         spi0_rx: spi0-rx {
1815                                 rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>;
1816                         };
1817                         spi0_cs1: spi0-cs1 {
1818                                 rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>;
1819                         };
1820                 };
1821                 spi1 {
1822                         spi1_clk: spi1-clk {
1823                                 rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>;
1824                         };
1825                         spi1_cs0: spi1-cs0 {
1826                                 rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>;
1827                         };
1828                         spi1_rx: spi1-rx {
1829                                 rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>;
1830                         };
1831                         spi1_tx: spi1-tx {
1832                                 rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>;
1833                         };
1834                 };
1835
1836                 spi2 {
1837                         spi2_cs1: spi2-cs1 {
1838                                 rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>;
1839                         };
1840                         spi2_clk: spi2-clk {
1841                                 rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>;
1842                         };
1843                         spi2_cs0: spi2-cs0 {
1844                                 rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>;
1845                         };
1846                         spi2_rx: spi2-rx {
1847                                 rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>;
1848                         };
1849                         spi2_tx: spi2-tx {
1850                                 rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>;
1851                         };
1852                 };
1853
1854                 uart0 {
1855                         uart0_xfer: uart0-xfer {
1856                                 rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>,
1857                                                 <4 RK_PC1 1 &pcfg_pull_none>;
1858                         };
1859
1860                         uart0_cts: uart0-cts {
1861                                 rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>;
1862                         };
1863
1864                         uart0_rts: uart0-rts {
1865                                 rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>;
1866                         };
1867                 };
1868
1869                 uart1 {
1870                         uart1_xfer: uart1-xfer {
1871                                 rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>,
1872                                                 <5 RK_PB1 1 &pcfg_pull_none>;
1873                         };
1874
1875                         uart1_cts: uart1-cts {
1876                                 rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>;
1877                         };
1878
1879                         uart1_rts: uart1-rts {
1880                                 rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>;
1881                         };
1882                 };
1883
1884                 uart2 {
1885                         uart2_xfer: uart2-xfer {
1886                                 rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>,
1887                                                 <7 RK_PC7 1 &pcfg_pull_none>;
1888                         };
1889                         /* no rts / cts for uart2 */
1890                 };
1891
1892                 uart3 {
1893                         uart3_xfer: uart3-xfer {
1894                                 rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>,
1895                                                 <7 RK_PB0 1 &pcfg_pull_none>;
1896                         };
1897
1898                         uart3_cts: uart3-cts {
1899                                 rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>;
1900                         };
1901
1902                         uart3_rts: uart3-rts {
1903                                 rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>;
1904                         };
1905                 };
1906
1907                 uart4 {
1908                         uart4_xfer: uart4-xfer {
1909                                 rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>,
1910                                                 <5 RK_PB6 3 &pcfg_pull_none>;
1911                         };
1912
1913                         uart4_cts: uart4-cts {
1914                                 rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>;
1915                         };
1916
1917                         uart4_rts: uart4-rts {
1918                                 rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>;
1919                         };
1920                 };
1921
1922                 tsadc {
1923                         otp_gpio: otp-gpio {
1924                                 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1925                         };
1926
1927                         otp_out: otp-out {
1928                                 rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>;
1929                         };
1930                 };
1931
1932                 pwm0 {
1933                         pwm0_pin: pwm0-pin {
1934                                 rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>;
1935                         };
1936                 };
1937
1938                 pwm1 {
1939                         pwm1_pin: pwm1-pin {
1940                                 rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>;
1941                         };
1942                 };
1943
1944                 pwm2 {
1945                         pwm2_pin: pwm2-pin {
1946                                 rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>;
1947                         };
1948                 };
1949
1950                 pwm3 {
1951                         pwm3_pin: pwm3-pin {
1952                                 rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>;
1953                         };
1954                 };
1955
1956                 gmac {
1957                         rgmii_pins: rgmii-pins {
1958                                 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
1959                                                 <3 RK_PD7 3 &pcfg_pull_none>,
1960                                                 <3 RK_PD2 3 &pcfg_pull_none>,
1961                                                 <3 RK_PD3 3 &pcfg_pull_none>,
1962                                                 <3 RK_PD4 3 &pcfg_pull_none_12ma>,
1963                                                 <3 RK_PD5 3 &pcfg_pull_none_12ma>,
1964                                                 <3 RK_PD0 3 &pcfg_pull_none_12ma>,
1965                                                 <3 RK_PD1 3 &pcfg_pull_none_12ma>,
1966                                                 <4 RK_PA0 3 &pcfg_pull_none>,
1967                                                 <4 RK_PA5 3 &pcfg_pull_none>,
1968                                                 <4 RK_PA6 3 &pcfg_pull_none>,
1969                                                 <4 RK_PB1 3 &pcfg_pull_none_12ma>,
1970                                                 <4 RK_PA4 3 &pcfg_pull_none_12ma>,
1971                                                 <4 RK_PA1 3 &pcfg_pull_none>,
1972                                                 <4 RK_PA3 3 &pcfg_pull_none>;
1973                         };
1974
1975                         rmii_pins: rmii-pins {
1976                                 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
1977                                                 <3 RK_PD7 3 &pcfg_pull_none>,
1978                                                 <3 RK_PD4 3 &pcfg_pull_none>,
1979                                                 <3 RK_PD5 3 &pcfg_pull_none>,
1980                                                 <4 RK_PA0 3 &pcfg_pull_none>,
1981                                                 <4 RK_PA5 3 &pcfg_pull_none>,
1982                                                 <4 RK_PA4 3 &pcfg_pull_none>,
1983                                                 <4 RK_PA1 3 &pcfg_pull_none>,
1984                                                 <4 RK_PA2 3 &pcfg_pull_none>,
1985                                                 <4 RK_PA3 3 &pcfg_pull_none>;
1986                         };
1987                 };
1988
1989                 spdif {
1990                         spdif_tx: spdif-tx {
1991                                 rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>;
1992                         };
1993                 };
1994         };
1995 };