arch/arm/boot/dts/rk3288.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/interrupt-controller/irq.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/pinctrl/rockchip.h>
   7 #include <dt-bindings/clock/rk3288-cru.h>
   8 #include <dt-bindings/power/rk3288-power.h>
   9 #include <dt-bindings/thermal/thermal.h>
  10 #include <dt-bindings/power/rk3288-power.h>
  11 #include <dt-bindings/soc/rockchip,boot-mode.h>
  12
  13 / {
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         compatible = "rockchip,rk3288";
  18
  19         interrupt-parent = <&gic>;
  20
  21         aliases {
  22                 ethernet0 = &gmac;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 mshc0 = &emmc;
  30                 mshc1 = &sdmmc;
  31                 mshc2 = &sdio0;
  32                 mshc3 = &sdio1;
  33                 serial0 = &uart0;
  34                 serial1 = &uart1;
  35                 serial2 = &uart2;
  36                 serial3 = &uart3;
  37                 serial4 = &uart4;
  38                 spi0 = &spi0;
  39                 spi1 = &spi1;
  40                 spi2 = &spi2;
  41         };
  42
  43         arm-pmu {
  44                 compatible = "arm,cortex-a12-pmu";
  45                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  46                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  47                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  48                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  49                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  50         };
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55                 enable-method = "rockchip,rk3066-smp";
  56                 rockchip,pmu = <&pmu>;
  57
  58                 cpu0: cpu@500 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a12";
  61                         reg = <0x500>;
  62                         resets = <&cru SRST_CORE0>;
  63                         operating-points-v2 = <&cpu_opp_table>;
  64                         #cooling-cells = <2>; /* min followed by max */
  65                         clock-latency = <40000>;
  66                         clocks = <&cru ARMCLK>;
  67                         dynamic-power-coefficient = <370>;
  68                 };
  69                 cpu1: cpu@501 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a12";
  72                         reg = <0x501>;
  73                         resets = <&cru SRST_CORE1>;
  74                         operating-points-v2 = <&cpu_opp_table>;
  75                         #cooling-cells = <2>; /* min followed by max */
  76                         clock-latency = <40000>;
  77                         clocks = <&cru ARMCLK>;
  78                         dynamic-power-coefficient = <370>;
  79                 };
  80                 cpu2: cpu@502 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a12";
  83                         reg = <0x502>;
  84                         resets = <&cru SRST_CORE2>;
  85                         operating-points-v2 = <&cpu_opp_table>;
  86                         #cooling-cells = <2>; /* min followed by max */
  87                         clock-latency = <40000>;
  88                         clocks = <&cru ARMCLK>;
  89                         dynamic-power-coefficient = <370>;
  90                 };
  91                 cpu3: cpu@503 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a12";
  94                         reg = <0x503>;
  95                         resets = <&cru SRST_CORE3>;
  96                         operating-points-v2 = <&cpu_opp_table>;
  97                         #cooling-cells = <2>; /* min followed by max */
  98                         clock-latency = <40000>;
  99                         clocks = <&cru ARMCLK>;
 100                         dynamic-power-coefficient = <370>;
 101                 };
 102         };
 103
 104         cpu_opp_table: cpu-opp-table {
 105                 compatible = "operating-points-v2";
 106                 opp-shared;
 107
 108                 opp-126000000 {
 109                         opp-hz = /bits/ 64 <126000000>;
 110                         opp-microvolt = <900000>;
 111                 };
 112                 opp-216000000 {
 113                         opp-hz = /bits/ 64 <216000000>;
 114                         opp-microvolt = <900000>;
 115                 };
 116                 opp-312000000 {
 117                         opp-hz = /bits/ 64 <312000000>;
 118                         opp-microvolt = <900000>;
 119                 };
 120                 opp-408000000 {
 121                         opp-hz = /bits/ 64 <408000000>;
 122                         opp-microvolt = <900000>;
 123                 };
 124                 opp-600000000 {
 125                         opp-hz = /bits/ 64 <600000000>;
 126                         opp-microvolt = <900000>;
 127                 };
 128                 opp-696000000 {
 129                         opp-hz = /bits/ 64 <696000000>;
 130                         opp-microvolt = <950000>;
 131                 };
 132                 opp-816000000 {
 133                         opp-hz = /bits/ 64 <816000000>;
 134                         opp-microvolt = <1000000>;
 135                 };
 136                 opp-1008000000 {
 137                         opp-hz = /bits/ 64 <1008000000>;
 138                         opp-microvolt = <1050000>;
 139                 };
 140                 opp-1200000000 {
 141                         opp-hz = /bits/ 64 <1200000000>;
 142                         opp-microvolt = <1100000>;
 143                 };
 144                 opp-1416000000 {
 145                         opp-hz = /bits/ 64 <1416000000>;
 146                         opp-microvolt = <1200000>;
 147                 };
 148                 opp-1512000000 {
 149                         opp-hz = /bits/ 64 <1512000000>;
 150                         opp-microvolt = <1300000>;
 151                 };
 152                 opp-1608000000 {
 153                         opp-hz = /bits/ 64 <1608000000>;
 154                         opp-microvolt = <1350000>;
 155                 };
 156         };
 157
 158         amba {
 159                 compatible = "simple-bus";
 160                 #address-cells = <2>;
 161                 #size-cells = <2>;
 162                 ranges;
 163
 164                 dmac_peri: dma-controller@ff250000 {
 165                         compatible = "arm,pl330", "arm,primecell";
 166                         reg = <0x0 0xff250000 0x0 0x4000>;
 167                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 168                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 169                         #dma-cells = <1>;
 170                         arm,pl330-broken-no-flushp;
 171                         clocks = <&cru ACLK_DMAC2>;
 172                         clock-names = "apb_pclk";
 173                 };
 174
 175                 dmac_bus_ns: dma-controller@ff600000 {
 176                         compatible = "arm,pl330", "arm,primecell";
 177                         reg = <0x0 0xff600000 0x0 0x4000>;
 178                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 179                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 180                         #dma-cells = <1>;
 181                         arm,pl330-broken-no-flushp;
 182                         clocks = <&cru ACLK_DMAC1>;
 183                         clock-names = "apb_pclk";
 184                         status = "disabled";
 185                 };
 186
 187                 dmac_bus_s: dma-controller@ffb20000 {
 188                         compatible = "arm,pl330", "arm,primecell";
 189                         reg = <0x0 0xffb20000 0x0 0x4000>;
 190                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 191                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 192                         #dma-cells = <1>;
 193                         arm,pl330-broken-no-flushp;
 194                         clocks = <&cru ACLK_DMAC1>;
 195                         clock-names = "apb_pclk";
 196                 };
 197         };
 198
 199         reserved-memory {
 200                 #address-cells = <2>;
 201                 #size-cells = <2>;
 202                 ranges;
 203
 204                 /*
 205                  * The rk3288 cannot use the memory area above 0xfe000000
 206                  * for dma operations for some reason. While there is
 207                  * probably a better solution available somewhere, we
 208                  * haven't found it yet and while devices with 2GB of ram
 209                  * are not affected, this issue prevents 4GB from booting.
 210                  * So to make these devices at least bootable, block
 211                  * this area for the time being until the real solution
 212                  * is found.
 213                  */
 214                 dma-unusable@fe000000 {
 215                         reg = <0x0 0xfe000000 0x0 0x1000000>;
 216                 };
 217         };
 218
 219         xin24m: oscillator {
 220                 compatible = "fixed-clock";
 221                 clock-frequency = <24000000>;
 222                 clock-output-names = "xin24m";
 223                 #clock-cells = <0>;
 224         };
 225
 226         timer {
 227                 compatible = "arm,armv7-timer";
 228                 arm,cpu-registers-not-fw-configured;
 229                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 230                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 231                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 232                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 233                 clock-frequency = <24000000>;
 234         };
 235
 236         timer: timer@ff810000 {
 237                 compatible = "rockchip,rk3288-timer";
 238                 reg = <0x0 0xff810000 0x0 0x20>;
 239                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 240                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 241                 clock-names = "timer", "pclk";
 242         };
 243
 244         display-subsystem {
 245                 compatible = "rockchip,display-subsystem";
 246                 ports = <&vopl_out>, <&vopb_out>;
 247         };
 248
 249         sdmmc: dwmmc@ff0c0000 {
 250                 compatible = "rockchip,rk3288-dw-mshc";
 251                 max-frequency = <150000000>;
 252                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 253                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 254                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 255                 fifo-depth = <0x100>;
 256                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 257                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 258                 resets = <&cru SRST_MMC0>;
 259                 reset-names = "reset";
 260                 status = "disabled";
 261         };
 262
 263         sdio0: dwmmc@ff0d0000 {
 264                 compatible = "rockchip,rk3288-dw-mshc";
 265                 max-frequency = <150000000>;
 266                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 267                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 268                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 269                 fifo-depth = <0x100>;
 270                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 271                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 272                 resets = <&cru SRST_SDIO0>;
 273                 reset-names = "reset";
 274                 status = "disabled";
 275         };
 276
 277         sdio1: dwmmc@ff0e0000 {
 278                 compatible = "rockchip,rk3288-dw-mshc";
 279                 max-frequency = <150000000>;
 280                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 281                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 282                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 283                 fifo-depth = <0x100>;
 284                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 285                 reg = <0x0 0xff0e0000 0x0 0x4000>;
 286                 resets = <&cru SRST_SDIO1>;
 287                 reset-names = "reset";
 288                 status = "disabled";
 289         };
 290
 291         emmc: dwmmc@ff0f0000 {
 292                 compatible = "rockchip,rk3288-dw-mshc";
 293                 max-frequency = <150000000>;
 294                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 295                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 296                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 297                 fifo-depth = <0x100>;
 298                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 299                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 300                 resets = <&cru SRST_EMMC>;
 301                 reset-names = "reset";
 302                 status = "disabled";
 303         };
 304
 305         saradc: saradc@ff100000 {
 306                 compatible = "rockchip,saradc";
 307                 reg = <0x0 0xff100000 0x0 0x100>;
 308                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 309                 #io-channel-cells = <1>;
 310                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 311                 clock-names = "saradc", "apb_pclk";
 312                 resets = <&cru SRST_SARADC>;
 313                 reset-names = "saradc-apb";
 314                 status = "disabled";
 315         };
 316
 317         spi0: spi@ff110000 {
 318                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 319                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 320                 clock-names = "spiclk", "apb_pclk";
 321                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 322                 dma-names = "tx", "rx";
 323                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 324                 pinctrl-names = "default";
 325                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 326                 reg = <0x0 0xff110000 0x0 0x1000>;
 327                 #address-cells = <1>;
 328                 #size-cells = <0>;
 329                 status = "disabled";
 330         };
 331
 332         spi1: spi@ff120000 {
 333                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 334                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 335                 clock-names = "spiclk", "apb_pclk";
 336                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 337                 dma-names = "tx", "rx";
 338                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 339                 pinctrl-names = "default";
 340                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 341                 reg = <0x0 0xff120000 0x0 0x1000>;
 342                 #address-cells = <1>;
 343                 #size-cells = <0>;
 344                 status = "disabled";
 345         };
 346
 347         spi2: spi@ff130000 {
 348                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 349                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 350                 clock-names = "spiclk", "apb_pclk";
 351                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 352                 dma-names = "tx", "rx";
 353                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 354                 pinctrl-names = "default";
 355                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 356                 reg = <0x0 0xff130000 0x0 0x1000>;
 357                 #address-cells = <1>;
 358                 #size-cells = <0>;
 359                 status = "disabled";
 360         };
 361
 362         i2c1: i2c@ff140000 {
 363                 compatible = "rockchip,rk3288-i2c";
 364                 reg = <0x0 0xff140000 0x0 0x1000>;
 365                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 366                 #address-cells = <1>;
 367                 #size-cells = <0>;
 368                 clock-names = "i2c";
 369                 clocks = <&cru PCLK_I2C1>;
 370                 pinctrl-names = "default";
 371                 pinctrl-0 = <&i2c1_xfer>;
 372                 status = "disabled";
 373         };
 374
 375         i2c3: i2c@ff150000 {
 376                 compatible = "rockchip,rk3288-i2c";
 377                 reg = <0x0 0xff150000 0x0 0x1000>;
 378                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 379                 #address-cells = <1>;
 380                 #size-cells = <0>;
 381                 clock-names = "i2c";
 382                 clocks = <&cru PCLK_I2C3>;
 383                 pinctrl-names = "default";
 384                 pinctrl-0 = <&i2c3_xfer>;
 385                 status = "disabled";
 386         };
 387
 388         i2c4: i2c@ff160000 {
 389                 compatible = "rockchip,rk3288-i2c";
 390                 reg = <0x0 0xff160000 0x0 0x1000>;
 391                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 392                 #address-cells = <1>;
 393                 #size-cells = <0>;
 394                 clock-names = "i2c";
 395                 clocks = <&cru PCLK_I2C4>;
 396                 pinctrl-names = "default";
 397                 pinctrl-0 = <&i2c4_xfer>;
 398                 status = "disabled";
 399         };
 400
 401         i2c5: i2c@ff170000 {
 402                 compatible = "rockchip,rk3288-i2c";
 403                 reg = <0x0 0xff170000 0x0 0x1000>;
 404                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 405                 #address-cells = <1>;
 406                 #size-cells = <0>;
 407                 clock-names = "i2c";
 408                 clocks = <&cru PCLK_I2C5>;
 409                 pinctrl-names = "default";
 410                 pinctrl-0 = <&i2c5_xfer>;
 411                 status = "disabled";
 412         };
 413
 414         uart0: serial@ff180000 {
 415                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 416                 reg = <0x0 0xff180000 0x0 0x100>;
 417                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 418                 reg-shift = <2>;
 419                 reg-io-width = <4>;
 420                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 421                 clock-names = "baudclk", "apb_pclk";
 422                 pinctrl-names = "default";
 423                 pinctrl-0 = <&uart0_xfer>;
 424                 status = "disabled";
 425         };
 426
 427         uart1: serial@ff190000 {
 428                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 429                 reg = <0x0 0xff190000 0x0 0x100>;
 430                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 431                 reg-shift = <2>;
 432                 reg-io-width = <4>;
 433                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 434                 clock-names = "baudclk", "apb_pclk";
 435                 pinctrl-names = "default";
 436                 pinctrl-0 = <&uart1_xfer>;
 437                 status = "disabled";
 438         };
 439
 440         uart2: serial@ff690000 {
 441                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 442                 reg = <0x0 0xff690000 0x0 0x100>;
 443                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 444                 reg-shift = <2>;
 445                 reg-io-width = <4>;
 446                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 447                 clock-names = "baudclk", "apb_pclk";
 448                 pinctrl-names = "default";
 449                 pinctrl-0 = <&uart2_xfer>;
 450                 status = "disabled";
 451         };
 452
 453         uart3: serial@ff1b0000 {
 454                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 455                 reg = <0x0 0xff1b0000 0x0 0x100>;
 456                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 457                 reg-shift = <2>;
 458                 reg-io-width = <4>;
 459                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 460                 clock-names = "baudclk", "apb_pclk";
 461                 pinctrl-names = "default";
 462                 pinctrl-0 = <&uart3_xfer>;
 463                 status = "disabled";
 464         };
 465
 466         uart4: serial@ff1c0000 {
 467                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 468                 reg = <0x0 0xff1c0000 0x0 0x100>;
 469                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 470                 reg-shift = <2>;
 471                 reg-io-width = <4>;
 472                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 473                 clock-names = "baudclk", "apb_pclk";
 474                 pinctrl-names = "default";
 475                 pinctrl-0 = <&uart4_xfer>;
 476                 status = "disabled";
 477         };
 478
 479         thermal-zones {
 480                 reserve_thermal: reserve_thermal {
 481                         polling-delay-passive = <1000>; /* milliseconds */
 482                         polling-delay = <5000>; /* milliseconds */
 483
 484                         thermal-sensors = <&tsadc 0>;
 485                 };
 486
 487                 cpu_thermal: cpu_thermal {
 488                         polling-delay-passive = <100>; /* milliseconds */
 489                         polling-delay = <5000>; /* milliseconds */
 490
 491                         thermal-sensors = <&tsadc 1>;
 492
 493                         trips {
 494                                 cpu_alert0: cpu_alert0 {
 495                                         temperature = <70000>; /* millicelsius */
 496                                         hysteresis = <2000>; /* millicelsius */
 497                                         type = "passive";
 498                                 };
 499                                 cpu_alert1: cpu_alert1 {
 500                                         temperature = <75000>; /* millicelsius */
 501                                         hysteresis = <2000>; /* millicelsius */
 502                                         type = "passive";
 503                                 };
 504                                 cpu_crit: cpu_crit {
 505                                         temperature = <90000>; /* millicelsius */
 506                                         hysteresis = <2000>; /* millicelsius */
 507                                         type = "critical";
 508                                 };
 509                         };
 510
 511                         cooling-maps {
 512                                 map0 {
 513                                         trip = <&cpu_alert0>;
 514                                         cooling-device =
 515                                                 <&cpu0 THERMAL_NO_LIMIT 6>,
 516                                                 <&cpu1 THERMAL_NO_LIMIT 6>,
 517                                                 <&cpu2 THERMAL_NO_LIMIT 6>,
 518                                                 <&cpu3 THERMAL_NO_LIMIT 6>;
 519                                 };
 520                                 map1 {
 521                                         trip = <&cpu_alert1>;
 522                                         cooling-device =
 523                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 524                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 525                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 526                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 527                                 };
 528                         };
 529                 };
 530
 531                 gpu_thermal: gpu_thermal {
 532                         polling-delay-passive = <100>; /* milliseconds */
 533                         polling-delay = <5000>; /* milliseconds */
 534
 535                         thermal-sensors = <&tsadc 2>;
 536
 537                         trips {
 538                                 gpu_alert0: gpu_alert0 {
 539                                         temperature = <70000>; /* millicelsius */
 540                                         hysteresis = <2000>; /* millicelsius */
 541                                         type = "passive";
 542                                 };
 543                                 gpu_crit: gpu_crit {
 544                                         temperature = <90000>; /* millicelsius */
 545                                         hysteresis = <2000>; /* millicelsius */
 546                                         type = "critical";
 547                                 };
 548                         };
 549
 550                         cooling-maps {
 551                                 map0 {
 552                                         trip = <&gpu_alert0>;
 553                                         cooling-device =
 554                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 555                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 556                                                 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 557                                                 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 558                                 };
 559                         };
 560                 };
 561         };
 562
 563         tsadc: tsadc@ff280000 {
 564                 compatible = "rockchip,rk3288-tsadc";
 565                 reg = <0x0 0xff280000 0x0 0x100>;
 566                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 567                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 568                 clock-names = "tsadc", "apb_pclk";
 569                 resets = <&cru SRST_TSADC>;
 570                 reset-names = "tsadc-apb";
 571                 pinctrl-names = "init", "default", "sleep";
 572                 pinctrl-0 = <&otp_gpio>;
 573                 pinctrl-1 = <&otp_out>;
 574                 pinctrl-2 = <&otp_gpio>;
 575                 #thermal-sensor-cells = <1>;
 576                 rockchip,grf = <&grf>;
 577                 rockchip,hw-tshut-temp = <95000>;
 578                 status = "disabled";
 579         };
 580
 581         gmac: ethernet@ff290000 {
 582                 compatible = "rockchip,rk3288-gmac";
 583                 reg = <0x0 0xff290000 0x0 0x10000>;
 584                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 585                                 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 586                 interrupt-names = "macirq", "eth_wake_irq";
 587                 rockchip,grf = <&grf>;
 588                 clocks = <&cru SCLK_MAC>,
 589                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 590                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 591                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 592                 clock-names = "stmmaceth",
 593                         "mac_clk_rx", "mac_clk_tx",
 594                         "clk_mac_ref", "clk_mac_refout",
 595                         "aclk_mac", "pclk_mac";
 596                 resets = <&cru SRST_MAC>;
 597                 reset-names = "stmmaceth";
 598                 status = "disabled";
 599         };
 600
 601         usb_host0_ehci: usb@ff500000 {
 602                 compatible = "generic-ehci";
 603                 reg = <0x0 0xff500000 0x0 0x100>;
 604                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 605                 clocks = <&cru HCLK_USBHOST0>;
 606                 clock-names = "usbhost";
 607                 phys = <&usbphy1>;
 608                 phy-names = "usb";
 609                 status = "disabled";
 610         };
 611
 612         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 613
 614         usb_host1: usb@ff540000 {
 615                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 616                                 "snps,dwc2";
 617                 reg = <0x0 0xff540000 0x0 0x40000>;
 618                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 619                 clocks = <&cru HCLK_USBHOST1>;
 620                 clock-names = "otg";
 621                 dr_mode = "host";
 622                 phys = <&usbphy2>;
 623                 phy-names = "usb2-phy";
 624                 snps,reset-phy-on-wake;
 625                 status = "disabled";
 626         };
 627
 628         usb_otg: usb@ff580000 {
 629                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 630                                 "snps,dwc2";
 631                 reg = <0x0 0xff580000 0x0 0x40000>;
 632                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 633                 clocks = <&cru HCLK_OTG0>;
 634                 clock-names = "otg";
 635                 dr_mode = "otg";
 636                 g-np-tx-fifo-size = <16>;
 637                 g-rx-fifo-size = <275>;
 638                 g-tx-fifo-size = <256 128 128 64 64 32>;
 639                 phys = <&usbphy0>;
 640                 phy-names = "usb2-phy";
 641                 status = "disabled";
 642         };
 643
 644         usb_hsic: usb@ff5c0000 {
 645                 compatible = "generic-ehci";
 646                 reg = <0x0 0xff5c0000 0x0 0x100>;
 647                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 648                 clocks = <&cru HCLK_HSIC>;
 649                 clock-names = "usbhost";
 650                 status = "disabled";
 651         };
 652
 653         i2c0: i2c@ff650000 {
 654                 compatible = "rockchip,rk3288-i2c";
 655                 reg = <0x0 0xff650000 0x0 0x1000>;
 656                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 657                 #address-cells = <1>;
 658                 #size-cells = <0>;
 659                 clock-names = "i2c";
 660                 clocks = <&cru PCLK_I2C0>;
 661                 pinctrl-names = "default";
 662                 pinctrl-0 = <&i2c0_xfer>;
 663                 status = "disabled";
 664         };
 665
 666         i2c2: i2c@ff660000 {
 667                 compatible = "rockchip,rk3288-i2c";
 668                 reg = <0x0 0xff660000 0x0 0x1000>;
 669                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 670                 #address-cells = <1>;
 671                 #size-cells = <0>;
 672                 clock-names = "i2c";
 673                 clocks = <&cru PCLK_I2C2>;
 674                 pinctrl-names = "default";
 675                 pinctrl-0 = <&i2c2_xfer>;
 676                 status = "disabled";
 677         };
 678
 679         pwm0: pwm@ff680000 {
 680                 compatible = "rockchip,rk3288-pwm";
 681                 reg = <0x0 0xff680000 0x0 0x10>;
 682                 #pwm-cells = <3>;
 683                 pinctrl-names = "default";
 684                 pinctrl-0 = <&pwm0_pin>;
 685                 clocks = <&cru PCLK_RKPWM>;
 686                 clock-names = "pwm";
 687                 status = "disabled";
 688         };
 689
 690         pwm1: pwm@ff680010 {
 691                 compatible = "rockchip,rk3288-pwm";
 692                 reg = <0x0 0xff680010 0x0 0x10>;
 693                 #pwm-cells = <3>;
 694                 pinctrl-names = "default";
 695                 pinctrl-0 = <&pwm1_pin>;
 696                 clocks = <&cru PCLK_RKPWM>;
 697                 clock-names = "pwm";
 698                 status = "disabled";
 699         };
 700
 701         pwm2: pwm@ff680020 {
 702                 compatible = "rockchip,rk3288-pwm";
 703                 reg = <0x0 0xff680020 0x0 0x10>;
 704                 #pwm-cells = <3>;
 705                 pinctrl-names = "default";
 706                 pinctrl-0 = <&pwm2_pin>;
 707                 clocks = <&cru PCLK_RKPWM>;
 708                 clock-names = "pwm";
 709                 status = "disabled";
 710         };
 711
 712         pwm3: pwm@ff680030 {
 713                 compatible = "rockchip,rk3288-pwm";
 714                 reg = <0x0 0xff680030 0x0 0x10>;
 715                 #pwm-cells = <2>;
 716                 pinctrl-names = "default";
 717                 pinctrl-0 = <&pwm3_pin>;
 718                 clocks = <&cru PCLK_RKPWM>;
 719                 clock-names = "pwm";
 720                 status = "disabled";
 721         };
 722
 723         bus_intmem@ff700000 {
 724                 compatible = "mmio-sram";
 725                 reg = <0x0 0xff700000 0x0 0x18000>;
 726                 #address-cells = <1>;
 727                 #size-cells = <1>;
 728                 ranges = <0 0x0 0xff700000 0x18000>;
 729                 smp-sram@0 {
 730                         compatible = "rockchip,rk3066-smp-sram";
 731                         reg = <0x00 0x10>;
 732                 };
 733         };
 734
 735         sram@ff720000 {
 736                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 737                 reg = <0x0 0xff720000 0x0 0x1000>;
 738         };
 739
 740         pmu: power-management@ff730000 {
 741                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 742                 reg = <0x0 0xff730000 0x0 0x100>;
 743
 744                 power: power-controller {
 745                         compatible = "rockchip,rk3288-power-controller";
 746                         #power-domain-cells = <1>;
 747                         #address-cells = <1>;
 748                         #size-cells = <0>;
 749
 750                         assigned-clocks = <&cru SCLK_EDP_24M>;
 751                         assigned-clock-parents = <&xin24m>;
 752
 753                         /*
 754                          * Note: Although SCLK_* are the working clocks
 755                          * of device without including on the NOC, needed for
 756                          * synchronous reset.
 757                          *
 758                          * The clocks on the which NOC:
 759                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 760                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 761                          * ACLK_RGA is on ACLK_RGA_NIU.
 762                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 763                          *
 764                          * Which clock are device clocks:
 765                          *      clocks          devices
 766                          *      *_IEP           IEP:Image Enhancement Processor
 767                          *      *_ISP           ISP:Image Signal Processing
 768                          *      *_VIP           VIP:Video Input Processor
 769                          *      *_VOP*          VOP:Visual Output Processor
 770                          *      *_RGA           RGA
 771                          *      *_EDP*          EDP
 772                          *      *_LVDS_*        LVDS
 773                          *      *_HDMI          HDMI
 774                          *      *_MIPI_*        MIPI
 775                          */
 776                         pd_vio@RK3288_PD_VIO {
 777                                 reg = <RK3288_PD_VIO>;
 778                                 clocks = <&cru ACLK_IEP>,
 779                                          <&cru ACLK_ISP>,
 780                                          <&cru ACLK_RGA>,
 781                                          <&cru ACLK_VIP>,
 782                                          <&cru ACLK_VOP0>,
 783                                          <&cru ACLK_VOP1>,
 784                                          <&cru DCLK_VOP0>,
 785                                          <&cru DCLK_VOP1>,
 786                                          <&cru HCLK_IEP>,
 787                                          <&cru HCLK_ISP>,
 788                                          <&cru HCLK_RGA>,
 789                                          <&cru HCLK_VIP>,
 790                                          <&cru HCLK_VOP0>,
 791                                          <&cru HCLK_VOP1>,
 792                                          <&cru PCLK_EDP_CTRL>,
 793                                          <&cru PCLK_HDMI_CTRL>,
 794                                          <&cru PCLK_LVDS_PHY>,
 795                                          <&cru PCLK_MIPI_CSI>,
 796                                          <&cru PCLK_MIPI_DSI0>,
 797                                          <&cru PCLK_MIPI_DSI1>,
 798                                          <&cru SCLK_EDP_24M>,
 799                                          <&cru SCLK_EDP>,
 800                                          <&cru SCLK_ISP_JPE>,
 801                                          <&cru SCLK_ISP>,
 802                                          <&cru SCLK_RGA>;
 803                                 pm_qos = <&qos_vio0_iep>,
 804                                          <&qos_vio1_vop>,
 805                                          <&qos_vio1_isp_w0>,
 806                                          <&qos_vio1_isp_w1>,
 807                                          <&qos_vio0_vop>,
 808                                          <&qos_vio0_vip>,
 809                                          <&qos_vio2_rga_r>,
 810                                          <&qos_vio2_rga_w>,
 811                                          <&qos_vio1_isp_r>;
 812                         };
 813
 814                         /*
 815                          * Note: The following 3 are HEVC(H.265) clocks,
 816                          * and on the ACLK_HEVC_NIU (NOC).
 817                          */
 818                         pd_hevc@RK3288_PD_HEVC {
 819                                 reg = <RK3288_PD_HEVC>;
 820                                 clocks = <&cru ACLK_HEVC>,
 821                                          <&cru SCLK_HEVC_CABAC>,
 822                                          <&cru SCLK_HEVC_CORE>;
 823                                 pm_qos = <&qos_hevc_r>,
 824                                          <&qos_hevc_w>;
 825                         };
 826
 827                         /*
 828                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 829                          * (video endecoder & decoder) clocks that on the
 830                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 831                          */
 832                         pd_video@RK3288_PD_VIDEO {
 833                                 reg = <RK3288_PD_VIDEO>;
 834                                 clocks = <&cru ACLK_VCODEC>,
 835                                          <&cru HCLK_VCODEC>;
 836                                 pm_qos = <&qos_video>;
 837                         };
 838
 839                         /*
 840                          * Note: ACLK_GPU is the GPU clock,
 841                          * and on the ACLK_GPU_NIU (NOC).
 842                          */
 843                         pd_gpu@RK3288_PD_GPU {
 844                                 reg = <RK3288_PD_GPU>;
 845                                 clocks = <&cru ACLK_GPU>;
 846                                 pm_qos = <&qos_gpu_r>,
 847                                          <&qos_gpu_w>;
 848                         };
 849                 };
 850
 851                 reboot-mode {
 852                         compatible = "syscon-reboot-mode";
 853                         offset = <0x94>;
 854                         mode-normal = <BOOT_NORMAL>;
 855                         mode-recovery = <BOOT_RECOVERY>;
 856                         mode-bootloader = <BOOT_FASTBOOT>;
 857                         mode-loader = <BOOT_BL_DOWNLOAD>;
 858                 };
 859         };
 860
 861         sgrf: syscon@ff740000 {
 862                 compatible = "rockchip,rk3288-sgrf", "syscon";
 863                 reg = <0x0 0xff740000 0x0 0x1000>;
 864         };
 865
 866         cru: clock-controller@ff760000 {
 867                 compatible = "rockchip,rk3288-cru";
 868                 reg = <0x0 0xff760000 0x0 0x1000>;
 869                 rockchip,grf = <&grf>;
 870                 #clock-cells = <1>;
 871                 #reset-cells = <1>;
 872                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 873                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 874                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 875                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 876                                   <&cru PCLK_PERI>;
 877                 assigned-clock-rates = <594000000>, <400000000>,
 878                                        <500000000>, <300000000>,
 879                                        <150000000>, <75000000>,
 880                                        <300000000>, <150000000>,
 881                                        <75000000>;
 882         };
 883
 884         grf: syscon@ff770000 {
 885                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 886                 reg = <0x0 0xff770000 0x0 0x1000>;
 887
 888                 edp_phy: edp-phy {
 889                         compatible = "rockchip,rk3288-dp-phy";
 890                         clocks = <&cru SCLK_EDP_24M>;
 891                         clock-names = "24m";
 892                         #phy-cells = <0>;
 893                         status = "disabled";
 894                 };
 895
 896                 io_domains: io-domains {
 897                         compatible = "rockchip,rk3288-io-voltage-domain";
 898                         status = "disabled";
 899                 };
 900
 901                 usbphy: usbphy {
 902                         compatible = "rockchip,rk3288-usb-phy";
 903                         #address-cells = <1>;
 904                         #size-cells = <0>;
 905                         status = "disabled";
 906
 907                         usbphy0: usb-phy@320 {
 908                                 #phy-cells = <0>;
 909                                 reg = <0x320>;
 910                                 clocks = <&cru SCLK_OTGPHY0>;
 911                                 clock-names = "phyclk";
 912                                 #clock-cells = <0>;
 913                                 resets = <&cru SRST_USBOTG_PHY>;
 914                                 reset-names = "phy-reset";
 915                         };
 916
 917                         usbphy1: usb-phy@334 {
 918                                 #phy-cells = <0>;
 919                                 reg = <0x334>;
 920                                 clocks = <&cru SCLK_OTGPHY1>;
 921                                 clock-names = "phyclk";
 922                                 #clock-cells = <0>;
 923                                 resets = <&cru SRST_USBHOST0_PHY>;
 924                                 reset-names = "phy-reset";
 925                         };
 926
 927                         usbphy2: usb-phy@348 {
 928                                 #phy-cells = <0>;
 929                                 reg = <0x348>;
 930                                 clocks = <&cru SCLK_OTGPHY2>;
 931                                 clock-names = "phyclk";
 932                                 #clock-cells = <0>;
 933                                 resets = <&cru SRST_USBHOST1_PHY>;
 934                                 reset-names = "phy-reset";
 935                         };
 936                 };
 937         };
 938
 939         wdt: watchdog@ff800000 {
 940                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 941                 reg = <0x0 0xff800000 0x0 0x100>;
 942                 clocks = <&cru PCLK_WDT>;
 943                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 944                 status = "disabled";
 945         };
 946
 947         spdif: sound@ff88b0000 {
 948                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 949                 reg = <0x0 0xff8b0000 0x0 0x10000>;
 950                 #sound-dai-cells = <0>;
 951                 clock-names = "hclk", "mclk";
 952                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 953                 dmas = <&dmac_bus_s 3>;
 954                 dma-names = "tx";
 955                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 956                 pinctrl-names = "default";
 957                 pinctrl-0 = <&spdif_tx>;
 958                 rockchip,grf = <&grf>;
 959                 status = "disabled";
 960         };
 961
 962         i2s: i2s@ff890000 {
 963                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 964                 reg = <0x0 0xff890000 0x0 0x10000>;
 965                 #sound-dai-cells = <0>;
 966                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 967                 #address-cells = <1>;
 968                 #size-cells = <0>;
 969                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 970                 dma-names = "tx", "rx";
 971                 clock-names = "i2s_hclk", "i2s_clk";
 972                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 973                 pinctrl-names = "default";
 974                 pinctrl-0 = <&i2s0_bus>;
 975                 rockchip,playback-channels = <8>;
 976                 rockchip,capture-channels = <2>;
 977                 status = "disabled";
 978         };
 979
 980         crypto: cypto-controller@ff8a0000 {
 981                 compatible = "rockchip,rk3288-crypto";
 982                 reg = <0x0 0xff8a0000 0x0 0x4000>;
 983                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 984                 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
 985                          <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
 986                 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
 987                 resets = <&cru SRST_CRYPTO>;
 988                 reset-names = "crypto-rst";
 989                 status = "okay";
 990         };
 991
 992         iep_mmu: iommu@ff900800 {
 993                 compatible = "rockchip,iommu";
 994                 reg = <0x0 0xff900800 0x0 0x40>;
 995                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 996                 interrupt-names = "iep_mmu";
 997                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 998                 clock-names = "aclk", "iface";
 999                 #iommu-cells = <0>;
1000                 status = "disabled";
1001         };
1002
1003         isp_mmu: iommu@ff914000 {
1004                 compatible = "rockchip,iommu";
1005                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1006                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1007                 interrupt-names = "isp_mmu";
1008                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1009                 clock-names = "aclk", "iface";
1010                 #iommu-cells = <0>;
1011                 rockchip,disable-mmu-reset;
1012                 status = "disabled";
1013         };
1014
1015         rga: rga@ff920000 {
1016                 compatible = "rockchip,rk3288-rga";
1017                 reg = <0x0 0xff920000 0x0 0x180>;
1018                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1019                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1020                 clock-names = "aclk", "hclk", "sclk";
1021                 power-domains = <&power RK3288_PD_VIO>;
1022                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1023                 reset-names = "core", "axi", "ahb";
1024         };
1025
1026         vopb: vop@ff930000 {
1027                 compatible = "rockchip,rk3288-vop";
1028                 reg = <0x0 0xff930000 0x0 0x19c>;
1029                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1030                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1031                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1032                 power-domains = <&power RK3288_PD_VIO>;
1033                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1034                 reset-names = "axi", "ahb", "dclk";
1035                 iommus = <&vopb_mmu>;
1036                 status = "disabled";
1037
1038                 vopb_out: port {
1039                         #address-cells = <1>;
1040                         #size-cells = <0>;
1041
1042                         vopb_out_hdmi: endpoint@0 {
1043                                 reg = <0>;
1044                                 remote-endpoint = <&hdmi_in_vopb>;
1045                         };
1046
1047                         vopb_out_edp: endpoint@1 {
1048                                 reg = <1>;
1049                                 remote-endpoint = <&edp_in_vopb>;
1050                         };
1051
1052                         vopb_out_mipi: endpoint@2 {
1053                                 reg = <2>;
1054                                 remote-endpoint = <&mipi_in_vopb>;
1055                         };
1056
1057                         vopb_out_lvds: endpoint@3 {
1058                                 reg = <3>;
1059                                 remote-endpoint = <&lvds_in_vopb>;
1060                         };
1061                 };
1062         };
1063
1064         vopb_mmu: iommu@ff930300 {
1065                 compatible = "rockchip,iommu";
1066                 reg = <0x0 0xff930300 0x0 0x100>;
1067                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1068                 interrupt-names = "vopb_mmu";
1069                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1070                 clock-names = "aclk", "iface";
1071                 power-domains = <&power RK3288_PD_VIO>;
1072                 #iommu-cells = <0>;
1073                 status = "disabled";
1074         };
1075
1076         vopl: vop@ff940000 {
1077                 compatible = "rockchip,rk3288-vop";
1078                 reg = <0x0 0xff940000 0x0 0x19c>;
1079                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1080                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1081                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1082                 power-domains = <&power RK3288_PD_VIO>;
1083                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1084                 reset-names = "axi", "ahb", "dclk";
1085                 iommus = <&vopl_mmu>;
1086                 status = "disabled";
1087
1088                 vopl_out: port {
1089                         #address-cells = <1>;
1090                         #size-cells = <0>;
1091
1092                         vopl_out_hdmi: endpoint@0 {
1093                                 reg = <0>;
1094                                 remote-endpoint = <&hdmi_in_vopl>;
1095                         };
1096
1097                         vopl_out_edp: endpoint@1 {
1098                                 reg = <1>;
1099                                 remote-endpoint = <&edp_in_vopl>;
1100                         };
1101
1102                         vopl_out_mipi: endpoint@2 {
1103                                 reg = <2>;
1104                                 remote-endpoint = <&mipi_in_vopl>;
1105                         };
1106
1107                         vopl_out_lvds: endpoint@3 {
1108                                 reg = <3>;
1109                                 remote-endpoint = <&lvds_in_vopl>;
1110                         };
1111                 };
1112         };
1113
1114         vopl_mmu: iommu@ff940300 {
1115                 compatible = "rockchip,iommu";
1116                 reg = <0x0 0xff940300 0x0 0x100>;
1117                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1118                 interrupt-names = "vopl_mmu";
1119                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1120                 clock-names = "aclk", "iface";
1121                 power-domains = <&power RK3288_PD_VIO>;
1122                 #iommu-cells = <0>;
1123                 status = "disabled";
1124         };
1125
1126         mipi_dsi: mipi@ff960000 {
1127                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1128                 reg = <0x0 0xff960000 0x0 0x4000>;
1129                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1130                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1131                 clock-names = "ref", "pclk";
1132                 power-domains = <&power RK3288_PD_VIO>;
1133                 rockchip,grf = <&grf>;
1134                 status = "disabled";
1135
1136                 ports {
1137                         mipi_in: port {
1138                                 #address-cells = <1>;
1139                                 #size-cells = <0>;
1140                                 mipi_in_vopb: endpoint@0 {
1141                                         reg = <0>;
1142                                         remote-endpoint = <&vopb_out_mipi>;
1143                                 };
1144                                 mipi_in_vopl: endpoint@1 {
1145                                         reg = <1>;
1146                                         remote-endpoint = <&vopl_out_mipi>;
1147                                 };
1148                         };
1149                 };
1150         };
1151
1152         lvds: lvds@ff96c000 {
1153                 compatible = "rockchip,rk3288-lvds";
1154                 reg = <0x0 0xff96c000 0x0 0x4000>;
1155                 clocks = <&cru PCLK_LVDS_PHY>;
1156                 clock-names = "pclk_lvds";
1157                 pinctrl-names = "lcdc";
1158                 pinctrl-0 = <&lcdc_ctl>;
1159                 power-domains = <&power RK3288_PD_VIO>;
1160                 rockchip,grf = <&grf>;
1161                 status = "disabled";
1162
1163                 ports {
1164                         #address-cells = <1>;
1165                         #size-cells = <0>;
1166
1167                         lvds_in: port@0 {
1168                                 reg = <0>;
1169
1170                                 #address-cells = <1>;
1171                                 #size-cells = <0>;
1172
1173                                 lvds_in_vopb: endpoint@0 {
1174                                         reg = <0>;
1175                                         remote-endpoint = <&vopb_out_lvds>;
1176                                 };
1177                                 lvds_in_vopl: endpoint@1 {
1178                                         reg = <1>;
1179                                         remote-endpoint = <&vopl_out_lvds>;
1180                                 };
1181                         };
1182                 };
1183         };
1184
1185         edp: dp@ff970000 {
1186                 compatible = "rockchip,rk3288-dp";
1187                 reg = <0x0 0xff970000 0x0 0x4000>;
1188                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1189                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1190                 clock-names = "dp", "pclk";
1191                 phys = <&edp_phy>;
1192                 phy-names = "dp";
1193                 resets = <&cru SRST_EDP>;
1194                 reset-names = "dp";
1195                 rockchip,grf = <&grf>;
1196                 status = "disabled";
1197
1198                 ports {
1199                         #address-cells = <1>;
1200                         #size-cells = <0>;
1201                         edp_in: port@0 {
1202                                 reg = <0>;
1203                                 #address-cells = <1>;
1204                                 #size-cells = <0>;
1205                                 edp_in_vopb: endpoint@0 {
1206                                         reg = <0>;
1207                                         remote-endpoint = <&vopb_out_edp>;
1208                                 };
1209                                 edp_in_vopl: endpoint@1 {
1210                                         reg = <1>;
1211                                         remote-endpoint = <&vopl_out_edp>;
1212                                 };
1213                         };
1214                 };
1215         };
1216
1217         hdmi: hdmi@ff980000 {
1218                 compatible = "rockchip,rk3288-dw-hdmi";
1219                 reg = <0x0 0xff980000 0x0 0x20000>;
1220                 reg-io-width = <4>;
1221                 #sound-dai-cells = <0>;
1222                 rockchip,grf = <&grf>;
1223                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1224                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1225                 clock-names = "iahb", "isfr", "cec";
1226                 power-domains = <&power RK3288_PD_VIO>;
1227                 status = "disabled";
1228
1229                 ports {
1230                         hdmi_in: port {
1231                                 #address-cells = <1>;
1232                                 #size-cells = <0>;
1233                                 hdmi_in_vopb: endpoint@0 {
1234                                         reg = <0>;
1235                                         remote-endpoint = <&vopb_out_hdmi>;
1236                                 };
1237                                 hdmi_in_vopl: endpoint@1 {
1238                                         reg = <1>;
1239                                         remote-endpoint = <&vopl_out_hdmi>;
1240                                 };
1241                         };
1242                 };
1243         };
1244
1245         vpu: video-codec@ff9a0000 {
1246                 compatible = "rockchip,rk3288-vpu";
1247                 reg = <0x0 0xff9a0000 0x0 0x800>;
1248                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1249                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1250                 interrupt-names = "vepu", "vdpu";
1251                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1252                 clock-names = "aclk", "hclk";
1253                 iommus = <&vpu_mmu>;
1254                 power-domains = <&power RK3288_PD_VIDEO>;
1255         };
1256
1257         vpu_mmu: iommu@ff9a0800 {
1258                 compatible = "rockchip,iommu";
1259                 reg = <0x0 0xff9a0800 0x0 0x100>;
1260                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1261                 interrupt-names = "vpu_mmu";
1262                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1263                 clock-names = "aclk", "iface";
1264                 #iommu-cells = <0>;
1265                 power-domains = <&power RK3288_PD_VIDEO>;
1266         };
1267
1268         hevc_mmu: iommu@ff9c0440 {
1269                 compatible = "rockchip,iommu";
1270                 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
1271                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1272                 interrupt-names = "hevc_mmu";
1273                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
1274                 clock-names = "aclk", "iface";
1275                 #iommu-cells = <0>;
1276                 status = "disabled";
1277         };
1278
1279         gpu: gpu@ffa30000 {
1280                 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1281                 reg = <0x0 0xffa30000 0x0 0x10000>;
1282                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1283                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1284                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1285                 interrupt-names = "job", "mmu", "gpu";
1286                 clocks = <&cru ACLK_GPU>;
1287                 operating-points-v2 = <&gpu_opp_table>;
1288                 power-domains = <&power RK3288_PD_GPU>;
1289                 status = "disabled";
1290         };
1291
1292         gpu_opp_table: gpu-opp-table {
1293                 compatible = "operating-points-v2";
1294
1295                 opp-100000000 {
1296                         opp-hz = /bits/ 64 <100000000>;
1297                         opp-microvolt = <950000>;
1298                 };
1299                 opp-200000000 {
1300                         opp-hz = /bits/ 64 <200000000>;
1301                         opp-microvolt = <950000>;
1302                 };
1303                 opp-300000000 {
1304                         opp-hz = /bits/ 64 <300000000>;
1305                         opp-microvolt = <1000000>;
1306                 };
1307                 opp-400000000 {
1308                         opp-hz = /bits/ 64 <400000000>;
1309                         opp-microvolt = <1100000>;
1310                 };
1311                 opp-500000000 {
1312                         opp-hz = /bits/ 64 <500000000>;
1313                         opp-microvolt = <1200000>;
1314                 };
1315                 opp-600000000 {
1316                         opp-hz = /bits/ 64 <600000000>;
1317                         opp-microvolt = <1250000>;
1318                 };
1319         };
1320
1321         qos_gpu_r: qos@ffaa0000 {
1322                 compatible = "syscon";
1323                 reg = <0x0 0xffaa0000 0x0 0x20>;
1324         };
1325
1326         qos_gpu_w: qos@ffaa0080 {
1327                 compatible = "syscon";
1328                 reg = <0x0 0xffaa0080 0x0 0x20>;
1329         };
1330
1331         qos_vio1_vop: qos@ffad0000 {
1332                 compatible = "syscon";
1333                 reg = <0x0 0xffad0000 0x0 0x20>;
1334         };
1335
1336         qos_vio1_isp_w0: qos@ffad0100 {
1337                 compatible = "syscon";
1338                 reg = <0x0 0xffad0100 0x0 0x20>;
1339         };
1340
1341         qos_vio1_isp_w1: qos@ffad0180 {
1342                 compatible = "syscon";
1343                 reg = <0x0 0xffad0180 0x0 0x20>;
1344         };
1345
1346         qos_vio0_vop: qos@ffad0400 {
1347                 compatible = "syscon";
1348                 reg = <0x0 0xffad0400 0x0 0x20>;
1349         };
1350
1351         qos_vio0_vip: qos@ffad0480 {
1352                 compatible = "syscon";
1353                 reg = <0x0 0xffad0480 0x0 0x20>;
1354         };
1355
1356         qos_vio0_iep: qos@ffad0500 {
1357                 compatible = "syscon";
1358                 reg = <0x0 0xffad0500 0x0 0x20>;
1359         };
1360
1361         qos_vio2_rga_r: qos@ffad0800 {
1362                 compatible = "syscon";
1363                 reg = <0x0 0xffad0800 0x0 0x20>;
1364         };
1365
1366         qos_vio2_rga_w: qos@ffad0880 {
1367                 compatible = "syscon";
1368                 reg = <0x0 0xffad0880 0x0 0x20>;
1369         };
1370
1371         qos_vio1_isp_r: qos@ffad0900 {
1372                 compatible = "syscon";
1373                 reg = <0x0 0xffad0900 0x0 0x20>;
1374         };
1375
1376         qos_video: qos@ffae0000 {
1377                 compatible = "syscon";
1378                 reg = <0x0 0xffae0000 0x0 0x20>;
1379         };
1380
1381         qos_hevc_r: qos@ffaf0000 {
1382                 compatible = "syscon";
1383                 reg = <0x0 0xffaf0000 0x0 0x20>;
1384         };
1385
1386         qos_hevc_w: qos@ffaf0080 {
1387                 compatible = "syscon";
1388                 reg = <0x0 0xffaf0080 0x0 0x20>;
1389         };
1390
1391         efuse: efuse@ffb40000 {
1392                 compatible = "rockchip,rk3288-efuse";
1393                 reg = <0x0 0xffb40000 0x0 0x20>;
1394                 #address-cells = <1>;
1395                 #size-cells = <1>;
1396                 clocks = <&cru PCLK_EFUSE256>;
1397                 clock-names = "pclk_efuse";
1398
1399                 cpu_leakage: cpu_leakage@17 {
1400                         reg = <0x17 0x1>;
1401                 };
1402         };
1403
1404         gic: interrupt-controller@ffc01000 {
1405                 compatible = "arm,gic-400";
1406                 interrupt-controller;
1407                 #interrupt-cells = <3>;
1408                 #address-cells = <0>;
1409
1410                 reg = <0x0 0xffc01000 0x0 0x1000>,
1411                       <0x0 0xffc02000 0x0 0x2000>,
1412                       <0x0 0xffc04000 0x0 0x2000>,
1413                       <0x0 0xffc06000 0x0 0x2000>;
1414                 interrupts = <GIC_PPI 9 0xf04>;
1415         };
1416
1417         pinctrl: pinctrl {
1418                 compatible = "rockchip,rk3288-pinctrl";
1419                 rockchip,grf = <&grf>;
1420                 rockchip,pmu = <&pmu>;
1421                 #address-cells = <2>;
1422                 #size-cells = <2>;
1423                 ranges;
1424
1425                 gpio0: gpio0@ff750000 {
1426                         compatible = "rockchip,gpio-bank";
1427                         reg = <0x0 0xff750000 0x0 0x100>;
1428                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1429                         clocks = <&cru PCLK_GPIO0>;
1430
1431                         gpio-controller;
1432                         #gpio-cells = <2>;
1433
1434                         interrupt-controller;
1435                         #interrupt-cells = <2>;
1436                 };
1437
1438                 gpio1: gpio1@ff780000 {
1439                         compatible = "rockchip,gpio-bank";
1440                         reg = <0x0 0xff780000 0x0 0x100>;
1441                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1442                         clocks = <&cru PCLK_GPIO1>;
1443
1444                         gpio-controller;
1445                         #gpio-cells = <2>;
1446
1447                         interrupt-controller;
1448                         #interrupt-cells = <2>;
1449                 };
1450
1451                 gpio2: gpio2@ff790000 {
1452                         compatible = "rockchip,gpio-bank";
1453                         reg = <0x0 0xff790000 0x0 0x100>;
1454                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1455                         clocks = <&cru PCLK_GPIO2>;
1456
1457                         gpio-controller;
1458                         #gpio-cells = <2>;
1459
1460                         interrupt-controller;
1461                         #interrupt-cells = <2>;
1462                 };
1463
1464                 gpio3: gpio3@ff7a0000 {
1465                         compatible = "rockchip,gpio-bank";
1466                         reg = <0x0 0xff7a0000 0x0 0x100>;
1467                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1468                         clocks = <&cru PCLK_GPIO3>;
1469
1470                         gpio-controller;
1471                         #gpio-cells = <2>;
1472
1473                         interrupt-controller;
1474                         #interrupt-cells = <2>;
1475                 };
1476
1477                 gpio4: gpio4@ff7b0000 {
1478                         compatible = "rockchip,gpio-bank";
1479                         reg = <0x0 0xff7b0000 0x0 0x100>;
1480                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1481                         clocks = <&cru PCLK_GPIO4>;
1482
1483                         gpio-controller;
1484                         #gpio-cells = <2>;
1485
1486                         interrupt-controller;
1487                         #interrupt-cells = <2>;
1488                 };
1489
1490                 gpio5: gpio5@ff7c0000 {
1491                         compatible = "rockchip,gpio-bank";
1492                         reg = <0x0 0xff7c0000 0x0 0x100>;
1493                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1494                         clocks = <&cru PCLK_GPIO5>;
1495
1496                         gpio-controller;
1497                         #gpio-cells = <2>;
1498
1499                         interrupt-controller;
1500                         #interrupt-cells = <2>;
1501                 };
1502
1503                 gpio6: gpio6@ff7d0000 {
1504                         compatible = "rockchip,gpio-bank";
1505                         reg = <0x0 0xff7d0000 0x0 0x100>;
1506                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1507                         clocks = <&cru PCLK_GPIO6>;
1508
1509                         gpio-controller;
1510                         #gpio-cells = <2>;
1511
1512                         interrupt-controller;
1513                         #interrupt-cells = <2>;
1514                 };
1515
1516                 gpio7: gpio7@ff7e0000 {
1517                         compatible = "rockchip,gpio-bank";
1518                         reg = <0x0 0xff7e0000 0x0 0x100>;
1519                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1520                         clocks = <&cru PCLK_GPIO7>;
1521
1522                         gpio-controller;
1523                         #gpio-cells = <2>;
1524
1525                         interrupt-controller;
1526                         #interrupt-cells = <2>;
1527                 };
1528
1529                 gpio8: gpio8@ff7f0000 {
1530                         compatible = "rockchip,gpio-bank";
1531                         reg = <0x0 0xff7f0000 0x0 0x100>;
1532                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1533                         clocks = <&cru PCLK_GPIO8>;
1534
1535                         gpio-controller;
1536                         #gpio-cells = <2>;
1537
1538                         interrupt-controller;
1539                         #interrupt-cells = <2>;
1540                 };
1541
1542                 hdmi {
1543                         hdmi_cec_c0: hdmi-cec-c0 {
1544                                 rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>;
1545                         };
1546
1547                         hdmi_cec_c7: hdmi-cec-c7 {
1548                                 rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>;
1549                         };
1550
1551                         hdmi_ddc: hdmi-ddc {
1552                                 rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>,
1553                                                 <7 RK_PC4 2 &pcfg_pull_none>;
1554                         };
1555                 };
1556
1557                 pcfg_pull_up: pcfg-pull-up {
1558                         bias-pull-up;
1559                 };
1560
1561                 pcfg_pull_down: pcfg-pull-down {
1562                         bias-pull-down;
1563                 };
1564
1565                 pcfg_pull_none: pcfg-pull-none {
1566                         bias-disable;
1567                 };
1568
1569                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1570                         bias-disable;
1571                         drive-strength = <12>;
1572                 };
1573
1574                 sleep {
1575                         global_pwroff: global-pwroff {
1576                                 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
1577                         };
1578
1579                         ddrio_pwroff: ddrio-pwroff {
1580                                 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
1581                         };
1582
1583                         ddr0_retention: ddr0-retention {
1584                                 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>;
1585                         };
1586
1587                         ddr1_retention: ddr1-retention {
1588                                 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
1589                         };
1590                 };
1591
1592                 edp {
1593                         edp_hpd: edp-hpd {
1594                                 rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>;
1595                         };
1596                 };
1597
1598                 i2c0 {
1599                         i2c0_xfer: i2c0-xfer {
1600                                 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>,
1601                                                 <0 RK_PC0 1 &pcfg_pull_none>;
1602                         };
1603                 };
1604
1605                 i2c1 {
1606                         i2c1_xfer: i2c1-xfer {
1607                                 rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>,
1608                                                 <8 RK_PA5 1 &pcfg_pull_none>;
1609                         };
1610                 };
1611
1612                 i2c2 {
1613                         i2c2_xfer: i2c2-xfer {
1614                                 rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>,
1615                                                 <6 RK_PB2 1 &pcfg_pull_none>;
1616                         };
1617                 };
1618
1619                 i2c3 {
1620                         i2c3_xfer: i2c3-xfer {
1621                                 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>,
1622                                                 <2 RK_PC1 1 &pcfg_pull_none>;
1623                         };
1624                 };
1625
1626                 i2c4 {
1627                         i2c4_xfer: i2c4-xfer {
1628                                 rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>,
1629                                                 <7 RK_PC2 1 &pcfg_pull_none>;
1630                         };
1631                 };
1632
1633                 i2c5 {
1634                         i2c5_xfer: i2c5-xfer {
1635                                 rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>,
1636                                                 <7 RK_PC4 1 &pcfg_pull_none>;
1637                         };
1638                 };
1639
1640                 i2s0 {
1641                         i2s0_bus: i2s0-bus {
1642                                 rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>,
1643                                                 <6 RK_PA1 1 &pcfg_pull_none>,
1644                                                 <6 RK_PA2 1 &pcfg_pull_none>,
1645                                                 <6 RK_PA3 1 &pcfg_pull_none>,
1646                                                 <6 RK_PA4 1 &pcfg_pull_none>,
1647                                                 <6 RK_PB0 1 &pcfg_pull_none>;
1648                         };
1649                 };
1650
1651                 lcdc {
1652                         lcdc_ctl: lcdc-ctl {
1653                                 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
1654                                                 <1 RK_PD1 1 &pcfg_pull_none>,
1655                                                 <1 RK_PD2 1 &pcfg_pull_none>,
1656                                                 <1 RK_PD3 1 &pcfg_pull_none>;
1657                         };
1658                 };
1659
1660                 sdmmc {
1661                         sdmmc_clk: sdmmc-clk {
1662                                 rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>;
1663                         };
1664
1665                         sdmmc_cmd: sdmmc-cmd {
1666                                 rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>;
1667                         };
1668
1669                         sdmmc_cd: sdmmc-cd {
1670                                 rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>;
1671                         };
1672
1673                         sdmmc_bus1: sdmmc-bus1 {
1674                                 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>;
1675                         };
1676
1677                         sdmmc_bus4: sdmmc-bus4 {
1678                                 rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>,
1679                                                 <6 RK_PC1 1 &pcfg_pull_up>,
1680                                                 <6 RK_PC2 1 &pcfg_pull_up>,
1681                                                 <6 RK_PC3 1 &pcfg_pull_up>;
1682                         };
1683                 };
1684
1685                 sdio0 {
1686                         sdio0_bus1: sdio0-bus1 {
1687                                 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>;
1688                         };
1689
1690                         sdio0_bus4: sdio0-bus4 {
1691                                 rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>,
1692                                                 <4 RK_PC5 1 &pcfg_pull_up>,
1693                                                 <4 RK_PC6 1 &pcfg_pull_up>,
1694                                                 <4 RK_PC7 1 &pcfg_pull_up>;
1695                         };
1696
1697                         sdio0_cmd: sdio0-cmd {
1698                                 rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>;
1699                         };
1700
1701                         sdio0_clk: sdio0-clk {
1702                                 rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>;
1703                         };
1704
1705                         sdio0_cd: sdio0-cd {
1706                                 rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>;
1707                         };
1708
1709                         sdio0_wp: sdio0-wp {
1710                                 rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>;
1711                         };
1712
1713                         sdio0_pwr: sdio0-pwr {
1714                                 rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>;
1715                         };
1716
1717                         sdio0_bkpwr: sdio0-bkpwr {
1718                                 rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>;
1719                         };
1720
1721                         sdio0_int: sdio0-int {
1722                                 rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>;
1723                         };
1724                 };
1725
1726                 sdio1 {
1727                         sdio1_bus1: sdio1-bus1 {
1728                                 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>;
1729                         };
1730
1731                         sdio1_bus4: sdio1-bus4 {
1732                                 rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>,
1733                                                 <3 RK_PD1 4 &pcfg_pull_up>,
1734                                                 <3 RK_PD2 4 &pcfg_pull_up>,
1735                                                 <3 RK_PD3 4 &pcfg_pull_up>;
1736                         };
1737
1738                         sdio1_cd: sdio1-cd {
1739                                 rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>;
1740                         };
1741
1742                         sdio1_wp: sdio1-wp {
1743                                 rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>;
1744                         };
1745
1746                         sdio1_bkpwr: sdio1-bkpwr {
1747                                 rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>;
1748                         };
1749
1750                         sdio1_int: sdio1-int {
1751                                 rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>;
1752                         };
1753
1754                         sdio1_cmd: sdio1-cmd {
1755                                 rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>;
1756                         };
1757
1758                         sdio1_clk: sdio1-clk {
1759                                 rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>;
1760                         };
1761
1762                         sdio1_pwr: sdio1-pwr {
1763                                 rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>;
1764                         };
1765                 };
1766
1767                 emmc {
1768                         emmc_clk: emmc-clk {
1769                                 rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>;
1770                         };
1771
1772                         emmc_cmd: emmc-cmd {
1773                                 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>;
1774                         };
1775
1776                         emmc_pwr: emmc-pwr {
1777                                 rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>;
1778                         };
1779
1780                         emmc_bus1: emmc-bus1 {
1781                                 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>;
1782                         };
1783
1784                         emmc_bus4: emmc-bus4 {
1785                                 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
1786                                                 <3 RK_PA1 2 &pcfg_pull_up>,
1787                                                 <3 RK_PA2 2 &pcfg_pull_up>,
1788                                                 <3 RK_PA3 2 &pcfg_pull_up>;
1789                         };
1790
1791                         emmc_bus8: emmc-bus8 {
1792                                 rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>,
1793                                                 <3 RK_PA1 2 &pcfg_pull_up>,
1794                                                 <3 RK_PA2 2 &pcfg_pull_up>,
1795                                                 <3 RK_PA3 2 &pcfg_pull_up>,
1796                                                 <3 RK_PA4 2 &pcfg_pull_up>,
1797                                                 <3 RK_PA5 2 &pcfg_pull_up>,
1798                                                 <3 RK_PA6 2 &pcfg_pull_up>,
1799                                                 <3 RK_PA7 2 &pcfg_pull_up>;
1800                         };
1801                 };
1802
1803                 spi0 {
1804                         spi0_clk: spi0-clk {
1805                                 rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>;
1806                         };
1807                         spi0_cs0: spi0-cs0 {
1808                                 rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>;
1809                         };
1810                         spi0_tx: spi0-tx {
1811                                 rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>;
1812                         };
1813                         spi0_rx: spi0-rx {
1814                                 rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>;
1815                         };
1816                         spi0_cs1: spi0-cs1 {
1817                                 rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>;
1818                         };
1819                 };
1820                 spi1 {
1821                         spi1_clk: spi1-clk {
1822                                 rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>;
1823                         };
1824                         spi1_cs0: spi1-cs0 {
1825                                 rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>;
1826                         };
1827                         spi1_rx: spi1-rx {
1828                                 rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>;
1829                         };
1830                         spi1_tx: spi1-tx {
1831                                 rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>;
1832                         };
1833                 };
1834
1835                 spi2 {
1836                         spi2_cs1: spi2-cs1 {
1837                                 rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>;
1838                         };
1839                         spi2_clk: spi2-clk {
1840                                 rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>;
1841                         };
1842                         spi2_cs0: spi2-cs0 {
1843                                 rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>;
1844                         };
1845                         spi2_rx: spi2-rx {
1846                                 rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>;
1847                         };
1848                         spi2_tx: spi2-tx {
1849                                 rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>;
1850                         };
1851                 };
1852
1853                 uart0 {
1854                         uart0_xfer: uart0-xfer {
1855                                 rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>,
1856                                                 <4 RK_PC1 1 &pcfg_pull_none>;
1857                         };
1858
1859                         uart0_cts: uart0-cts {
1860                                 rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>;
1861                         };
1862
1863                         uart0_rts: uart0-rts {
1864                                 rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>;
1865                         };
1866                 };
1867
1868                 uart1 {
1869                         uart1_xfer: uart1-xfer {
1870                                 rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>,
1871                                                 <5 RK_PB1 1 &pcfg_pull_none>;
1872                         };
1873
1874                         uart1_cts: uart1-cts {
1875                                 rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>;
1876                         };
1877
1878                         uart1_rts: uart1-rts {
1879                                 rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>;
1880                         };
1881                 };
1882
1883                 uart2 {
1884                         uart2_xfer: uart2-xfer {
1885                                 rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>,
1886                                                 <7 RK_PC7 1 &pcfg_pull_none>;
1887                         };
1888                         /* no rts / cts for uart2 */
1889                 };
1890
1891                 uart3 {
1892                         uart3_xfer: uart3-xfer {
1893                                 rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>,
1894                                                 <7 RK_PB0 1 &pcfg_pull_none>;
1895                         };
1896
1897                         uart3_cts: uart3-cts {
1898                                 rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>;
1899                         };
1900
1901                         uart3_rts: uart3-rts {
1902                                 rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>;
1903                         };
1904                 };
1905
1906                 uart4 {
1907                         uart4_xfer: uart4-xfer {
1908                                 rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>,
1909                                                 <5 RK_PB6 3 &pcfg_pull_none>;
1910                         };
1911
1912                         uart4_cts: uart4-cts {
1913                                 rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>;
1914                         };
1915
1916                         uart4_rts: uart4-rts {
1917                                 rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>;
1918                         };
1919                 };
1920
1921                 tsadc {
1922                         otp_gpio: otp-gpio {
1923                                 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1924                         };
1925
1926                         otp_out: otp-out {
1927                                 rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>;
1928                         };
1929                 };
1930
1931                 pwm0 {
1932                         pwm0_pin: pwm0-pin {
1933                                 rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>;
1934                         };
1935                 };
1936
1937                 pwm1 {
1938                         pwm1_pin: pwm1-pin {
1939                                 rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>;
1940                         };
1941                 };
1942
1943                 pwm2 {
1944                         pwm2_pin: pwm2-pin {
1945                                 rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>;
1946                         };
1947                 };
1948
1949                 pwm3 {
1950                         pwm3_pin: pwm3-pin {
1951                                 rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>;
1952                         };
1953                 };
1954
1955                 gmac {
1956                         rgmii_pins: rgmii-pins {
1957                                 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
1958                                                 <3 RK_PD7 3 &pcfg_pull_none>,
1959                                                 <3 RK_PD2 3 &pcfg_pull_none>,
1960                                                 <3 RK_PD3 3 &pcfg_pull_none>,
1961                                                 <3 RK_PD4 3 &pcfg_pull_none_12ma>,
1962                                                 <3 RK_PD5 3 &pcfg_pull_none_12ma>,
1963                                                 <3 RK_PD0 3 &pcfg_pull_none_12ma>,
1964                                                 <3 RK_PD1 3 &pcfg_pull_none_12ma>,
1965                                                 <4 RK_PA0 3 &pcfg_pull_none>,
1966                                                 <4 RK_PA5 3 &pcfg_pull_none>,
1967                                                 <4 RK_PA6 3 &pcfg_pull_none>,
1968                                                 <4 RK_PB1 3 &pcfg_pull_none_12ma>,
1969                                                 <4 RK_PA4 3 &pcfg_pull_none_12ma>,
1970                                                 <4 RK_PA1 3 &pcfg_pull_none>,
1971                                                 <4 RK_PA3 3 &pcfg_pull_none>;
1972                         };
1973
1974                         rmii_pins: rmii-pins {
1975                                 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>,
1976                                                 <3 RK_PD7 3 &pcfg_pull_none>,
1977                                                 <3 RK_PD4 3 &pcfg_pull_none>,
1978                                                 <3 RK_PD5 3 &pcfg_pull_none>,
1979                                                 <4 RK_PA0 3 &pcfg_pull_none>,
1980                                                 <4 RK_PA5 3 &pcfg_pull_none>,
1981                                                 <4 RK_PA4 3 &pcfg_pull_none>,
1982                                                 <4 RK_PA1 3 &pcfg_pull_none>,
1983                                                 <4 RK_PA2 3 &pcfg_pull_none>,
1984                                                 <4 RK_PA3 3 &pcfg_pull_none>;
1985                         };
1986                 };
1987
1988                 spdif {
1989                         spdif_tx: spdif-tx {
1990                                 rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>;
1991                         };
1992                 };
1993         };
1994 };