arch/arm/boot/dts/r8a7791.dtsi

   1 /*
   2  * Device Tree Source for the r8a7791 SoC
   3  *
   4  * Copyright (C) 2013 Renesas Electronics Corporation
   5  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   6  * Copyright (C) 2014 Cogent Embedded Inc.
   7  *
   8  * This file is licensed under the terms of the GNU General Public License
   9  * version 2.  This program is licensed "as is" without any warranty of any
  10  * kind, whether express or implied.
  11  */
  12
  13 #include <dt-bindings/clock/r8a7791-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16
  17 / {
  18         compatible = "renesas,r8a7791";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 spi0 = &qspi;
  31                 spi1 = &msiof0;
  32                 spi2 = &msiof1;
  33                 spi3 = &msiof2;
  34         };
  35
  36         cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39
  40                 cpu0: cpu@0 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a15";
  43                         reg = <0>;
  44                         clock-frequency = <1500000000>;
  45                 };
  46
  47                 cpu1: cpu@1 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a15";
  50                         reg = <1>;
  51                         clock-frequency = <1500000000>;
  52                 };
  53         };
  54
  55         gic: interrupt-controller@f1001000 {
  56                 compatible = "arm,cortex-a15-gic";
  57                 #interrupt-cells = <3>;
  58                 #address-cells = <0>;
  59                 interrupt-controller;
  60                 reg = <0 0xf1001000 0 0x1000>,
  61                         <0 0xf1002000 0 0x1000>,
  62                         <0 0xf1004000 0 0x2000>,
  63                         <0 0xf1006000 0 0x2000>;
  64                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  65         };
  66
  67         gpio0: gpio@e6050000 {
  68                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  69                 reg = <0 0xe6050000 0 0x50>;
  70                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
  71                 #gpio-cells = <2>;
  72                 gpio-controller;
  73                 gpio-ranges = <&pfc 0 0 32>;
  74                 #interrupt-cells = <2>;
  75                 interrupt-controller;
  76         };
  77
  78         gpio1: gpio@e6051000 {
  79                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  80                 reg = <0 0xe6051000 0 0x50>;
  81                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
  82                 #gpio-cells = <2>;
  83                 gpio-controller;
  84                 gpio-ranges = <&pfc 0 32 32>;
  85                 #interrupt-cells = <2>;
  86                 interrupt-controller;
  87         };
  88
  89         gpio2: gpio@e6052000 {
  90                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  91                 reg = <0 0xe6052000 0 0x50>;
  92                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
  93                 #gpio-cells = <2>;
  94                 gpio-controller;
  95                 gpio-ranges = <&pfc 0 64 32>;
  96                 #interrupt-cells = <2>;
  97                 interrupt-controller;
  98         };
  99
 100         gpio3: gpio@e6053000 {
 101                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 102                 reg = <0 0xe6053000 0 0x50>;
 103                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 104                 #gpio-cells = <2>;
 105                 gpio-controller;
 106                 gpio-ranges = <&pfc 0 96 32>;
 107                 #interrupt-cells = <2>;
 108                 interrupt-controller;
 109         };
 110
 111         gpio4: gpio@e6054000 {
 112                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 113                 reg = <0 0xe6054000 0 0x50>;
 114                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 115                 #gpio-cells = <2>;
 116                 gpio-controller;
 117                 gpio-ranges = <&pfc 0 128 32>;
 118                 #interrupt-cells = <2>;
 119                 interrupt-controller;
 120         };
 121
 122         gpio5: gpio@e6055000 {
 123                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 124                 reg = <0 0xe6055000 0 0x50>;
 125                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 126                 #gpio-cells = <2>;
 127                 gpio-controller;
 128                 gpio-ranges = <&pfc 0 160 32>;
 129                 #interrupt-cells = <2>;
 130                 interrupt-controller;
 131         };
 132
 133         gpio6: gpio@e6055400 {
 134                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 135                 reg = <0 0xe6055400 0 0x50>;
 136                 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 137                 #gpio-cells = <2>;
 138                 gpio-controller;
 139                 gpio-ranges = <&pfc 0 192 32>;
 140                 #interrupt-cells = <2>;
 141                 interrupt-controller;
 142         };
 143
 144         gpio7: gpio@e6055800 {
 145                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 146                 reg = <0 0xe6055800 0 0x50>;
 147                 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 148                 #gpio-cells = <2>;
 149                 gpio-controller;
 150                 gpio-ranges = <&pfc 0 224 26>;
 151                 #interrupt-cells = <2>;
 152                 interrupt-controller;
 153         };
 154
 155         thermal@e61f0000 {
 156                 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
 157                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 158                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 159                 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
 160         };
 161
 162         timer {
 163                 compatible = "arm,armv7-timer";
 164                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 165                              <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 166                              <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 167                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 168         };
 169
 170         irqc0: interrupt-controller@e61c0000 {
 171                 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
 172                 #interrupt-cells = <2>;
 173                 interrupt-controller;
 174                 reg = <0 0xe61c0000 0 0x200>;
 175                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 176                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 177                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 178                              <0 3 IRQ_TYPE_LEVEL_HIGH>,
 179                              <0 12 IRQ_TYPE_LEVEL_HIGH>,
 180                              <0 13 IRQ_TYPE_LEVEL_HIGH>,
 181                              <0 14 IRQ_TYPE_LEVEL_HIGH>,
 182                              <0 15 IRQ_TYPE_LEVEL_HIGH>,
 183                              <0 16 IRQ_TYPE_LEVEL_HIGH>,
 184                              <0 17 IRQ_TYPE_LEVEL_HIGH>;
 185         };
 186
 187         i2c0: i2c@e6508000 {
 188                 #address-cells = <1>;
 189                 #size-cells = <0>;
 190                 compatible = "renesas,i2c-r8a7791";
 191                 reg = <0 0xe6508000 0 0x40>;
 192                 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 193                 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
 194                 status = "disabled";
 195         };
 196
 197         i2c1: i2c@e6518000 {
 198                 #address-cells = <1>;
 199                 #size-cells = <0>;
 200                 compatible = "renesas,i2c-r8a7791";
 201                 reg = <0 0xe6518000 0 0x40>;
 202                 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 203                 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
 204                 status = "disabled";
 205         };
 206
 207         i2c2: i2c@e6530000 {
 208                 #address-cells = <1>;
 209                 #size-cells = <0>;
 210                 compatible = "renesas,i2c-r8a7791";
 211                 reg = <0 0xe6530000 0 0x40>;
 212                 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 213                 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
 214                 status = "disabled";
 215         };
 216
 217         i2c3: i2c@e6540000 {
 218                 #address-cells = <1>;
 219                 #size-cells = <0>;
 220                 compatible = "renesas,i2c-r8a7791";
 221                 reg = <0 0xe6540000 0 0x40>;
 222                 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 223                 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
 224                 status = "disabled";
 225         };
 226
 227         i2c4: i2c@e6520000 {
 228                 #address-cells = <1>;
 229                 #size-cells = <0>;
 230                 compatible = "renesas,i2c-r8a7791";
 231                 reg = <0 0xe6520000 0 0x40>;
 232                 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
 233                 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
 234                 status = "disabled";
 235         };
 236
 237         i2c5: i2c@e6528000 {
 238                 #address-cells = <1>;
 239                 #size-cells = <0>;
 240                 compatible = "renesas,i2c-r8a7791";
 241                 reg = <0 0xe6528000 0 0x40>;
 242                 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
 243                 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
 244                 status = "disabled";
 245         };
 246
 247         pfc: pfc@e6060000 {
 248                 compatible = "renesas,pfc-r8a7791";
 249                 reg = <0 0xe6060000 0 0x250>;
 250                 #gpio-range-cells = <3>;
 251         };
 252
 253         sdhi0: sd@ee100000 {
 254                 compatible = "renesas,sdhi-r8a7791";
 255                 reg = <0 0xee100000 0 0x200>;
 256                 interrupt-parent = <&gic>;
 257                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 258                 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
 259                 status = "disabled";
 260         };
 261
 262         sdhi1: sd@ee140000 {
 263                 compatible = "renesas,sdhi-r8a7791";
 264                 reg = <0 0xee140000 0 0x100>;
 265                 interrupt-parent = <&gic>;
 266                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 267                 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
 268                 status = "disabled";
 269         };
 270
 271         sdhi2: sd@ee160000 {
 272                 compatible = "renesas,sdhi-r8a7791";
 273                 reg = <0 0xee160000 0 0x100>;
 274                 interrupt-parent = <&gic>;
 275                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 276                 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
 277                 status = "disabled";
 278         };
 279
 280         scifa0: serial@e6c40000 {
 281                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 282                 reg = <0 0xe6c40000 0 64>;
 283                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 284                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
 285                 clock-names = "sci_ick";
 286                 status = "disabled";
 287         };
 288
 289         scifa1: serial@e6c50000 {
 290                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 291                 reg = <0 0xe6c50000 0 64>;
 292                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 293                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
 294                 clock-names = "sci_ick";
 295                 status = "disabled";
 296         };
 297
 298         scifa2: serial@e6c60000 {
 299                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 300                 reg = <0 0xe6c60000 0 64>;
 301                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 302                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
 303                 clock-names = "sci_ick";
 304                 status = "disabled";
 305         };
 306
 307         scifa3: serial@e6c70000 {
 308                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 309                 reg = <0 0xe6c70000 0 64>;
 310                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 311                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
 312                 clock-names = "sci_ick";
 313                 status = "disabled";
 314         };
 315
 316         scifa4: serial@e6c78000 {
 317                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 318                 reg = <0 0xe6c78000 0 64>;
 319                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 320                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
 321                 clock-names = "sci_ick";
 322                 status = "disabled";
 323         };
 324
 325         scifa5: serial@e6c80000 {
 326                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 327                 reg = <0 0xe6c80000 0 64>;
 328                 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 329                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
 330                 clock-names = "sci_ick";
 331                 status = "disabled";
 332         };
 333
 334         scifb0: serial@e6c20000 {
 335                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 336                 reg = <0 0xe6c20000 0 64>;
 337                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 338                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
 339                 clock-names = "sci_ick";
 340                 status = "disabled";
 341         };
 342
 343         scifb1: serial@e6c30000 {
 344                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 345                 reg = <0 0xe6c30000 0 64>;
 346                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 347                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
 348                 clock-names = "sci_ick";
 349                 status = "disabled";
 350         };
 351
 352         scifb2: serial@e6ce0000 {
 353                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 354                 reg = <0 0xe6ce0000 0 64>;
 355                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 356                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
 357                 clock-names = "sci_ick";
 358                 status = "disabled";
 359         };
 360
 361         scif0: serial@e6e60000 {
 362                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 363                 reg = <0 0xe6e60000 0 64>;
 364                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 365                 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
 366                 clock-names = "sci_ick";
 367                 status = "disabled";
 368         };
 369
 370         scif1: serial@e6e68000 {
 371                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 372                 reg = <0 0xe6e68000 0 64>;
 373                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 374                 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
 375                 clock-names = "sci_ick";
 376                 status = "disabled";
 377         };
 378
 379         scif2: serial@e6e58000 {
 380                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 381                 reg = <0 0xe6e58000 0 64>;
 382                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 383                 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
 384                 clock-names = "sci_ick";
 385                 status = "disabled";
 386         };
 387
 388         scif3: serial@e6ea8000 {
 389                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 390                 reg = <0 0xe6ea8000 0 64>;
 391                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 392                 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
 393                 clock-names = "sci_ick";
 394                 status = "disabled";
 395         };
 396
 397         scif4: serial@e6ee0000 {
 398                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 399                 reg = <0 0xe6ee0000 0 64>;
 400                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 401                 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
 402                 clock-names = "sci_ick";
 403                 status = "disabled";
 404         };
 405
 406         scif5: serial@e6ee8000 {
 407                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 408                 reg = <0 0xe6ee8000 0 64>;
 409                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 410                 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
 411                 clock-names = "sci_ick";
 412                 status = "disabled";
 413         };
 414
 415         hscif0: serial@e62c0000 {
 416                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 417                 reg = <0 0xe62c0000 0 96>;
 418                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 419                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
 420                 clock-names = "sci_ick";
 421                 status = "disabled";
 422         };
 423
 424         hscif1: serial@e62c8000 {
 425                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 426                 reg = <0 0xe62c8000 0 96>;
 427                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 428                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
 429                 clock-names = "sci_ick";
 430                 status = "disabled";
 431         };
 432
 433         hscif2: serial@e62d0000 {
 434                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 435                 reg = <0 0xe62d0000 0 96>;
 436                 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 437                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
 438                 clock-names = "sci_ick";
 439                 status = "disabled";
 440         };
 441
 442         ether: ethernet@ee700000 {
 443                 compatible = "renesas,ether-r8a7791";
 444                 reg = <0 0xee700000 0 0x400>;
 445                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 446                 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
 447                 phy-mode = "rmii";
 448                 #address-cells = <1>;
 449                 #size-cells = <0>;
 450                 status = "disabled";
 451         };
 452
 453         sata0: sata@ee300000 {
 454                 compatible = "renesas,sata-r8a7791";
 455                 reg = <0 0xee300000 0 0x2000>;
 456                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 457                 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
 458                 status = "disabled";
 459         };
 460
 461         sata1: sata@ee500000 {
 462                 compatible = "renesas,sata-r8a7791";
 463                 reg = <0 0xee500000 0 0x2000>;
 464                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 465                 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
 466                 status = "disabled";
 467         };
 468
 469         clocks {
 470                 #address-cells = <2>;
 471                 #size-cells = <2>;
 472                 ranges;
 473
 474                 /* External root clock */
 475                 extal_clk: extal_clk {
 476                         compatible = "fixed-clock";
 477                         #clock-cells = <0>;
 478                         /* This value must be overriden by the board. */
 479                         clock-frequency = <0>;
 480                         clock-output-names = "extal";
 481                 };
 482
 483                 /* Special CPG clocks */
 484                 cpg_clocks: cpg_clocks@e6150000 {
 485                         compatible = "renesas,r8a7791-cpg-clocks",
 486                                      "renesas,rcar-gen2-cpg-clocks";
 487                         reg = <0 0xe6150000 0 0x1000>;
 488                         clocks = <&extal_clk>;
 489                         #clock-cells = <1>;
 490                         clock-output-names = "main", "pll0", "pll1", "pll3",
 491                                              "lb", "qspi", "sdh", "sd0", "z";
 492                 };
 493
 494                 /* Variable factor clocks */
 495                 sd1_clk: sd2_clk@e6150078 {
 496                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 497                         reg = <0 0xe6150078 0 4>;
 498                         clocks = <&pll1_div2_clk>;
 499                         #clock-cells = <0>;
 500                         clock-output-names = "sd1";
 501                 };
 502                 sd2_clk: sd3_clk@e615007c {
 503                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 504                         reg = <0 0xe615007c 0 4>;
 505                         clocks = <&pll1_div2_clk>;
 506                         #clock-cells = <0>;
 507                         clock-output-names = "sd2";
 508                 };
 509                 mmc0_clk: mmc0_clk@e6150240 {
 510                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 511                         reg = <0 0xe6150240 0 4>;
 512                         clocks = <&pll1_div2_clk>;
 513                         #clock-cells = <0>;
 514                         clock-output-names = "mmc0";
 515                 };
 516                 ssp_clk: ssp_clk@e6150248 {
 517                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 518                         reg = <0 0xe6150248 0 4>;
 519                         clocks = <&pll1_div2_clk>;
 520                         #clock-cells = <0>;
 521                         clock-output-names = "ssp";
 522                 };
 523                 ssprs_clk: ssprs_clk@e615024c {
 524                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 525                         reg = <0 0xe615024c 0 4>;
 526                         clocks = <&pll1_div2_clk>;
 527                         #clock-cells = <0>;
 528                         clock-output-names = "ssprs";
 529                 };
 530
 531                 /* Fixed factor clocks */
 532                 pll1_div2_clk: pll1_div2_clk {
 533                         compatible = "fixed-factor-clock";
 534                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 535                         #clock-cells = <0>;
 536                         clock-div = <2>;
 537                         clock-mult = <1>;
 538                         clock-output-names = "pll1_div2";
 539                 };
 540                 zg_clk: zg_clk {
 541                         compatible = "fixed-factor-clock";
 542                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 543                         #clock-cells = <0>;
 544                         clock-div = <3>;
 545                         clock-mult = <1>;
 546                         clock-output-names = "zg";
 547                 };
 548                 zx_clk: zx_clk {
 549                         compatible = "fixed-factor-clock";
 550                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 551                         #clock-cells = <0>;
 552                         clock-div = <3>;
 553                         clock-mult = <1>;
 554                         clock-output-names = "zx";
 555                 };
 556                 zs_clk: zs_clk {
 557                         compatible = "fixed-factor-clock";
 558                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 559                         #clock-cells = <0>;
 560                         clock-div = <6>;
 561                         clock-mult = <1>;
 562                         clock-output-names = "zs";
 563                 };
 564                 hp_clk: hp_clk {
 565                         compatible = "fixed-factor-clock";
 566                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 567                         #clock-cells = <0>;
 568                         clock-div = <12>;
 569                         clock-mult = <1>;
 570                         clock-output-names = "hp";
 571                 };
 572                 i_clk: i_clk {
 573                         compatible = "fixed-factor-clock";
 574                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 575                         #clock-cells = <0>;
 576                         clock-div = <2>;
 577                         clock-mult = <1>;
 578                         clock-output-names = "i";
 579                 };
 580                 b_clk: b_clk {
 581                         compatible = "fixed-factor-clock";
 582                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 583                         #clock-cells = <0>;
 584                         clock-div = <12>;
 585                         clock-mult = <1>;
 586                         clock-output-names = "b";
 587                 };
 588                 p_clk: p_clk {
 589                         compatible = "fixed-factor-clock";
 590                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 591                         #clock-cells = <0>;
 592                         clock-div = <24>;
 593                         clock-mult = <1>;
 594                         clock-output-names = "p";
 595                 };
 596                 cl_clk: cl_clk {
 597                         compatible = "fixed-factor-clock";
 598                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 599                         #clock-cells = <0>;
 600                         clock-div = <48>;
 601                         clock-mult = <1>;
 602                         clock-output-names = "cl";
 603                 };
 604                 m2_clk: m2_clk {
 605                         compatible = "fixed-factor-clock";
 606                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 607                         #clock-cells = <0>;
 608                         clock-div = <8>;
 609                         clock-mult = <1>;
 610                         clock-output-names = "m2";
 611                 };
 612                 imp_clk: imp_clk {
 613                         compatible = "fixed-factor-clock";
 614                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 615                         #clock-cells = <0>;
 616                         clock-div = <4>;
 617                         clock-mult = <1>;
 618                         clock-output-names = "imp";
 619                 };
 620                 rclk_clk: rclk_clk {
 621                         compatible = "fixed-factor-clock";
 622                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 623                         #clock-cells = <0>;
 624                         clock-div = <(48 * 1024)>;
 625                         clock-mult = <1>;
 626                         clock-output-names = "rclk";
 627                 };
 628                 oscclk_clk: oscclk_clk {
 629                         compatible = "fixed-factor-clock";
 630                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 631                         #clock-cells = <0>;
 632                         clock-div = <(12 * 1024)>;
 633                         clock-mult = <1>;
 634                         clock-output-names = "oscclk";
 635                 };
 636                 zb3_clk: zb3_clk {
 637                         compatible = "fixed-factor-clock";
 638                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 639                         #clock-cells = <0>;
 640                         clock-div = <4>;
 641                         clock-mult = <1>;
 642                         clock-output-names = "zb3";
 643                 };
 644                 zb3d2_clk: zb3d2_clk {
 645                         compatible = "fixed-factor-clock";
 646                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 647                         #clock-cells = <0>;
 648                         clock-div = <8>;
 649                         clock-mult = <1>;
 650                         clock-output-names = "zb3d2";
 651                 };
 652                 ddr_clk: ddr_clk {
 653                         compatible = "fixed-factor-clock";
 654                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 655                         #clock-cells = <0>;
 656                         clock-div = <8>;
 657                         clock-mult = <1>;
 658                         clock-output-names = "ddr";
 659                 };
 660                 mp_clk: mp_clk {
 661                         compatible = "fixed-factor-clock";
 662                         clocks = <&pll1_div2_clk>;
 663                         #clock-cells = <0>;
 664                         clock-div = <15>;
 665                         clock-mult = <1>;
 666                         clock-output-names = "mp";
 667                 };
 668                 cp_clk: cp_clk {
 669                         compatible = "fixed-factor-clock";
 670                         clocks = <&extal_clk>;
 671                         #clock-cells = <0>;
 672                         clock-div = <2>;
 673                         clock-mult = <1>;
 674                         clock-output-names = "cp";
 675                 };
 676
 677                 /* Gate clocks */
 678                 mstp0_clks: mstp0_clks@e6150130 {
 679                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 680                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
 681                         clocks = <&mp_clk>;
 682                         #clock-cells = <1>;
 683                         renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
 684                         clock-output-names = "msiof0";
 685                 };
 686                 mstp1_clks: mstp1_clks@e6150134 {
 687                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 688                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 689                         clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
 690                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
 691                         #clock-cells = <1>;
 692                         renesas,clock-indices = <
 693                                 R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
 694                                 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
 695                                 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S
 696                         >;
 697                         clock-output-names =
 698                                 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
 699                                 "vsp1-du0", "vsp1-sy";
 700                 };
 701                 mstp2_clks: mstp2_clks@e6150138 {
 702                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 703                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 704                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 705                                  <&mp_clk>, <&mp_clk>, <&mp_clk>;
 706                         #clock-cells = <1>;
 707                         renesas,clock-indices = <
 708                                 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
 709                                 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
 710                                 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
 711                         >;
 712                         clock-output-names =
 713                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
 714                                 "scifb1", "msiof1", "scifb2";
 715                 };
 716                 mstp3_clks: mstp3_clks@e615013c {
 717                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 718                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 719                         clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
 720                                  <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>;
 721                         #clock-cells = <1>;
 722                         renesas,clock-indices = <
 723                                 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
 724                                 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_IIC1 R8A7791_CLK_CMT1
 725                         >;
 726                         clock-output-names =
 727                                 "tpu0", "sdhi2", "sdhi1", "sdhi0",
 728                                 "mmcif0", "i2c7", "i2c8", "cmt1";
 729                 };
 730                 mstp5_clks: mstp5_clks@e6150144 {
 731                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 732                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
 733                         clocks = <&extal_clk>, <&p_clk>;
 734                         #clock-cells = <1>;
 735                         renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
 736                         clock-output-names = "thermal", "pwm";
 737                 };
 738                 mstp7_clks: mstp7_clks@e615014c {
 739                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 740                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 741                         clocks = <&mp_clk>,  <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
 742                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 743                                  <&zx_clk>, <&zx_clk>, <&zx_clk>;
 744                         #clock-cells = <1>;
 745                         renesas,clock-indices = <
 746                                 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
 747                                 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
 748                                 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
 749                                 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
 750                                 R8A7791_CLK_LVDS0
 751                         >;
 752                         clock-output-names =
 753                                 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
 754                                 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
 755                 };
 756                 mstp8_clks: mstp8_clks@e6150990 {
 757                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 758                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 759                         clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
 760                                  <&zs_clk>;
 761                         #clock-cells = <1>;
 762                         renesas,clock-indices = <
 763                                 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
 764                                 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
 765                         >;
 766                         clock-output-names =
 767                                 "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
 768                 };
 769                 mstp9_clks: mstp9_clks@e6150994 {
 770                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 771                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 772                         clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&p_clk>,
 773                                  <&cp_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 774                                  <&p_clk>, <&p_clk>;
 775                         #clock-cells = <1>;
 776                         renesas,clock-indices = <
 777                                 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
 778                                 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
 779                                 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
 780                         >;
 781                         clock-output-names =
 782                                 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3",
 783                                 "i2c2", "i2c1", "i2c0";
 784                 };
 785                 mstp11_clks: mstp11_clks@e615099c {
 786                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 787                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
 788                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
 789                         #clock-cells = <1>;
 790                         renesas,clock-indices = <
 791                                 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
 792                         >;
 793                         clock-output-names = "scifa3", "scifa4", "scifa5";
 794                 };
 795         };
 796
 797         qspi: spi@e6b10000 {
 798                 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
 799                 reg = <0 0xe6b10000 0 0x2c>;
 800                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
 801                 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
 802                 num-cs = <1>;
 803                 #address-cells = <1>;
 804                 #size-cells = <0>;
 805                 status = "disabled";
 806         };
 807
 808         msiof0: spi@e6e20000 {
 809                 compatible = "renesas,msiof-r8a7791";
 810                 reg = <0 0xe6e20000 0 0x0064>;
 811                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
 812                 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
 813                 #address-cells = <1>;
 814                 #size-cells = <0>;
 815                 status = "disabled";
 816         };
 817
 818         msiof1: spi@e6e10000 {
 819                 compatible = "renesas,msiof-r8a7791";
 820                 reg = <0 0xe6e10000 0 0x0064>;
 821                 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
 822                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
 823                 #address-cells = <1>;
 824                 #size-cells = <0>;
 825                 status = "disabled";
 826         };
 827
 828         msiof2: spi@e6e00000 {
 829                 compatible = "renesas,msiof-r8a7791";
 830                 reg = <0 0xe6e00000 0 0x0064>;
 831                 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
 832                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
 833                 #address-cells = <1>;
 834                 #size-cells = <0>;
 835                 status = "disabled";
 836         };
 837 };