arch/arm/boot/dts/r8a7791.dtsi

   1 /*
   2  * Device Tree Source for the r8a7791 SoC
   3  *
   4  * Copyright (C) 2013 Renesas Electronics Corporation
   5  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   6  * Copyright (C) 2014 Cogent Embedded Inc.
   7  *
   8  * This file is licensed under the terms of the GNU General Public License
   9  * version 2.  This program is licensed "as is" without any warranty of any
  10  * kind, whether express or implied.
  11  */
  12
  13 #include <dt-bindings/clock/r8a7791-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16
  17 / {
  18         compatible = "renesas,r8a7791";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 i2c6 = &i2c6;
  31                 i2c7 = &i2c7;
  32                 i2c8 = &i2c8;
  33                 spi0 = &qspi;
  34                 spi1 = &msiof0;
  35                 spi2 = &msiof1;
  36                 spi3 = &msiof2;
  37         };
  38
  39         cpus {
  40                 #address-cells = <1>;
  41                 #size-cells = <0>;
  42
  43                 cpu0: cpu@0 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a15";
  46                         reg = <0>;
  47                         clock-frequency = <1500000000>;
  48                         voltage-tolerance = <1>; /* 1% */
  49                         clocks = <&cpg_clocks R8A7791_CLK_Z>;
  50                         clock-latency = <300000>; /* 300 us */
  51
  52                         /* kHz - uV - OPPs unknown yet */
  53                         operating-points = <1500000 1000000>,
  54                                            <1312500 1000000>,
  55                                            <1125000 1000000>,
  56                                            < 937500 1000000>,
  57                                            < 750000 1000000>,
  58                                            < 375000 1000000>;
  59                 };
  60
  61                 cpu1: cpu@1 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a15";
  64                         reg = <1>;
  65                         clock-frequency = <1500000000>;
  66                 };
  67         };
  68
  69         gic: interrupt-controller@f1001000 {
  70                 compatible = "arm,cortex-a15-gic";
  71                 #interrupt-cells = <3>;
  72                 #address-cells = <0>;
  73                 interrupt-controller;
  74                 reg = <0 0xf1001000 0 0x1000>,
  75                         <0 0xf1002000 0 0x1000>,
  76                         <0 0xf1004000 0 0x2000>,
  77                         <0 0xf1006000 0 0x2000>;
  78                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  79         };
  80
  81         gpio0: gpio@e6050000 {
  82                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  83                 reg = <0 0xe6050000 0 0x50>;
  84                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
  85                 #gpio-cells = <2>;
  86                 gpio-controller;
  87                 gpio-ranges = <&pfc 0 0 32>;
  88                 #interrupt-cells = <2>;
  89                 interrupt-controller;
  90                 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
  91         };
  92
  93         gpio1: gpio@e6051000 {
  94                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  95                 reg = <0 0xe6051000 0 0x50>;
  96                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
  97                 #gpio-cells = <2>;
  98                 gpio-controller;
  99                 gpio-ranges = <&pfc 0 32 32>;
 100                 #interrupt-cells = <2>;
 101                 interrupt-controller;
 102                 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
 103         };
 104
 105         gpio2: gpio@e6052000 {
 106                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 107                 reg = <0 0xe6052000 0 0x50>;
 108                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 109                 #gpio-cells = <2>;
 110                 gpio-controller;
 111                 gpio-ranges = <&pfc 0 64 32>;
 112                 #interrupt-cells = <2>;
 113                 interrupt-controller;
 114                 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
 115         };
 116
 117         gpio3: gpio@e6053000 {
 118                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 119                 reg = <0 0xe6053000 0 0x50>;
 120                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 121                 #gpio-cells = <2>;
 122                 gpio-controller;
 123                 gpio-ranges = <&pfc 0 96 32>;
 124                 #interrupt-cells = <2>;
 125                 interrupt-controller;
 126                 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
 127         };
 128
 129         gpio4: gpio@e6054000 {
 130                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 131                 reg = <0 0xe6054000 0 0x50>;
 132                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 133                 #gpio-cells = <2>;
 134                 gpio-controller;
 135                 gpio-ranges = <&pfc 0 128 32>;
 136                 #interrupt-cells = <2>;
 137                 interrupt-controller;
 138                 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
 139         };
 140
 141         gpio5: gpio@e6055000 {
 142                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 143                 reg = <0 0xe6055000 0 0x50>;
 144                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 145                 #gpio-cells = <2>;
 146                 gpio-controller;
 147                 gpio-ranges = <&pfc 0 160 32>;
 148                 #interrupt-cells = <2>;
 149                 interrupt-controller;
 150                 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
 151         };
 152
 153         gpio6: gpio@e6055400 {
 154                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 155                 reg = <0 0xe6055400 0 0x50>;
 156                 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 157                 #gpio-cells = <2>;
 158                 gpio-controller;
 159                 gpio-ranges = <&pfc 0 192 32>;
 160                 #interrupt-cells = <2>;
 161                 interrupt-controller;
 162                 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
 163         };
 164
 165         gpio7: gpio@e6055800 {
 166                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 167                 reg = <0 0xe6055800 0 0x50>;
 168                 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 169                 #gpio-cells = <2>;
 170                 gpio-controller;
 171                 gpio-ranges = <&pfc 0 224 26>;
 172                 #interrupt-cells = <2>;
 173                 interrupt-controller;
 174                 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
 175         };
 176
 177         thermal@e61f0000 {
 178                 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
 179                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 180                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 181                 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
 182         };
 183
 184         timer {
 185                 compatible = "arm,armv7-timer";
 186                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 187                              <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 188                              <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 189                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 190         };
 191
 192         irqc0: interrupt-controller@e61c0000 {
 193                 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
 194                 #interrupt-cells = <2>;
 195                 interrupt-controller;
 196                 reg = <0 0xe61c0000 0 0x200>;
 197                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 198                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 199                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 200                              <0 3 IRQ_TYPE_LEVEL_HIGH>,
 201                              <0 12 IRQ_TYPE_LEVEL_HIGH>,
 202                              <0 13 IRQ_TYPE_LEVEL_HIGH>,
 203                              <0 14 IRQ_TYPE_LEVEL_HIGH>,
 204                              <0 15 IRQ_TYPE_LEVEL_HIGH>,
 205                              <0 16 IRQ_TYPE_LEVEL_HIGH>,
 206                              <0 17 IRQ_TYPE_LEVEL_HIGH>;
 207         };
 208
 209         /* The memory map in the User's Manual maps the cores to bus numbers */
 210         i2c0: i2c@e6508000 {
 211                 #address-cells = <1>;
 212                 #size-cells = <0>;
 213                 compatible = "renesas,i2c-r8a7791";
 214                 reg = <0 0xe6508000 0 0x40>;
 215                 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 216                 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
 217                 status = "disabled";
 218         };
 219
 220         i2c1: i2c@e6518000 {
 221                 #address-cells = <1>;
 222                 #size-cells = <0>;
 223                 compatible = "renesas,i2c-r8a7791";
 224                 reg = <0 0xe6518000 0 0x40>;
 225                 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 226                 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
 227                 status = "disabled";
 228         };
 229
 230         i2c2: i2c@e6530000 {
 231                 #address-cells = <1>;
 232                 #size-cells = <0>;
 233                 compatible = "renesas,i2c-r8a7791";
 234                 reg = <0 0xe6530000 0 0x40>;
 235                 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 236                 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
 237                 status = "disabled";
 238         };
 239
 240         i2c3: i2c@e6540000 {
 241                 #address-cells = <1>;
 242                 #size-cells = <0>;
 243                 compatible = "renesas,i2c-r8a7791";
 244                 reg = <0 0xe6540000 0 0x40>;
 245                 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 246                 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
 247                 status = "disabled";
 248         };
 249
 250         i2c4: i2c@e6520000 {
 251                 #address-cells = <1>;
 252                 #size-cells = <0>;
 253                 compatible = "renesas,i2c-r8a7791";
 254                 reg = <0 0xe6520000 0 0x40>;
 255                 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
 256                 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
 257                 status = "disabled";
 258         };
 259
 260         i2c5: i2c@e6528000 {
 261                 /* doesn't need pinmux */
 262                 #address-cells = <1>;
 263                 #size-cells = <0>;
 264                 compatible = "renesas,i2c-r8a7791";
 265                 reg = <0 0xe6528000 0 0x40>;
 266                 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
 267                 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
 268                 status = "disabled";
 269         };
 270
 271         i2c6: i2c@e60b0000 {
 272                 /* doesn't need pinmux */
 273                 #address-cells = <1>;
 274                 #size-cells = <0>;
 275                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 276                 reg = <0 0xe60b0000 0 0x425>;
 277                 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
 278                 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
 279                 status = "disabled";
 280         };
 281
 282         i2c7: i2c@e6500000 {
 283                 #address-cells = <1>;
 284                 #size-cells = <0>;
 285                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 286                 reg = <0 0xe6500000 0 0x425>;
 287                 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
 288                 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
 289                 status = "disabled";
 290         };
 291
 292         i2c8: i2c@e6510000 {
 293                 #address-cells = <1>;
 294                 #size-cells = <0>;
 295                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 296                 reg = <0 0xe6510000 0 0x425>;
 297                 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
 298                 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
 299                 status = "disabled";
 300         };
 301
 302         pfc: pfc@e6060000 {
 303                 compatible = "renesas,pfc-r8a7791";
 304                 reg = <0 0xe6060000 0 0x250>;
 305                 #gpio-range-cells = <3>;
 306         };
 307
 308         sdhi0: sd@ee100000 {
 309                 compatible = "renesas,sdhi-r8a7791";
 310                 reg = <0 0xee100000 0 0x200>;
 311                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 312                 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
 313                 status = "disabled";
 314         };
 315
 316         sdhi1: sd@ee140000 {
 317                 compatible = "renesas,sdhi-r8a7791";
 318                 reg = <0 0xee140000 0 0x100>;
 319                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 320                 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
 321                 status = "disabled";
 322         };
 323
 324         sdhi2: sd@ee160000 {
 325                 compatible = "renesas,sdhi-r8a7791";
 326                 reg = <0 0xee160000 0 0x100>;
 327                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 328                 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
 329                 status = "disabled";
 330         };
 331
 332         scifa0: serial@e6c40000 {
 333                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 334                 reg = <0 0xe6c40000 0 64>;
 335                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 336                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
 337                 clock-names = "sci_ick";
 338                 status = "disabled";
 339         };
 340
 341         scifa1: serial@e6c50000 {
 342                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 343                 reg = <0 0xe6c50000 0 64>;
 344                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 345                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
 346                 clock-names = "sci_ick";
 347                 status = "disabled";
 348         };
 349
 350         scifa2: serial@e6c60000 {
 351                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 352                 reg = <0 0xe6c60000 0 64>;
 353                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 354                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
 355                 clock-names = "sci_ick";
 356                 status = "disabled";
 357         };
 358
 359         scifa3: serial@e6c70000 {
 360                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 361                 reg = <0 0xe6c70000 0 64>;
 362                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 363                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
 364                 clock-names = "sci_ick";
 365                 status = "disabled";
 366         };
 367
 368         scifa4: serial@e6c78000 {
 369                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 370                 reg = <0 0xe6c78000 0 64>;
 371                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 372                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
 373                 clock-names = "sci_ick";
 374                 status = "disabled";
 375         };
 376
 377         scifa5: serial@e6c80000 {
 378                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 379                 reg = <0 0xe6c80000 0 64>;
 380                 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 381                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
 382                 clock-names = "sci_ick";
 383                 status = "disabled";
 384         };
 385
 386         scifb0: serial@e6c20000 {
 387                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 388                 reg = <0 0xe6c20000 0 64>;
 389                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 390                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
 391                 clock-names = "sci_ick";
 392                 status = "disabled";
 393         };
 394
 395         scifb1: serial@e6c30000 {
 396                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 397                 reg = <0 0xe6c30000 0 64>;
 398                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 399                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
 400                 clock-names = "sci_ick";
 401                 status = "disabled";
 402         };
 403
 404         scifb2: serial@e6ce0000 {
 405                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 406                 reg = <0 0xe6ce0000 0 64>;
 407                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 408                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
 409                 clock-names = "sci_ick";
 410                 status = "disabled";
 411         };
 412
 413         scif0: serial@e6e60000 {
 414                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 415                 reg = <0 0xe6e60000 0 64>;
 416                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 417                 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
 418                 clock-names = "sci_ick";
 419                 status = "disabled";
 420         };
 421
 422         scif1: serial@e6e68000 {
 423                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 424                 reg = <0 0xe6e68000 0 64>;
 425                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 426                 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
 427                 clock-names = "sci_ick";
 428                 status = "disabled";
 429         };
 430
 431         scif2: serial@e6e58000 {
 432                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 433                 reg = <0 0xe6e58000 0 64>;
 434                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 435                 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
 436                 clock-names = "sci_ick";
 437                 status = "disabled";
 438         };
 439
 440         scif3: serial@e6ea8000 {
 441                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 442                 reg = <0 0xe6ea8000 0 64>;
 443                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 444                 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
 445                 clock-names = "sci_ick";
 446                 status = "disabled";
 447         };
 448
 449         scif4: serial@e6ee0000 {
 450                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 451                 reg = <0 0xe6ee0000 0 64>;
 452                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 453                 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
 454                 clock-names = "sci_ick";
 455                 status = "disabled";
 456         };
 457
 458         scif5: serial@e6ee8000 {
 459                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 460                 reg = <0 0xe6ee8000 0 64>;
 461                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 462                 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
 463                 clock-names = "sci_ick";
 464                 status = "disabled";
 465         };
 466
 467         hscif0: serial@e62c0000 {
 468                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 469                 reg = <0 0xe62c0000 0 96>;
 470                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 471                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
 472                 clock-names = "sci_ick";
 473                 status = "disabled";
 474         };
 475
 476         hscif1: serial@e62c8000 {
 477                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 478                 reg = <0 0xe62c8000 0 96>;
 479                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 480                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
 481                 clock-names = "sci_ick";
 482                 status = "disabled";
 483         };
 484
 485         hscif2: serial@e62d0000 {
 486                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 487                 reg = <0 0xe62d0000 0 96>;
 488                 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 489                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
 490                 clock-names = "sci_ick";
 491                 status = "disabled";
 492         };
 493
 494         ether: ethernet@ee700000 {
 495                 compatible = "renesas,ether-r8a7791";
 496                 reg = <0 0xee700000 0 0x400>;
 497                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 498                 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
 499                 phy-mode = "rmii";
 500                 #address-cells = <1>;
 501                 #size-cells = <0>;
 502                 status = "disabled";
 503         };
 504
 505         sata0: sata@ee300000 {
 506                 compatible = "renesas,sata-r8a7791";
 507                 reg = <0 0xee300000 0 0x2000>;
 508                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 509                 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
 510                 status = "disabled";
 511         };
 512
 513         sata1: sata@ee500000 {
 514                 compatible = "renesas,sata-r8a7791";
 515                 reg = <0 0xee500000 0 0x2000>;
 516                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 517                 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
 518                 status = "disabled";
 519         };
 520
 521         clocks {
 522                 #address-cells = <2>;
 523                 #size-cells = <2>;
 524                 ranges;
 525
 526                 /* External root clock */
 527                 extal_clk: extal_clk {
 528                         compatible = "fixed-clock";
 529                         #clock-cells = <0>;
 530                         /* This value must be overriden by the board. */
 531                         clock-frequency = <0>;
 532                         clock-output-names = "extal";
 533                 };
 534
 535                 /* Special CPG clocks */
 536                 cpg_clocks: cpg_clocks@e6150000 {
 537                         compatible = "renesas,r8a7791-cpg-clocks",
 538                                      "renesas,rcar-gen2-cpg-clocks";
 539                         reg = <0 0xe6150000 0 0x1000>;
 540                         clocks = <&extal_clk>;
 541                         #clock-cells = <1>;
 542                         clock-output-names = "main", "pll0", "pll1", "pll3",
 543                                              "lb", "qspi", "sdh", "sd0", "z";
 544                 };
 545
 546                 /* Variable factor clocks */
 547                 sd1_clk: sd2_clk@e6150078 {
 548                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 549                         reg = <0 0xe6150078 0 4>;
 550                         clocks = <&pll1_div2_clk>;
 551                         #clock-cells = <0>;
 552                         clock-output-names = "sd1";
 553                 };
 554                 sd2_clk: sd3_clk@e615026c {
 555                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 556                         reg = <0 0xe615026c 0 4>;
 557                         clocks = <&pll1_div2_clk>;
 558                         #clock-cells = <0>;
 559                         clock-output-names = "sd2";
 560                 };
 561                 mmc0_clk: mmc0_clk@e6150240 {
 562                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 563                         reg = <0 0xe6150240 0 4>;
 564                         clocks = <&pll1_div2_clk>;
 565                         #clock-cells = <0>;
 566                         clock-output-names = "mmc0";
 567                 };
 568                 ssp_clk: ssp_clk@e6150248 {
 569                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 570                         reg = <0 0xe6150248 0 4>;
 571                         clocks = <&pll1_div2_clk>;
 572                         #clock-cells = <0>;
 573                         clock-output-names = "ssp";
 574                 };
 575                 ssprs_clk: ssprs_clk@e615024c {
 576                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 577                         reg = <0 0xe615024c 0 4>;
 578                         clocks = <&pll1_div2_clk>;
 579                         #clock-cells = <0>;
 580                         clock-output-names = "ssprs";
 581                 };
 582
 583                 /* Fixed factor clocks */
 584                 pll1_div2_clk: pll1_div2_clk {
 585                         compatible = "fixed-factor-clock";
 586                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 587                         #clock-cells = <0>;
 588                         clock-div = <2>;
 589                         clock-mult = <1>;
 590                         clock-output-names = "pll1_div2";
 591                 };
 592                 zg_clk: zg_clk {
 593                         compatible = "fixed-factor-clock";
 594                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 595                         #clock-cells = <0>;
 596                         clock-div = <3>;
 597                         clock-mult = <1>;
 598                         clock-output-names = "zg";
 599                 };
 600                 zx_clk: zx_clk {
 601                         compatible = "fixed-factor-clock";
 602                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 603                         #clock-cells = <0>;
 604                         clock-div = <3>;
 605                         clock-mult = <1>;
 606                         clock-output-names = "zx";
 607                 };
 608                 zs_clk: zs_clk {
 609                         compatible = "fixed-factor-clock";
 610                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 611                         #clock-cells = <0>;
 612                         clock-div = <6>;
 613                         clock-mult = <1>;
 614                         clock-output-names = "zs";
 615                 };
 616                 hp_clk: hp_clk {
 617                         compatible = "fixed-factor-clock";
 618                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 619                         #clock-cells = <0>;
 620                         clock-div = <12>;
 621                         clock-mult = <1>;
 622                         clock-output-names = "hp";
 623                 };
 624                 i_clk: i_clk {
 625                         compatible = "fixed-factor-clock";
 626                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 627                         #clock-cells = <0>;
 628                         clock-div = <2>;
 629                         clock-mult = <1>;
 630                         clock-output-names = "i";
 631                 };
 632                 b_clk: b_clk {
 633                         compatible = "fixed-factor-clock";
 634                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 635                         #clock-cells = <0>;
 636                         clock-div = <12>;
 637                         clock-mult = <1>;
 638                         clock-output-names = "b";
 639                 };
 640                 p_clk: p_clk {
 641                         compatible = "fixed-factor-clock";
 642                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 643                         #clock-cells = <0>;
 644                         clock-div = <24>;
 645                         clock-mult = <1>;
 646                         clock-output-names = "p";
 647                 };
 648                 cl_clk: cl_clk {
 649                         compatible = "fixed-factor-clock";
 650                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 651                         #clock-cells = <0>;
 652                         clock-div = <48>;
 653                         clock-mult = <1>;
 654                         clock-output-names = "cl";
 655                 };
 656                 m2_clk: m2_clk {
 657                         compatible = "fixed-factor-clock";
 658                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 659                         #clock-cells = <0>;
 660                         clock-div = <8>;
 661                         clock-mult = <1>;
 662                         clock-output-names = "m2";
 663                 };
 664                 imp_clk: imp_clk {
 665                         compatible = "fixed-factor-clock";
 666                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 667                         #clock-cells = <0>;
 668                         clock-div = <4>;
 669                         clock-mult = <1>;
 670                         clock-output-names = "imp";
 671                 };
 672                 rclk_clk: rclk_clk {
 673                         compatible = "fixed-factor-clock";
 674                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 675                         #clock-cells = <0>;
 676                         clock-div = <(48 * 1024)>;
 677                         clock-mult = <1>;
 678                         clock-output-names = "rclk";
 679                 };
 680                 oscclk_clk: oscclk_clk {
 681                         compatible = "fixed-factor-clock";
 682                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 683                         #clock-cells = <0>;
 684                         clock-div = <(12 * 1024)>;
 685                         clock-mult = <1>;
 686                         clock-output-names = "oscclk";
 687                 };
 688                 zb3_clk: zb3_clk {
 689                         compatible = "fixed-factor-clock";
 690                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 691                         #clock-cells = <0>;
 692                         clock-div = <4>;
 693                         clock-mult = <1>;
 694                         clock-output-names = "zb3";
 695                 };
 696                 zb3d2_clk: zb3d2_clk {
 697                         compatible = "fixed-factor-clock";
 698                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 699                         #clock-cells = <0>;
 700                         clock-div = <8>;
 701                         clock-mult = <1>;
 702                         clock-output-names = "zb3d2";
 703                 };
 704                 ddr_clk: ddr_clk {
 705                         compatible = "fixed-factor-clock";
 706                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 707                         #clock-cells = <0>;
 708                         clock-div = <8>;
 709                         clock-mult = <1>;
 710                         clock-output-names = "ddr";
 711                 };
 712                 mp_clk: mp_clk {
 713                         compatible = "fixed-factor-clock";
 714                         clocks = <&pll1_div2_clk>;
 715                         #clock-cells = <0>;
 716                         clock-div = <15>;
 717                         clock-mult = <1>;
 718                         clock-output-names = "mp";
 719                 };
 720                 cp_clk: cp_clk {
 721                         compatible = "fixed-factor-clock";
 722                         clocks = <&extal_clk>;
 723                         #clock-cells = <0>;
 724                         clock-div = <2>;
 725                         clock-mult = <1>;
 726                         clock-output-names = "cp";
 727                 };
 728
 729                 /* Gate clocks */
 730                 mstp0_clks: mstp0_clks@e6150130 {
 731                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 732                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
 733                         clocks = <&mp_clk>;
 734                         #clock-cells = <1>;
 735                         renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
 736                         clock-output-names = "msiof0";
 737                 };
 738                 mstp1_clks: mstp1_clks@e6150134 {
 739                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 740                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 741                         clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
 742                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
 743                         #clock-cells = <1>;
 744                         renesas,clock-indices = <
 745                                 R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
 746                                 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
 747                                 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S
 748                         >;
 749                         clock-output-names =
 750                                 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
 751                                 "vsp1-du0", "vsp1-sy";
 752                 };
 753                 mstp2_clks: mstp2_clks@e6150138 {
 754                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 755                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 756                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 757                                  <&mp_clk>, <&mp_clk>, <&mp_clk>,
 758                                  <&zs_clk>, <&zs_clk>;
 759                         #clock-cells = <1>;
 760                         renesas,clock-indices = <
 761                                 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
 762                                 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
 763                                 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
 764                                 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
 765                         >;
 766                         clock-output-names =
 767                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
 768                                 "scifb1", "msiof1", "scifb2",
 769                                 "sys-dmac1", "sys-dmac0";
 770                 };
 771                 mstp3_clks: mstp3_clks@e615013c {
 772                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 773                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 774                         clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
 775                                  <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
 776                         #clock-cells = <1>;
 777                         renesas,clock-indices = <
 778                                 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
 779                                 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_IIC1 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
 780                         >;
 781                         clock-output-names =
 782                                 "tpu0", "sdhi2", "sdhi1", "sdhi0",
 783                                 "mmcif0", "i2c7", "i2c8", "ssusb", "cmt1";
 784                 };
 785                 mstp5_clks: mstp5_clks@e6150144 {
 786                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 787                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
 788                         clocks = <&extal_clk>, <&p_clk>;
 789                         #clock-cells = <1>;
 790                         renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
 791                         clock-output-names = "thermal", "pwm";
 792                 };
 793                 mstp7_clks: mstp7_clks@e615014c {
 794                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 795                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 796                         clocks = <&mp_clk>,  <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
 797                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 798                                  <&zx_clk>, <&zx_clk>, <&zx_clk>;
 799                         #clock-cells = <1>;
 800                         renesas,clock-indices = <
 801                                 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
 802                                 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
 803                                 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
 804                                 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
 805                                 R8A7791_CLK_LVDS0
 806                         >;
 807                         clock-output-names =
 808                                 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
 809                                 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
 810                 };
 811                 mstp8_clks: mstp8_clks@e6150990 {
 812                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 813                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 814                         clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
 815                                  <&zs_clk>;
 816                         #clock-cells = <1>;
 817                         renesas,clock-indices = <
 818                                 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
 819                                 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
 820                         >;
 821                         clock-output-names =
 822                                 "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
 823                 };
 824                 mstp9_clks: mstp9_clks@e6150994 {
 825                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 826                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 827                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
 828                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
 829                                  <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
 830                                  <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
 831                                  <&hp_clk>, <&hp_clk>;
 832                         #clock-cells = <1>;
 833                         renesas,clock-indices = <
 834                                 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
 835                                 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
 836                                 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
 837                                 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
 838                                 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
 839                         >;
 840                         clock-output-names =
 841                                 "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
 842                                 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
 843                                 "i2c1", "i2c0";
 844                 };
 845                 mstp11_clks: mstp11_clks@e615099c {
 846                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 847                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
 848                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
 849                         #clock-cells = <1>;
 850                         renesas,clock-indices = <
 851                                 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
 852                         >;
 853                         clock-output-names = "scifa3", "scifa4", "scifa5";
 854                 };
 855         };
 856
 857         qspi: spi@e6b10000 {
 858                 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
 859                 reg = <0 0xe6b10000 0 0x2c>;
 860                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
 861                 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
 862                 num-cs = <1>;
 863                 #address-cells = <1>;
 864                 #size-cells = <0>;
 865                 status = "disabled";
 866         };
 867
 868         msiof0: spi@e6e20000 {
 869                 compatible = "renesas,msiof-r8a7791";
 870                 reg = <0 0xe6e20000 0 0x0064>;
 871                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
 872                 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
 873                 #address-cells = <1>;
 874                 #size-cells = <0>;
 875                 status = "disabled";
 876         };
 877
 878         msiof1: spi@e6e10000 {
 879                 compatible = "renesas,msiof-r8a7791";
 880                 reg = <0 0xe6e10000 0 0x0064>;
 881                 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
 882                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
 883                 #address-cells = <1>;
 884                 #size-cells = <0>;
 885                 status = "disabled";
 886         };
 887
 888         msiof2: spi@e6e00000 {
 889                 compatible = "renesas,msiof-r8a7791";
 890                 reg = <0 0xe6e00000 0 0x0064>;
 891                 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
 892                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
 893                 #address-cells = <1>;
 894                 #size-cells = <0>;
 895                 status = "disabled";
 896         };
 897 };