arch/arm/boot/dts/r8a7791.dtsi

   1 /*
   2  * Device Tree Source for the r8a7791 SoC
   3  *
   4  * Copyright (C) 2013 Renesas Electronics Corporation
   5  * Copyright (C) 2013 Renesas Solutions Corp.
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a7791-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,r8a7791";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29         };
  30
  31         cpus {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34
  35                 cpu0: cpu@0 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a15";
  38                         reg = <0>;
  39                         clock-frequency = <1300000000>;
  40                 };
  41
  42                 cpu1: cpu@1 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a15";
  45                         reg = <1>;
  46                         clock-frequency = <1300000000>;
  47                 };
  48         };
  49
  50         gic: interrupt-controller@f1001000 {
  51                 compatible = "arm,cortex-a15-gic";
  52                 #interrupt-cells = <3>;
  53                 #address-cells = <0>;
  54                 interrupt-controller;
  55                 reg = <0 0xf1001000 0 0x1000>,
  56                         <0 0xf1002000 0 0x1000>,
  57                         <0 0xf1004000 0 0x2000>,
  58                         <0 0xf1006000 0 0x2000>;
  59                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  60         };
  61
  62         gpio0: gpio@e6050000 {
  63                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  64                 reg = <0 0xe6050000 0 0x50>;
  65                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
  66                 #gpio-cells = <2>;
  67                 gpio-controller;
  68                 gpio-ranges = <&pfc 0 0 32>;
  69                 #interrupt-cells = <2>;
  70                 interrupt-controller;
  71         };
  72
  73         gpio1: gpio@e6051000 {
  74                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  75                 reg = <0 0xe6051000 0 0x50>;
  76                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
  77                 #gpio-cells = <2>;
  78                 gpio-controller;
  79                 gpio-ranges = <&pfc 0 32 32>;
  80                 #interrupt-cells = <2>;
  81                 interrupt-controller;
  82         };
  83
  84         gpio2: gpio@e6052000 {
  85                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  86                 reg = <0 0xe6052000 0 0x50>;
  87                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
  88                 #gpio-cells = <2>;
  89                 gpio-controller;
  90                 gpio-ranges = <&pfc 0 64 32>;
  91                 #interrupt-cells = <2>;
  92                 interrupt-controller;
  93         };
  94
  95         gpio3: gpio@e6053000 {
  96                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  97                 reg = <0 0xe6053000 0 0x50>;
  98                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
  99                 #gpio-cells = <2>;
 100                 gpio-controller;
 101                 gpio-ranges = <&pfc 0 96 32>;
 102                 #interrupt-cells = <2>;
 103                 interrupt-controller;
 104         };
 105
 106         gpio4: gpio@e6054000 {
 107                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 108                 reg = <0 0xe6054000 0 0x50>;
 109                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 110                 #gpio-cells = <2>;
 111                 gpio-controller;
 112                 gpio-ranges = <&pfc 0 128 32>;
 113                 #interrupt-cells = <2>;
 114                 interrupt-controller;
 115         };
 116
 117         gpio5: gpio@e6055000 {
 118                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 119                 reg = <0 0xe6055000 0 0x50>;
 120                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 121                 #gpio-cells = <2>;
 122                 gpio-controller;
 123                 gpio-ranges = <&pfc 0 160 32>;
 124                 #interrupt-cells = <2>;
 125                 interrupt-controller;
 126         };
 127
 128         gpio6: gpio@e6055400 {
 129                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 130                 reg = <0 0xe6055400 0 0x50>;
 131                 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 132                 #gpio-cells = <2>;
 133                 gpio-controller;
 134                 gpio-ranges = <&pfc 0 192 32>;
 135                 #interrupt-cells = <2>;
 136                 interrupt-controller;
 137         };
 138
 139         gpio7: gpio@e6055800 {
 140                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 141                 reg = <0 0xe6055800 0 0x50>;
 142                 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 143                 #gpio-cells = <2>;
 144                 gpio-controller;
 145                 gpio-ranges = <&pfc 0 224 26>;
 146                 #interrupt-cells = <2>;
 147                 interrupt-controller;
 148         };
 149
 150         thermal@e61f0000 {
 151                 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
 152                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 153                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 154                 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
 155         };
 156
 157         timer {
 158                 compatible = "arm,armv7-timer";
 159                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 160                              <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 161                              <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 162                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 163         };
 164
 165         irqc0: interrupt-controller@e61c0000 {
 166                 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
 167                 #interrupt-cells = <2>;
 168                 interrupt-controller;
 169                 reg = <0 0xe61c0000 0 0x200>;
 170                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 171                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 172                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 173                              <0 3 IRQ_TYPE_LEVEL_HIGH>,
 174                              <0 12 IRQ_TYPE_LEVEL_HIGH>,
 175                              <0 13 IRQ_TYPE_LEVEL_HIGH>,
 176                              <0 14 IRQ_TYPE_LEVEL_HIGH>,
 177                              <0 15 IRQ_TYPE_LEVEL_HIGH>,
 178                              <0 16 IRQ_TYPE_LEVEL_HIGH>,
 179                              <0 17 IRQ_TYPE_LEVEL_HIGH>;
 180         };
 181
 182         i2c0: i2c@e6508000 {
 183                 #address-cells = <1>;
 184                 #size-cells = <0>;
 185                 compatible = "renesas,i2c-r8a7791";
 186                 reg = <0 0xe6508000 0 0x40>;
 187                 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 188                 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
 189                 status = "disabled";
 190         };
 191
 192         i2c1: i2c@e6518000 {
 193                 #address-cells = <1>;
 194                 #size-cells = <0>;
 195                 compatible = "renesas,i2c-r8a7791";
 196                 reg = <0 0xe6518000 0 0x40>;
 197                 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 198                 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
 199                 status = "disabled";
 200         };
 201
 202         i2c2: i2c@e6530000 {
 203                 #address-cells = <1>;
 204                 #size-cells = <0>;
 205                 compatible = "renesas,i2c-r8a7791";
 206                 reg = <0 0xe6530000 0 0x40>;
 207                 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 208                 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
 209                 status = "disabled";
 210         };
 211
 212         i2c3: i2c@e6540000 {
 213                 #address-cells = <1>;
 214                 #size-cells = <0>;
 215                 compatible = "renesas,i2c-r8a7791";
 216                 reg = <0 0xe6540000 0 0x40>;
 217                 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 218                 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
 219                 status = "disabled";
 220         };
 221
 222         i2c4: i2c@e6520000 {
 223                 #address-cells = <1>;
 224                 #size-cells = <0>;
 225                 compatible = "renesas,i2c-r8a7791";
 226                 reg = <0 0xe6520000 0 0x40>;
 227                 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
 228                 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
 229                 status = "disabled";
 230         };
 231
 232         i2c5: i2c@e6528000 {
 233                 #address-cells = <1>;
 234                 #size-cells = <0>;
 235                 compatible = "renesas,i2c-r8a7791";
 236                 reg = <0 0xe6528000 0 0x40>;
 237                 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
 238                 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
 239                 status = "disabled";
 240         };
 241
 242         pfc: pfc@e6060000 {
 243                 compatible = "renesas,pfc-r8a7791";
 244                 reg = <0 0xe6060000 0 0x250>;
 245                 #gpio-range-cells = <3>;
 246         };
 247
 248         scifa0: serial@e6c40000 {
 249                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 250                 reg = <0 0xe6c40000 0 64>;
 251                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 252                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
 253                 clock-names = "sci_ick";
 254                 status = "disabled";
 255         };
 256
 257         scifa1: serial@e6c50000 {
 258                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 259                 reg = <0 0xe6c50000 0 64>;
 260                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 261                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
 262                 clock-names = "sci_ick";
 263                 status = "disabled";
 264         };
 265
 266         scifa2: serial@e6c60000 {
 267                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 268                 reg = <0 0xe6c60000 0 64>;
 269                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 270                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
 271                 clock-names = "sci_ick";
 272                 status = "disabled";
 273         };
 274
 275         scifa3: serial@e6c70000 {
 276                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 277                 reg = <0 0xe6c70000 0 64>;
 278                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 279                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
 280                 clock-names = "sci_ick";
 281                 status = "disabled";
 282         };
 283
 284         scifa4: serial@e6c78000 {
 285                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 286                 reg = <0 0xe6c78000 0 64>;
 287                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 288                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
 289                 clock-names = "sci_ick";
 290                 status = "disabled";
 291         };
 292
 293         scifa5: serial@e6c80000 {
 294                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 295                 reg = <0 0xe6c80000 0 64>;
 296                 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 297                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
 298                 clock-names = "sci_ick";
 299                 status = "disabled";
 300         };
 301
 302         scifb0: serial@e6c20000 {
 303                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 304                 reg = <0 0xe6c20000 0 64>;
 305                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 306                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
 307                 clock-names = "sci_ick";
 308                 status = "disabled";
 309         };
 310
 311         scifb1: serial@e6c30000 {
 312                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 313                 reg = <0 0xe6c30000 0 64>;
 314                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 315                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
 316                 clock-names = "sci_ick";
 317                 status = "disabled";
 318         };
 319
 320         scifb2: serial@e6ce0000 {
 321                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 322                 reg = <0 0xe6ce0000 0 64>;
 323                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 324                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
 325                 clock-names = "sci_ick";
 326                 status = "disabled";
 327         };
 328
 329         scif0: serial@e6e60000 {
 330                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 331                 reg = <0 0xe6e60000 0 64>;
 332                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 333                 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
 334                 clock-names = "sci_ick";
 335                 status = "disabled";
 336         };
 337
 338         scif1: serial@e6e68000 {
 339                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 340                 reg = <0 0xe6e68000 0 64>;
 341                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 342                 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
 343                 clock-names = "sci_ick";
 344                 status = "disabled";
 345         };
 346
 347         scif2: serial@e6e58000 {
 348                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 349                 reg = <0 0xe6e58000 0 64>;
 350                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 351                 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
 352                 clock-names = "sci_ick";
 353                 status = "disabled";
 354         };
 355
 356         scif3: serial@e6ea8000 {
 357                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 358                 reg = <0 0xe6ea8000 0 64>;
 359                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 360                 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
 361                 clock-names = "sci_ick";
 362                 status = "disabled";
 363         };
 364
 365         scif4: serial@e6ee0000 {
 366                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 367                 reg = <0 0xe6ee0000 0 64>;
 368                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 369                 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
 370                 clock-names = "sci_ick";
 371                 status = "disabled";
 372         };
 373
 374         scif5: serial@e6ee8000 {
 375                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 376                 reg = <0 0xe6ee8000 0 64>;
 377                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 378                 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
 379                 clock-names = "sci_ick";
 380                 status = "disabled";
 381         };
 382
 383         hscif0: serial@e62c0000 {
 384                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 385                 reg = <0 0xe62c0000 0 96>;
 386                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 387                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
 388                 clock-names = "sci_ick";
 389                 status = "disabled";
 390         };
 391
 392         hscif1: serial@e62c8000 {
 393                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 394                 reg = <0 0xe62c8000 0 96>;
 395                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 396                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
 397                 clock-names = "sci_ick";
 398                 status = "disabled";
 399         };
 400
 401         hscif2: serial@e62d0000 {
 402                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 403                 reg = <0 0xe62d0000 0 96>;
 404                 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 405                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
 406                 clock-names = "sci_ick";
 407                 status = "disabled";
 408         };
 409
 410         sata0: sata@ee300000 {
 411                 compatible = "renesas,sata-r8a7791";
 412                 reg = <0 0xee300000 0 0x2000>;
 413                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 414                 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
 415                 status = "disabled";
 416         };
 417
 418         sata1: sata@ee500000 {
 419                 compatible = "renesas,sata-r8a7791";
 420                 reg = <0 0xee500000 0 0x2000>;
 421                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 422                 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
 423                 status = "disabled";
 424         };
 425
 426         clocks {
 427                 #address-cells = <2>;
 428                 #size-cells = <2>;
 429                 ranges;
 430
 431                 /* External root clock */
 432                 extal_clk: extal_clk {
 433                         compatible = "fixed-clock";
 434                         #clock-cells = <0>;
 435                         /* This value must be overriden by the board. */
 436                         clock-frequency = <0>;
 437                         clock-output-names = "extal";
 438                 };
 439
 440                 /* Special CPG clocks */
 441                 cpg_clocks: cpg_clocks@e6150000 {
 442                         compatible = "renesas,r8a7791-cpg-clocks",
 443                                      "renesas,rcar-gen2-cpg-clocks";
 444                         reg = <0 0xe6150000 0 0x1000>;
 445                         clocks = <&extal_clk>;
 446                         #clock-cells = <1>;
 447                         clock-output-names = "main", "pll0", "pll1", "pll3",
 448                                              "lb", "qspi", "sdh", "sd0", "z";
 449                 };
 450
 451                 /* Variable factor clocks */
 452                 sd1_clk: sd2_clk@e6150078 {
 453                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 454                         reg = <0 0xe6150078 0 4>;
 455                         clocks = <&pll1_div2_clk>;
 456                         #clock-cells = <0>;
 457                         clock-output-names = "sd1";
 458                 };
 459                 sd2_clk: sd3_clk@e615007c {
 460                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 461                         reg = <0 0xe615007c 0 4>;
 462                         clocks = <&pll1_div2_clk>;
 463                         #clock-cells = <0>;
 464                         clock-output-names = "sd2";
 465                 };
 466                 mmc0_clk: mmc0_clk@e6150240 {
 467                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 468                         reg = <0 0xe6150240 0 4>;
 469                         clocks = <&pll1_div2_clk>;
 470                         #clock-cells = <0>;
 471                         clock-output-names = "mmc0";
 472                 };
 473                 ssp_clk: ssp_clk@e6150248 {
 474                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 475                         reg = <0 0xe6150248 0 4>;
 476                         clocks = <&pll1_div2_clk>;
 477                         #clock-cells = <0>;
 478                         clock-output-names = "ssp";
 479                 };
 480                 ssprs_clk: ssprs_clk@e615024c {
 481                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 482                         reg = <0 0xe615024c 0 4>;
 483                         clocks = <&pll1_div2_clk>;
 484                         #clock-cells = <0>;
 485                         clock-output-names = "ssprs";
 486                 };
 487
 488                 /* Fixed factor clocks */
 489                 pll1_div2_clk: pll1_div2_clk {
 490                         compatible = "fixed-factor-clock";
 491                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 492                         #clock-cells = <0>;
 493                         clock-div = <2>;
 494                         clock-mult = <1>;
 495                         clock-output-names = "pll1_div2";
 496                 };
 497                 zg_clk: zg_clk {
 498                         compatible = "fixed-factor-clock";
 499                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 500                         #clock-cells = <0>;
 501                         clock-div = <3>;
 502                         clock-mult = <1>;
 503                         clock-output-names = "zg";
 504                 };
 505                 zx_clk: zx_clk {
 506                         compatible = "fixed-factor-clock";
 507                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 508                         #clock-cells = <0>;
 509                         clock-div = <3>;
 510                         clock-mult = <1>;
 511                         clock-output-names = "zx";
 512                 };
 513                 zs_clk: zs_clk {
 514                         compatible = "fixed-factor-clock";
 515                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 516                         #clock-cells = <0>;
 517                         clock-div = <6>;
 518                         clock-mult = <1>;
 519                         clock-output-names = "zs";
 520                 };
 521                 hp_clk: hp_clk {
 522                         compatible = "fixed-factor-clock";
 523                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 524                         #clock-cells = <0>;
 525                         clock-div = <12>;
 526                         clock-mult = <1>;
 527                         clock-output-names = "hp";
 528                 };
 529                 i_clk: i_clk {
 530                         compatible = "fixed-factor-clock";
 531                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 532                         #clock-cells = <0>;
 533                         clock-div = <2>;
 534                         clock-mult = <1>;
 535                         clock-output-names = "i";
 536                 };
 537                 b_clk: b_clk {
 538                         compatible = "fixed-factor-clock";
 539                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 540                         #clock-cells = <0>;
 541                         clock-div = <12>;
 542                         clock-mult = <1>;
 543                         clock-output-names = "b";
 544                 };
 545                 p_clk: p_clk {
 546                         compatible = "fixed-factor-clock";
 547                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 548                         #clock-cells = <0>;
 549                         clock-div = <24>;
 550                         clock-mult = <1>;
 551                         clock-output-names = "p";
 552                 };
 553                 cl_clk: cl_clk {
 554                         compatible = "fixed-factor-clock";
 555                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 556                         #clock-cells = <0>;
 557                         clock-div = <48>;
 558                         clock-mult = <1>;
 559                         clock-output-names = "cl";
 560                 };
 561                 m2_clk: m2_clk {
 562                         compatible = "fixed-factor-clock";
 563                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 564                         #clock-cells = <0>;
 565                         clock-div = <8>;
 566                         clock-mult = <1>;
 567                         clock-output-names = "m2";
 568                 };
 569                 imp_clk: imp_clk {
 570                         compatible = "fixed-factor-clock";
 571                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 572                         #clock-cells = <0>;
 573                         clock-div = <4>;
 574                         clock-mult = <1>;
 575                         clock-output-names = "imp";
 576                 };
 577                 rclk_clk: rclk_clk {
 578                         compatible = "fixed-factor-clock";
 579                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 580                         #clock-cells = <0>;
 581                         clock-div = <(48 * 1024)>;
 582                         clock-mult = <1>;
 583                         clock-output-names = "rclk";
 584                 };
 585                 oscclk_clk: oscclk_clk {
 586                         compatible = "fixed-factor-clock";
 587                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 588                         #clock-cells = <0>;
 589                         clock-div = <(12 * 1024)>;
 590                         clock-mult = <1>;
 591                         clock-output-names = "oscclk";
 592                 };
 593                 zb3_clk: zb3_clk {
 594                         compatible = "fixed-factor-clock";
 595                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 596                         #clock-cells = <0>;
 597                         clock-div = <4>;
 598                         clock-mult = <1>;
 599                         clock-output-names = "zb3";
 600                 };
 601                 zb3d2_clk: zb3d2_clk {
 602                         compatible = "fixed-factor-clock";
 603                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 604                         #clock-cells = <0>;
 605                         clock-div = <8>;
 606                         clock-mult = <1>;
 607                         clock-output-names = "zb3d2";
 608                 };
 609                 ddr_clk: ddr_clk {
 610                         compatible = "fixed-factor-clock";
 611                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 612                         #clock-cells = <0>;
 613                         clock-div = <8>;
 614                         clock-mult = <1>;
 615                         clock-output-names = "ddr";
 616                 };
 617                 mp_clk: mp_clk {
 618                         compatible = "fixed-factor-clock";
 619                         clocks = <&pll1_div2_clk>;
 620                         #clock-cells = <0>;
 621                         clock-div = <15>;
 622                         clock-mult = <1>;
 623                         clock-output-names = "mp";
 624                 };
 625                 cp_clk: cp_clk {
 626                         compatible = "fixed-factor-clock";
 627                         clocks = <&extal_clk>;
 628                         #clock-cells = <0>;
 629                         clock-div = <2>;
 630                         clock-mult = <1>;
 631                         clock-output-names = "cp";
 632                 };
 633
 634                 /* Gate clocks */
 635                 mstp0_clks: mstp0_clks@e6150130 {
 636                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 637                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
 638                         clocks = <&mp_clk>;
 639                         #clock-cells = <1>;
 640                         renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
 641                         clock-output-names = "msiof0";
 642                 };
 643                 mstp1_clks: mstp1_clks@e6150134 {
 644                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 645                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 646                         clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
 647                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
 648                         #clock-cells = <1>;
 649                         renesas,clock-indices = <
 650                                 R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
 651                                 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
 652                                 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_SY
 653                         >;
 654                         clock-output-names =
 655                                 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
 656                                 "vsp1-du0", "vsp1-sy";
 657                 };
 658                 mstp2_clks: mstp2_clks@e6150138 {
 659                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 660                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 661                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 662                                  <&mp_clk>, <&mp_clk>, <&mp_clk>;
 663                         #clock-cells = <1>;
 664                         renesas,clock-indices = <
 665                                 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
 666                                 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
 667                                 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
 668                         >;
 669                         clock-output-names =
 670                                 "scifa2", "scifa1", "scifa0", "misof2", "scifb0",
 671                                 "scifb1", "msiof1", "scifb2";
 672                 };
 673                 mstp3_clks: mstp3_clks@e615013c {
 674                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 675                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 676                         clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>,
 677                                 <&cpg_clocks R8A7791_CLK_SD0>, <&mmc0_clk>, <&rclk_clk>;
 678                         #clock-cells = <1>;
 679                         renesas,clock-indices = <
 680                                 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1
 681                                 R8A7791_CLK_SDHI0 R8A7791_CLK_MMCIF0 R8A7791_CLK_CMT1
 682                         >;
 683                         clock-output-names =
 684                                 "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", "cmt1";
 685                 };
 686                 mstp5_clks: mstp5_clks@e6150144 {
 687                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 688                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
 689                         clocks = <&extal_clk>, <&p_clk>;
 690                         #clock-cells = <1>;
 691                         renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
 692                         clock-output-names = "thermal", "pwm";
 693                 };
 694                 mstp7_clks: mstp7_clks@e615014c {
 695                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 696                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 697                         clocks = <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
 698                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 699                                  <&zx_clk>, <&zx_clk>, <&zx_clk>;
 700                         #clock-cells = <1>;
 701                         renesas,clock-indices = <
 702                                 R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
 703                                 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
 704                                 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
 705                                 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
 706                                 R8A7791_CLK_LVDS0
 707                         >;
 708                         clock-output-names =
 709                                 "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
 710                                 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
 711                 };
 712                 mstp8_clks: mstp8_clks@e6150990 {
 713                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 714                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 715                         clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
 716                                  <&zs_clk>;
 717                         #clock-cells = <1>;
 718                         renesas,clock-indices = <
 719                                 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
 720                                 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
 721                         >;
 722                         clock-output-names =
 723                                 "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
 724                 };
 725                 mstp9_clks: mstp9_clks@e6150994 {
 726                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 727                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 728                         clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>,
 729                                  <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 730                                  <&p_clk>;
 731                         #clock-cells = <1>;
 732                         renesas,clock-indices = <
 733                                 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD
 734                                 R8A7791_CLK_I2C4 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3
 735                                 R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
 736                         >;
 737                         clock-output-names =
 738                                 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3",
 739                                 "i2c2", "i2c1", "i2c0";
 740                 };
 741                 mstp11_clks: mstp11_clks@e615099c {
 742                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 743                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
 744                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
 745                         #clock-cells = <1>;
 746                         renesas,clock-indices = <
 747                                 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
 748                         >;
 749                         clock-output-names = "scifa3", "scifa4", "scifa5";
 750                 };
 751         };
 752
 753         spi: spi@e6b10000 {
 754                 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
 755                 reg = <0 0xe6b10000 0 0x2c>;
 756                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
 757                 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
 758                 num-cs = <1>;
 759                 #address-cells = <1>;
 760                 #size-cells = <0>;
 761                 status = "disabled";
 762         };
 763 };