arch/arm/boot/dts/r8a7791.dtsi

   1 /*
   2  * Device Tree Source for the r8a7791 SoC
   3  *
   4  * Copyright (C) 2013 Renesas Electronics Corporation
   5  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   6  * Copyright (C) 2014 Cogent Embedded Inc.
   7  *
   8  * This file is licensed under the terms of the GNU General Public License
   9  * version 2.  This program is licensed "as is" without any warranty of any
  10  * kind, whether express or implied.
  11  */
  12
  13 #include <dt-bindings/clock/r8a7791-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16
  17 / {
  18         compatible = "renesas,r8a7791";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 i2c6 = &i2c6;
  31                 i2c7 = &i2c7;
  32                 i2c8 = &i2c8;
  33                 spi0 = &qspi;
  34                 spi1 = &msiof0;
  35                 spi2 = &msiof1;
  36                 spi3 = &msiof2;
  37         };
  38
  39         cpus {
  40                 #address-cells = <1>;
  41                 #size-cells = <0>;
  42
  43                 cpu0: cpu@0 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a15";
  46                         reg = <0>;
  47                         clock-frequency = <1500000000>;
  48                 };
  49
  50                 cpu1: cpu@1 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a15";
  53                         reg = <1>;
  54                         clock-frequency = <1500000000>;
  55                 };
  56         };
  57
  58         gic: interrupt-controller@f1001000 {
  59                 compatible = "arm,cortex-a15-gic";
  60                 #interrupt-cells = <3>;
  61                 #address-cells = <0>;
  62                 interrupt-controller;
  63                 reg = <0 0xf1001000 0 0x1000>,
  64                         <0 0xf1002000 0 0x1000>,
  65                         <0 0xf1004000 0 0x2000>,
  66                         <0 0xf1006000 0 0x2000>;
  67                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  68         };
  69
  70         gpio0: gpio@e6050000 {
  71                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  72                 reg = <0 0xe6050000 0 0x50>;
  73                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
  74                 #gpio-cells = <2>;
  75                 gpio-controller;
  76                 gpio-ranges = <&pfc 0 0 32>;
  77                 #interrupt-cells = <2>;
  78                 interrupt-controller;
  79         };
  80
  81         gpio1: gpio@e6051000 {
  82                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  83                 reg = <0 0xe6051000 0 0x50>;
  84                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
  85                 #gpio-cells = <2>;
  86                 gpio-controller;
  87                 gpio-ranges = <&pfc 0 32 32>;
  88                 #interrupt-cells = <2>;
  89                 interrupt-controller;
  90         };
  91
  92         gpio2: gpio@e6052000 {
  93                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  94                 reg = <0 0xe6052000 0 0x50>;
  95                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
  96                 #gpio-cells = <2>;
  97                 gpio-controller;
  98                 gpio-ranges = <&pfc 0 64 32>;
  99                 #interrupt-cells = <2>;
 100                 interrupt-controller;
 101         };
 102
 103         gpio3: gpio@e6053000 {
 104                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 105                 reg = <0 0xe6053000 0 0x50>;
 106                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 107                 #gpio-cells = <2>;
 108                 gpio-controller;
 109                 gpio-ranges = <&pfc 0 96 32>;
 110                 #interrupt-cells = <2>;
 111                 interrupt-controller;
 112         };
 113
 114         gpio4: gpio@e6054000 {
 115                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 116                 reg = <0 0xe6054000 0 0x50>;
 117                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 118                 #gpio-cells = <2>;
 119                 gpio-controller;
 120                 gpio-ranges = <&pfc 0 128 32>;
 121                 #interrupt-cells = <2>;
 122                 interrupt-controller;
 123         };
 124
 125         gpio5: gpio@e6055000 {
 126                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 127                 reg = <0 0xe6055000 0 0x50>;
 128                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 129                 #gpio-cells = <2>;
 130                 gpio-controller;
 131                 gpio-ranges = <&pfc 0 160 32>;
 132                 #interrupt-cells = <2>;
 133                 interrupt-controller;
 134         };
 135
 136         gpio6: gpio@e6055400 {
 137                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 138                 reg = <0 0xe6055400 0 0x50>;
 139                 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 140                 #gpio-cells = <2>;
 141                 gpio-controller;
 142                 gpio-ranges = <&pfc 0 192 32>;
 143                 #interrupt-cells = <2>;
 144                 interrupt-controller;
 145         };
 146
 147         gpio7: gpio@e6055800 {
 148                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 149                 reg = <0 0xe6055800 0 0x50>;
 150                 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 151                 #gpio-cells = <2>;
 152                 gpio-controller;
 153                 gpio-ranges = <&pfc 0 224 26>;
 154                 #interrupt-cells = <2>;
 155                 interrupt-controller;
 156         };
 157
 158         thermal@e61f0000 {
 159                 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
 160                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 161                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 162                 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
 163         };
 164
 165         timer {
 166                 compatible = "arm,armv7-timer";
 167                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 168                              <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 169                              <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 170                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 171         };
 172
 173         irqc0: interrupt-controller@e61c0000 {
 174                 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
 175                 #interrupt-cells = <2>;
 176                 interrupt-controller;
 177                 reg = <0 0xe61c0000 0 0x200>;
 178                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 179                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 180                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 181                              <0 3 IRQ_TYPE_LEVEL_HIGH>,
 182                              <0 12 IRQ_TYPE_LEVEL_HIGH>,
 183                              <0 13 IRQ_TYPE_LEVEL_HIGH>,
 184                              <0 14 IRQ_TYPE_LEVEL_HIGH>,
 185                              <0 15 IRQ_TYPE_LEVEL_HIGH>,
 186                              <0 16 IRQ_TYPE_LEVEL_HIGH>,
 187                              <0 17 IRQ_TYPE_LEVEL_HIGH>;
 188         };
 189
 190         /* The memory map in the User's Manual maps the cores to bus numbers */
 191         i2c0: i2c@e6508000 {
 192                 #address-cells = <1>;
 193                 #size-cells = <0>;
 194                 compatible = "renesas,i2c-r8a7791";
 195                 reg = <0 0xe6508000 0 0x40>;
 196                 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 197                 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
 198                 status = "disabled";
 199         };
 200
 201         i2c1: i2c@e6518000 {
 202                 #address-cells = <1>;
 203                 #size-cells = <0>;
 204                 compatible = "renesas,i2c-r8a7791";
 205                 reg = <0 0xe6518000 0 0x40>;
 206                 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 207                 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
 208                 status = "disabled";
 209         };
 210
 211         i2c2: i2c@e6530000 {
 212                 #address-cells = <1>;
 213                 #size-cells = <0>;
 214                 compatible = "renesas,i2c-r8a7791";
 215                 reg = <0 0xe6530000 0 0x40>;
 216                 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 217                 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
 218                 status = "disabled";
 219         };
 220
 221         i2c3: i2c@e6540000 {
 222                 #address-cells = <1>;
 223                 #size-cells = <0>;
 224                 compatible = "renesas,i2c-r8a7791";
 225                 reg = <0 0xe6540000 0 0x40>;
 226                 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 227                 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
 228                 status = "disabled";
 229         };
 230
 231         i2c4: i2c@e6520000 {
 232                 #address-cells = <1>;
 233                 #size-cells = <0>;
 234                 compatible = "renesas,i2c-r8a7791";
 235                 reg = <0 0xe6520000 0 0x40>;
 236                 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
 237                 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
 238                 status = "disabled";
 239         };
 240
 241         i2c5: i2c@e6528000 {
 242                 /* doesn't need pinmux */
 243                 #address-cells = <1>;
 244                 #size-cells = <0>;
 245                 compatible = "renesas,i2c-r8a7791";
 246                 reg = <0 0xe6528000 0 0x40>;
 247                 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
 248                 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
 249                 status = "disabled";
 250         };
 251
 252         i2c6: i2c@e60b0000 {
 253                 /* doesn't need pinmux */
 254                 #address-cells = <1>;
 255                 #size-cells = <0>;
 256                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 257                 reg = <0 0xe60b0000 0 0x425>;
 258                 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
 259                 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
 260                 status = "disabled";
 261         };
 262
 263         i2c7: i2c@e6500000 {
 264                 #address-cells = <1>;
 265                 #size-cells = <0>;
 266                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 267                 reg = <0 0xe6500000 0 0x425>;
 268                 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
 269                 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
 270                 status = "disabled";
 271         };
 272
 273         i2c8: i2c@e6510000 {
 274                 #address-cells = <1>;
 275                 #size-cells = <0>;
 276                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 277                 reg = <0 0xe6510000 0 0x425>;
 278                 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
 279                 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
 280                 status = "disabled";
 281         };
 282
 283         pfc: pfc@e6060000 {
 284                 compatible = "renesas,pfc-r8a7791";
 285                 reg = <0 0xe6060000 0 0x250>;
 286                 #gpio-range-cells = <3>;
 287         };
 288
 289         sdhi0: sd@ee100000 {
 290                 compatible = "renesas,sdhi-r8a7791";
 291                 reg = <0 0xee100000 0 0x200>;
 292                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 293                 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
 294                 status = "disabled";
 295         };
 296
 297         sdhi1: sd@ee140000 {
 298                 compatible = "renesas,sdhi-r8a7791";
 299                 reg = <0 0xee140000 0 0x100>;
 300                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 301                 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
 302                 status = "disabled";
 303         };
 304
 305         sdhi2: sd@ee160000 {
 306                 compatible = "renesas,sdhi-r8a7791";
 307                 reg = <0 0xee160000 0 0x100>;
 308                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 309                 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
 310                 status = "disabled";
 311         };
 312
 313         scifa0: serial@e6c40000 {
 314                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 315                 reg = <0 0xe6c40000 0 64>;
 316                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 317                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
 318                 clock-names = "sci_ick";
 319                 status = "disabled";
 320         };
 321
 322         scifa1: serial@e6c50000 {
 323                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 324                 reg = <0 0xe6c50000 0 64>;
 325                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 326                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
 327                 clock-names = "sci_ick";
 328                 status = "disabled";
 329         };
 330
 331         scifa2: serial@e6c60000 {
 332                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 333                 reg = <0 0xe6c60000 0 64>;
 334                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 335                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
 336                 clock-names = "sci_ick";
 337                 status = "disabled";
 338         };
 339
 340         scifa3: serial@e6c70000 {
 341                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 342                 reg = <0 0xe6c70000 0 64>;
 343                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 344                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
 345                 clock-names = "sci_ick";
 346                 status = "disabled";
 347         };
 348
 349         scifa4: serial@e6c78000 {
 350                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 351                 reg = <0 0xe6c78000 0 64>;
 352                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 353                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
 354                 clock-names = "sci_ick";
 355                 status = "disabled";
 356         };
 357
 358         scifa5: serial@e6c80000 {
 359                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 360                 reg = <0 0xe6c80000 0 64>;
 361                 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 362                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
 363                 clock-names = "sci_ick";
 364                 status = "disabled";
 365         };
 366
 367         scifb0: serial@e6c20000 {
 368                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 369                 reg = <0 0xe6c20000 0 64>;
 370                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 371                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
 372                 clock-names = "sci_ick";
 373                 status = "disabled";
 374         };
 375
 376         scifb1: serial@e6c30000 {
 377                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 378                 reg = <0 0xe6c30000 0 64>;
 379                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 380                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
 381                 clock-names = "sci_ick";
 382                 status = "disabled";
 383         };
 384
 385         scifb2: serial@e6ce0000 {
 386                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 387                 reg = <0 0xe6ce0000 0 64>;
 388                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 389                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
 390                 clock-names = "sci_ick";
 391                 status = "disabled";
 392         };
 393
 394         scif0: serial@e6e60000 {
 395                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 396                 reg = <0 0xe6e60000 0 64>;
 397                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 398                 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
 399                 clock-names = "sci_ick";
 400                 status = "disabled";
 401         };
 402
 403         scif1: serial@e6e68000 {
 404                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 405                 reg = <0 0xe6e68000 0 64>;
 406                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 407                 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
 408                 clock-names = "sci_ick";
 409                 status = "disabled";
 410         };
 411
 412         scif2: serial@e6e58000 {
 413                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 414                 reg = <0 0xe6e58000 0 64>;
 415                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 416                 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
 417                 clock-names = "sci_ick";
 418                 status = "disabled";
 419         };
 420
 421         scif3: serial@e6ea8000 {
 422                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 423                 reg = <0 0xe6ea8000 0 64>;
 424                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 425                 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
 426                 clock-names = "sci_ick";
 427                 status = "disabled";
 428         };
 429
 430         scif4: serial@e6ee0000 {
 431                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 432                 reg = <0 0xe6ee0000 0 64>;
 433                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 434                 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
 435                 clock-names = "sci_ick";
 436                 status = "disabled";
 437         };
 438
 439         scif5: serial@e6ee8000 {
 440                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 441                 reg = <0 0xe6ee8000 0 64>;
 442                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 443                 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
 444                 clock-names = "sci_ick";
 445                 status = "disabled";
 446         };
 447
 448         hscif0: serial@e62c0000 {
 449                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 450                 reg = <0 0xe62c0000 0 96>;
 451                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 452                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
 453                 clock-names = "sci_ick";
 454                 status = "disabled";
 455         };
 456
 457         hscif1: serial@e62c8000 {
 458                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 459                 reg = <0 0xe62c8000 0 96>;
 460                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 461                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
 462                 clock-names = "sci_ick";
 463                 status = "disabled";
 464         };
 465
 466         hscif2: serial@e62d0000 {
 467                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 468                 reg = <0 0xe62d0000 0 96>;
 469                 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 470                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
 471                 clock-names = "sci_ick";
 472                 status = "disabled";
 473         };
 474
 475         ether: ethernet@ee700000 {
 476                 compatible = "renesas,ether-r8a7791";
 477                 reg = <0 0xee700000 0 0x400>;
 478                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 479                 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
 480                 phy-mode = "rmii";
 481                 #address-cells = <1>;
 482                 #size-cells = <0>;
 483                 status = "disabled";
 484         };
 485
 486         sata0: sata@ee300000 {
 487                 compatible = "renesas,sata-r8a7791";
 488                 reg = <0 0xee300000 0 0x2000>;
 489                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 490                 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
 491                 status = "disabled";
 492         };
 493
 494         sata1: sata@ee500000 {
 495                 compatible = "renesas,sata-r8a7791";
 496                 reg = <0 0xee500000 0 0x2000>;
 497                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 498                 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
 499                 status = "disabled";
 500         };
 501
 502         clocks {
 503                 #address-cells = <2>;
 504                 #size-cells = <2>;
 505                 ranges;
 506
 507                 /* External root clock */
 508                 extal_clk: extal_clk {
 509                         compatible = "fixed-clock";
 510                         #clock-cells = <0>;
 511                         /* This value must be overriden by the board. */
 512                         clock-frequency = <0>;
 513                         clock-output-names = "extal";
 514                 };
 515
 516                 /* Special CPG clocks */
 517                 cpg_clocks: cpg_clocks@e6150000 {
 518                         compatible = "renesas,r8a7791-cpg-clocks",
 519                                      "renesas,rcar-gen2-cpg-clocks";
 520                         reg = <0 0xe6150000 0 0x1000>;
 521                         clocks = <&extal_clk>;
 522                         #clock-cells = <1>;
 523                         clock-output-names = "main", "pll0", "pll1", "pll3",
 524                                              "lb", "qspi", "sdh", "sd0", "z";
 525                 };
 526
 527                 /* Variable factor clocks */
 528                 sd1_clk: sd2_clk@e6150078 {
 529                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 530                         reg = <0 0xe6150078 0 4>;
 531                         clocks = <&pll1_div2_clk>;
 532                         #clock-cells = <0>;
 533                         clock-output-names = "sd1";
 534                 };
 535                 sd2_clk: sd3_clk@e615007c {
 536                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 537                         reg = <0 0xe615007c 0 4>;
 538                         clocks = <&pll1_div2_clk>;
 539                         #clock-cells = <0>;
 540                         clock-output-names = "sd2";
 541                 };
 542                 mmc0_clk: mmc0_clk@e6150240 {
 543                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 544                         reg = <0 0xe6150240 0 4>;
 545                         clocks = <&pll1_div2_clk>;
 546                         #clock-cells = <0>;
 547                         clock-output-names = "mmc0";
 548                 };
 549                 ssp_clk: ssp_clk@e6150248 {
 550                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 551                         reg = <0 0xe6150248 0 4>;
 552                         clocks = <&pll1_div2_clk>;
 553                         #clock-cells = <0>;
 554                         clock-output-names = "ssp";
 555                 };
 556                 ssprs_clk: ssprs_clk@e615024c {
 557                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 558                         reg = <0 0xe615024c 0 4>;
 559                         clocks = <&pll1_div2_clk>;
 560                         #clock-cells = <0>;
 561                         clock-output-names = "ssprs";
 562                 };
 563
 564                 /* Fixed factor clocks */
 565                 pll1_div2_clk: pll1_div2_clk {
 566                         compatible = "fixed-factor-clock";
 567                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 568                         #clock-cells = <0>;
 569                         clock-div = <2>;
 570                         clock-mult = <1>;
 571                         clock-output-names = "pll1_div2";
 572                 };
 573                 zg_clk: zg_clk {
 574                         compatible = "fixed-factor-clock";
 575                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 576                         #clock-cells = <0>;
 577                         clock-div = <3>;
 578                         clock-mult = <1>;
 579                         clock-output-names = "zg";
 580                 };
 581                 zx_clk: zx_clk {
 582                         compatible = "fixed-factor-clock";
 583                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 584                         #clock-cells = <0>;
 585                         clock-div = <3>;
 586                         clock-mult = <1>;
 587                         clock-output-names = "zx";
 588                 };
 589                 zs_clk: zs_clk {
 590                         compatible = "fixed-factor-clock";
 591                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 592                         #clock-cells = <0>;
 593                         clock-div = <6>;
 594                         clock-mult = <1>;
 595                         clock-output-names = "zs";
 596                 };
 597                 hp_clk: hp_clk {
 598                         compatible = "fixed-factor-clock";
 599                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 600                         #clock-cells = <0>;
 601                         clock-div = <12>;
 602                         clock-mult = <1>;
 603                         clock-output-names = "hp";
 604                 };
 605                 i_clk: i_clk {
 606                         compatible = "fixed-factor-clock";
 607                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 608                         #clock-cells = <0>;
 609                         clock-div = <2>;
 610                         clock-mult = <1>;
 611                         clock-output-names = "i";
 612                 };
 613                 b_clk: b_clk {
 614                         compatible = "fixed-factor-clock";
 615                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 616                         #clock-cells = <0>;
 617                         clock-div = <12>;
 618                         clock-mult = <1>;
 619                         clock-output-names = "b";
 620                 };
 621                 p_clk: p_clk {
 622                         compatible = "fixed-factor-clock";
 623                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 624                         #clock-cells = <0>;
 625                         clock-div = <24>;
 626                         clock-mult = <1>;
 627                         clock-output-names = "p";
 628                 };
 629                 cl_clk: cl_clk {
 630                         compatible = "fixed-factor-clock";
 631                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 632                         #clock-cells = <0>;
 633                         clock-div = <48>;
 634                         clock-mult = <1>;
 635                         clock-output-names = "cl";
 636                 };
 637                 m2_clk: m2_clk {
 638                         compatible = "fixed-factor-clock";
 639                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 640                         #clock-cells = <0>;
 641                         clock-div = <8>;
 642                         clock-mult = <1>;
 643                         clock-output-names = "m2";
 644                 };
 645                 imp_clk: imp_clk {
 646                         compatible = "fixed-factor-clock";
 647                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 648                         #clock-cells = <0>;
 649                         clock-div = <4>;
 650                         clock-mult = <1>;
 651                         clock-output-names = "imp";
 652                 };
 653                 rclk_clk: rclk_clk {
 654                         compatible = "fixed-factor-clock";
 655                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 656                         #clock-cells = <0>;
 657                         clock-div = <(48 * 1024)>;
 658                         clock-mult = <1>;
 659                         clock-output-names = "rclk";
 660                 };
 661                 oscclk_clk: oscclk_clk {
 662                         compatible = "fixed-factor-clock";
 663                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 664                         #clock-cells = <0>;
 665                         clock-div = <(12 * 1024)>;
 666                         clock-mult = <1>;
 667                         clock-output-names = "oscclk";
 668                 };
 669                 zb3_clk: zb3_clk {
 670                         compatible = "fixed-factor-clock";
 671                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 672                         #clock-cells = <0>;
 673                         clock-div = <4>;
 674                         clock-mult = <1>;
 675                         clock-output-names = "zb3";
 676                 };
 677                 zb3d2_clk: zb3d2_clk {
 678                         compatible = "fixed-factor-clock";
 679                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 680                         #clock-cells = <0>;
 681                         clock-div = <8>;
 682                         clock-mult = <1>;
 683                         clock-output-names = "zb3d2";
 684                 };
 685                 ddr_clk: ddr_clk {
 686                         compatible = "fixed-factor-clock";
 687                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 688                         #clock-cells = <0>;
 689                         clock-div = <8>;
 690                         clock-mult = <1>;
 691                         clock-output-names = "ddr";
 692                 };
 693                 mp_clk: mp_clk {
 694                         compatible = "fixed-factor-clock";
 695                         clocks = <&pll1_div2_clk>;
 696                         #clock-cells = <0>;
 697                         clock-div = <15>;
 698                         clock-mult = <1>;
 699                         clock-output-names = "mp";
 700                 };
 701                 cp_clk: cp_clk {
 702                         compatible = "fixed-factor-clock";
 703                         clocks = <&extal_clk>;
 704                         #clock-cells = <0>;
 705                         clock-div = <2>;
 706                         clock-mult = <1>;
 707                         clock-output-names = "cp";
 708                 };
 709
 710                 /* Gate clocks */
 711                 mstp0_clks: mstp0_clks@e6150130 {
 712                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 713                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
 714                         clocks = <&mp_clk>;
 715                         #clock-cells = <1>;
 716                         renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
 717                         clock-output-names = "msiof0";
 718                 };
 719                 mstp1_clks: mstp1_clks@e6150134 {
 720                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 721                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 722                         clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
 723                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
 724                         #clock-cells = <1>;
 725                         renesas,clock-indices = <
 726                                 R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
 727                                 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
 728                                 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S
 729                         >;
 730                         clock-output-names =
 731                                 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
 732                                 "vsp1-du0", "vsp1-sy";
 733                 };
 734                 mstp2_clks: mstp2_clks@e6150138 {
 735                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 736                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 737                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 738                                  <&mp_clk>, <&mp_clk>, <&mp_clk>;
 739                         #clock-cells = <1>;
 740                         renesas,clock-indices = <
 741                                 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
 742                                 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
 743                                 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
 744                         >;
 745                         clock-output-names =
 746                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
 747                                 "scifb1", "msiof1", "scifb2";
 748                 };
 749                 mstp3_clks: mstp3_clks@e615013c {
 750                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 751                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 752                         clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
 753                                  <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>;
 754                         #clock-cells = <1>;
 755                         renesas,clock-indices = <
 756                                 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
 757                                 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_IIC1 R8A7791_CLK_CMT1
 758                         >;
 759                         clock-output-names =
 760                                 "tpu0", "sdhi2", "sdhi1", "sdhi0",
 761                                 "mmcif0", "i2c7", "i2c8", "cmt1";
 762                 };
 763                 mstp5_clks: mstp5_clks@e6150144 {
 764                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 765                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
 766                         clocks = <&extal_clk>, <&p_clk>;
 767                         #clock-cells = <1>;
 768                         renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
 769                         clock-output-names = "thermal", "pwm";
 770                 };
 771                 mstp7_clks: mstp7_clks@e615014c {
 772                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 773                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 774                         clocks = <&mp_clk>,  <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
 775                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 776                                  <&zx_clk>, <&zx_clk>, <&zx_clk>;
 777                         #clock-cells = <1>;
 778                         renesas,clock-indices = <
 779                                 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
 780                                 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
 781                                 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
 782                                 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
 783                                 R8A7791_CLK_LVDS0
 784                         >;
 785                         clock-output-names =
 786                                 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
 787                                 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
 788                 };
 789                 mstp8_clks: mstp8_clks@e6150990 {
 790                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 791                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 792                         clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
 793                                  <&zs_clk>;
 794                         #clock-cells = <1>;
 795                         renesas,clock-indices = <
 796                                 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
 797                                 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
 798                         >;
 799                         clock-output-names =
 800                                 "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
 801                 };
 802                 mstp9_clks: mstp9_clks@e6150994 {
 803                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 804                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 805                         clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
 806                                  <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
 807                                  <&hp_clk>, <&hp_clk>;
 808                         #clock-cells = <1>;
 809                         renesas,clock-indices = <
 810                                 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
 811                                 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
 812                                 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
 813                         >;
 814                         clock-output-names =
 815                                 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3",
 816                                 "i2c2", "i2c1", "i2c0";
 817                 };
 818                 mstp11_clks: mstp11_clks@e615099c {
 819                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 820                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
 821                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
 822                         #clock-cells = <1>;
 823                         renesas,clock-indices = <
 824                                 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
 825                         >;
 826                         clock-output-names = "scifa3", "scifa4", "scifa5";
 827                 };
 828         };
 829
 830         qspi: spi@e6b10000 {
 831                 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
 832                 reg = <0 0xe6b10000 0 0x2c>;
 833                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
 834                 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
 835                 num-cs = <1>;
 836                 #address-cells = <1>;
 837                 #size-cells = <0>;
 838                 status = "disabled";
 839         };
 840
 841         msiof0: spi@e6e20000 {
 842                 compatible = "renesas,msiof-r8a7791";
 843                 reg = <0 0xe6e20000 0 0x0064>;
 844                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
 845                 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
 846                 #address-cells = <1>;
 847                 #size-cells = <0>;
 848                 status = "disabled";
 849         };
 850
 851         msiof1: spi@e6e10000 {
 852                 compatible = "renesas,msiof-r8a7791";
 853                 reg = <0 0xe6e10000 0 0x0064>;
 854                 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
 855                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
 856                 #address-cells = <1>;
 857                 #size-cells = <0>;
 858                 status = "disabled";
 859         };
 860
 861         msiof2: spi@e6e00000 {
 862                 compatible = "renesas,msiof-r8a7791";
 863                 reg = <0 0xe6e00000 0 0x0064>;
 864                 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
 865                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
 866                 #address-cells = <1>;
 867                 #size-cells = <0>;
 868                 status = "disabled";
 869         };
 870 };