arch/arm/boot/dts/r8a7791.dtsi

   1 /*
   2  * Device Tree Source for the r8a7791 SoC
   3  *
   4  * Copyright (C) 2013 Renesas Electronics Corporation
   5  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   6  * Copyright (C) 2014 Cogent Embedded Inc.
   7  *
   8  * This file is licensed under the terms of the GNU General Public License
   9  * version 2.  This program is licensed "as is" without any warranty of any
  10  * kind, whether express or implied.
  11  */
  12
  13 #include <dt-bindings/clock/r8a7791-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16
  17 / {
  18         compatible = "renesas,r8a7791";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 i2c6 = &i2c6;
  31                 i2c7 = &i2c7;
  32                 i2c8 = &i2c8;
  33                 spi0 = &qspi;
  34                 spi1 = &msiof0;
  35                 spi2 = &msiof1;
  36                 spi3 = &msiof2;
  37         };
  38
  39         cpus {
  40                 #address-cells = <1>;
  41                 #size-cells = <0>;
  42
  43                 cpu0: cpu@0 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a15";
  46                         reg = <0>;
  47                         clock-frequency = <1500000000>;
  48                 };
  49
  50                 cpu1: cpu@1 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a15";
  53                         reg = <1>;
  54                         clock-frequency = <1500000000>;
  55                 };
  56         };
  57
  58         gic: interrupt-controller@f1001000 {
  59                 compatible = "arm,cortex-a15-gic";
  60                 #interrupt-cells = <3>;
  61                 #address-cells = <0>;
  62                 interrupt-controller;
  63                 reg = <0 0xf1001000 0 0x1000>,
  64                         <0 0xf1002000 0 0x1000>,
  65                         <0 0xf1004000 0 0x2000>,
  66                         <0 0xf1006000 0 0x2000>;
  67                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  68         };
  69
  70         gpio0: gpio@e6050000 {
  71                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  72                 reg = <0 0xe6050000 0 0x50>;
  73                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
  74                 #gpio-cells = <2>;
  75                 gpio-controller;
  76                 gpio-ranges = <&pfc 0 0 32>;
  77                 #interrupt-cells = <2>;
  78                 interrupt-controller;
  79         };
  80
  81         gpio1: gpio@e6051000 {
  82                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  83                 reg = <0 0xe6051000 0 0x50>;
  84                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
  85                 #gpio-cells = <2>;
  86                 gpio-controller;
  87                 gpio-ranges = <&pfc 0 32 32>;
  88                 #interrupt-cells = <2>;
  89                 interrupt-controller;
  90         };
  91
  92         gpio2: gpio@e6052000 {
  93                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  94                 reg = <0 0xe6052000 0 0x50>;
  95                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
  96                 #gpio-cells = <2>;
  97                 gpio-controller;
  98                 gpio-ranges = <&pfc 0 64 32>;
  99                 #interrupt-cells = <2>;
 100                 interrupt-controller;
 101         };
 102
 103         gpio3: gpio@e6053000 {
 104                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 105                 reg = <0 0xe6053000 0 0x50>;
 106                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 107                 #gpio-cells = <2>;
 108                 gpio-controller;
 109                 gpio-ranges = <&pfc 0 96 32>;
 110                 #interrupt-cells = <2>;
 111                 interrupt-controller;
 112         };
 113
 114         gpio4: gpio@e6054000 {
 115                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 116                 reg = <0 0xe6054000 0 0x50>;
 117                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 118                 #gpio-cells = <2>;
 119                 gpio-controller;
 120                 gpio-ranges = <&pfc 0 128 32>;
 121                 #interrupt-cells = <2>;
 122                 interrupt-controller;
 123         };
 124
 125         gpio5: gpio@e6055000 {
 126                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 127                 reg = <0 0xe6055000 0 0x50>;
 128                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 129                 #gpio-cells = <2>;
 130                 gpio-controller;
 131                 gpio-ranges = <&pfc 0 160 32>;
 132                 #interrupt-cells = <2>;
 133                 interrupt-controller;
 134         };
 135
 136         gpio6: gpio@e6055400 {
 137                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 138                 reg = <0 0xe6055400 0 0x50>;
 139                 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 140                 #gpio-cells = <2>;
 141                 gpio-controller;
 142                 gpio-ranges = <&pfc 0 192 32>;
 143                 #interrupt-cells = <2>;
 144                 interrupt-controller;
 145         };
 146
 147         gpio7: gpio@e6055800 {
 148                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 149                 reg = <0 0xe6055800 0 0x50>;
 150                 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 151                 #gpio-cells = <2>;
 152                 gpio-controller;
 153                 gpio-ranges = <&pfc 0 224 26>;
 154                 #interrupt-cells = <2>;
 155                 interrupt-controller;
 156         };
 157
 158         thermal@e61f0000 {
 159                 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
 160                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 161                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 162                 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
 163         };
 164
 165         timer {
 166                 compatible = "arm,armv7-timer";
 167                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 168                              <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 169                              <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 170                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 171         };
 172
 173         irqc0: interrupt-controller@e61c0000 {
 174                 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
 175                 #interrupt-cells = <2>;
 176                 interrupt-controller;
 177                 reg = <0 0xe61c0000 0 0x200>;
 178                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 179                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 180                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 181                              <0 3 IRQ_TYPE_LEVEL_HIGH>,
 182                              <0 12 IRQ_TYPE_LEVEL_HIGH>,
 183                              <0 13 IRQ_TYPE_LEVEL_HIGH>,
 184                              <0 14 IRQ_TYPE_LEVEL_HIGH>,
 185                              <0 15 IRQ_TYPE_LEVEL_HIGH>,
 186                              <0 16 IRQ_TYPE_LEVEL_HIGH>,
 187                              <0 17 IRQ_TYPE_LEVEL_HIGH>;
 188         };
 189
 190         /* The memory map in the User's Manual maps the cores to bus numbers */
 191         i2c0: i2c@e6508000 {
 192                 #address-cells = <1>;
 193                 #size-cells = <0>;
 194                 compatible = "renesas,i2c-r8a7791";
 195                 reg = <0 0xe6508000 0 0x40>;
 196                 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 197                 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
 198                 status = "disabled";
 199         };
 200
 201         i2c1: i2c@e6518000 {
 202                 #address-cells = <1>;
 203                 #size-cells = <0>;
 204                 compatible = "renesas,i2c-r8a7791";
 205                 reg = <0 0xe6518000 0 0x40>;
 206                 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 207                 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
 208                 status = "disabled";
 209         };
 210
 211         i2c2: i2c@e6530000 {
 212                 #address-cells = <1>;
 213                 #size-cells = <0>;
 214                 compatible = "renesas,i2c-r8a7791";
 215                 reg = <0 0xe6530000 0 0x40>;
 216                 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 217                 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
 218                 status = "disabled";
 219         };
 220
 221         i2c3: i2c@e6540000 {
 222                 #address-cells = <1>;
 223                 #size-cells = <0>;
 224                 compatible = "renesas,i2c-r8a7791";
 225                 reg = <0 0xe6540000 0 0x40>;
 226                 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 227                 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
 228                 status = "disabled";
 229         };
 230
 231         i2c4: i2c@e6520000 {
 232                 #address-cells = <1>;
 233                 #size-cells = <0>;
 234                 compatible = "renesas,i2c-r8a7791";
 235                 reg = <0 0xe6520000 0 0x40>;
 236                 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
 237                 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
 238                 status = "disabled";
 239         };
 240
 241         i2c5: i2c@e6528000 {
 242                 /* doesn't need pinmux */
 243                 #address-cells = <1>;
 244                 #size-cells = <0>;
 245                 compatible = "renesas,i2c-r8a7791";
 246                 reg = <0 0xe6528000 0 0x40>;
 247                 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
 248                 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
 249                 status = "disabled";
 250         };
 251
 252         i2c6: i2c@e60b0000 {
 253                 /* doesn't need pinmux */
 254                 #address-cells = <1>;
 255                 #size-cells = <0>;
 256                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 257                 reg = <0 0xe60b0000 0 0x425>;
 258                 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
 259                 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
 260                 status = "disabled";
 261         };
 262
 263         i2c7: i2c@e6500000 {
 264                 #address-cells = <1>;
 265                 #size-cells = <0>;
 266                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 267                 reg = <0 0xe6500000 0 0x425>;
 268                 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
 269                 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
 270                 status = "disabled";
 271         };
 272
 273         i2c8: i2c@e6510000 {
 274                 #address-cells = <1>;
 275                 #size-cells = <0>;
 276                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 277                 reg = <0 0xe6510000 0 0x425>;
 278                 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
 279                 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
 280                 status = "disabled";
 281         };
 282
 283         pfc: pfc@e6060000 {
 284                 compatible = "renesas,pfc-r8a7791";
 285                 reg = <0 0xe6060000 0 0x250>;
 286                 #gpio-range-cells = <3>;
 287         };
 288
 289         sdhi0: sd@ee100000 {
 290                 compatible = "renesas,sdhi-r8a7791";
 291                 reg = <0 0xee100000 0 0x200>;
 292                 interrupt-parent = <&gic>;
 293                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 294                 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
 295                 status = "disabled";
 296         };
 297
 298         sdhi1: sd@ee140000 {
 299                 compatible = "renesas,sdhi-r8a7791";
 300                 reg = <0 0xee140000 0 0x100>;
 301                 interrupt-parent = <&gic>;
 302                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 303                 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
 304                 status = "disabled";
 305         };
 306
 307         sdhi2: sd@ee160000 {
 308                 compatible = "renesas,sdhi-r8a7791";
 309                 reg = <0 0xee160000 0 0x100>;
 310                 interrupt-parent = <&gic>;
 311                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 312                 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
 313                 status = "disabled";
 314         };
 315
 316         scifa0: serial@e6c40000 {
 317                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 318                 reg = <0 0xe6c40000 0 64>;
 319                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 320                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
 321                 clock-names = "sci_ick";
 322                 status = "disabled";
 323         };
 324
 325         scifa1: serial@e6c50000 {
 326                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 327                 reg = <0 0xe6c50000 0 64>;
 328                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 329                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
 330                 clock-names = "sci_ick";
 331                 status = "disabled";
 332         };
 333
 334         scifa2: serial@e6c60000 {
 335                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 336                 reg = <0 0xe6c60000 0 64>;
 337                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 338                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
 339                 clock-names = "sci_ick";
 340                 status = "disabled";
 341         };
 342
 343         scifa3: serial@e6c70000 {
 344                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 345                 reg = <0 0xe6c70000 0 64>;
 346                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 347                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
 348                 clock-names = "sci_ick";
 349                 status = "disabled";
 350         };
 351
 352         scifa4: serial@e6c78000 {
 353                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 354                 reg = <0 0xe6c78000 0 64>;
 355                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 356                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
 357                 clock-names = "sci_ick";
 358                 status = "disabled";
 359         };
 360
 361         scifa5: serial@e6c80000 {
 362                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 363                 reg = <0 0xe6c80000 0 64>;
 364                 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 365                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
 366                 clock-names = "sci_ick";
 367                 status = "disabled";
 368         };
 369
 370         scifb0: serial@e6c20000 {
 371                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 372                 reg = <0 0xe6c20000 0 64>;
 373                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 374                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
 375                 clock-names = "sci_ick";
 376                 status = "disabled";
 377         };
 378
 379         scifb1: serial@e6c30000 {
 380                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 381                 reg = <0 0xe6c30000 0 64>;
 382                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 383                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
 384                 clock-names = "sci_ick";
 385                 status = "disabled";
 386         };
 387
 388         scifb2: serial@e6ce0000 {
 389                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 390                 reg = <0 0xe6ce0000 0 64>;
 391                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 392                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
 393                 clock-names = "sci_ick";
 394                 status = "disabled";
 395         };
 396
 397         scif0: serial@e6e60000 {
 398                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 399                 reg = <0 0xe6e60000 0 64>;
 400                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 401                 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
 402                 clock-names = "sci_ick";
 403                 status = "disabled";
 404         };
 405
 406         scif1: serial@e6e68000 {
 407                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 408                 reg = <0 0xe6e68000 0 64>;
 409                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 410                 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
 411                 clock-names = "sci_ick";
 412                 status = "disabled";
 413         };
 414
 415         scif2: serial@e6e58000 {
 416                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 417                 reg = <0 0xe6e58000 0 64>;
 418                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 419                 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
 420                 clock-names = "sci_ick";
 421                 status = "disabled";
 422         };
 423
 424         scif3: serial@e6ea8000 {
 425                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 426                 reg = <0 0xe6ea8000 0 64>;
 427                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 428                 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
 429                 clock-names = "sci_ick";
 430                 status = "disabled";
 431         };
 432
 433         scif4: serial@e6ee0000 {
 434                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 435                 reg = <0 0xe6ee0000 0 64>;
 436                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 437                 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
 438                 clock-names = "sci_ick";
 439                 status = "disabled";
 440         };
 441
 442         scif5: serial@e6ee8000 {
 443                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 444                 reg = <0 0xe6ee8000 0 64>;
 445                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 446                 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
 447                 clock-names = "sci_ick";
 448                 status = "disabled";
 449         };
 450
 451         hscif0: serial@e62c0000 {
 452                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 453                 reg = <0 0xe62c0000 0 96>;
 454                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 455                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
 456                 clock-names = "sci_ick";
 457                 status = "disabled";
 458         };
 459
 460         hscif1: serial@e62c8000 {
 461                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 462                 reg = <0 0xe62c8000 0 96>;
 463                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 464                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
 465                 clock-names = "sci_ick";
 466                 status = "disabled";
 467         };
 468
 469         hscif2: serial@e62d0000 {
 470                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 471                 reg = <0 0xe62d0000 0 96>;
 472                 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 473                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
 474                 clock-names = "sci_ick";
 475                 status = "disabled";
 476         };
 477
 478         ether: ethernet@ee700000 {
 479                 compatible = "renesas,ether-r8a7791";
 480                 reg = <0 0xee700000 0 0x400>;
 481                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 482                 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
 483                 phy-mode = "rmii";
 484                 #address-cells = <1>;
 485                 #size-cells = <0>;
 486                 status = "disabled";
 487         };
 488
 489         sata0: sata@ee300000 {
 490                 compatible = "renesas,sata-r8a7791";
 491                 reg = <0 0xee300000 0 0x2000>;
 492                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 493                 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
 494                 status = "disabled";
 495         };
 496
 497         sata1: sata@ee500000 {
 498                 compatible = "renesas,sata-r8a7791";
 499                 reg = <0 0xee500000 0 0x2000>;
 500                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 501                 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
 502                 status = "disabled";
 503         };
 504
 505         clocks {
 506                 #address-cells = <2>;
 507                 #size-cells = <2>;
 508                 ranges;
 509
 510                 /* External root clock */
 511                 extal_clk: extal_clk {
 512                         compatible = "fixed-clock";
 513                         #clock-cells = <0>;
 514                         /* This value must be overriden by the board. */
 515                         clock-frequency = <0>;
 516                         clock-output-names = "extal";
 517                 };
 518
 519                 /* Special CPG clocks */
 520                 cpg_clocks: cpg_clocks@e6150000 {
 521                         compatible = "renesas,r8a7791-cpg-clocks",
 522                                      "renesas,rcar-gen2-cpg-clocks";
 523                         reg = <0 0xe6150000 0 0x1000>;
 524                         clocks = <&extal_clk>;
 525                         #clock-cells = <1>;
 526                         clock-output-names = "main", "pll0", "pll1", "pll3",
 527                                              "lb", "qspi", "sdh", "sd0", "z";
 528                 };
 529
 530                 /* Variable factor clocks */
 531                 sd1_clk: sd2_clk@e6150078 {
 532                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 533                         reg = <0 0xe6150078 0 4>;
 534                         clocks = <&pll1_div2_clk>;
 535                         #clock-cells = <0>;
 536                         clock-output-names = "sd1";
 537                 };
 538                 sd2_clk: sd3_clk@e615007c {
 539                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 540                         reg = <0 0xe615007c 0 4>;
 541                         clocks = <&pll1_div2_clk>;
 542                         #clock-cells = <0>;
 543                         clock-output-names = "sd2";
 544                 };
 545                 mmc0_clk: mmc0_clk@e6150240 {
 546                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 547                         reg = <0 0xe6150240 0 4>;
 548                         clocks = <&pll1_div2_clk>;
 549                         #clock-cells = <0>;
 550                         clock-output-names = "mmc0";
 551                 };
 552                 ssp_clk: ssp_clk@e6150248 {
 553                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 554                         reg = <0 0xe6150248 0 4>;
 555                         clocks = <&pll1_div2_clk>;
 556                         #clock-cells = <0>;
 557                         clock-output-names = "ssp";
 558                 };
 559                 ssprs_clk: ssprs_clk@e615024c {
 560                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 561                         reg = <0 0xe615024c 0 4>;
 562                         clocks = <&pll1_div2_clk>;
 563                         #clock-cells = <0>;
 564                         clock-output-names = "ssprs";
 565                 };
 566
 567                 /* Fixed factor clocks */
 568                 pll1_div2_clk: pll1_div2_clk {
 569                         compatible = "fixed-factor-clock";
 570                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 571                         #clock-cells = <0>;
 572                         clock-div = <2>;
 573                         clock-mult = <1>;
 574                         clock-output-names = "pll1_div2";
 575                 };
 576                 zg_clk: zg_clk {
 577                         compatible = "fixed-factor-clock";
 578                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 579                         #clock-cells = <0>;
 580                         clock-div = <3>;
 581                         clock-mult = <1>;
 582                         clock-output-names = "zg";
 583                 };
 584                 zx_clk: zx_clk {
 585                         compatible = "fixed-factor-clock";
 586                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 587                         #clock-cells = <0>;
 588                         clock-div = <3>;
 589                         clock-mult = <1>;
 590                         clock-output-names = "zx";
 591                 };
 592                 zs_clk: zs_clk {
 593                         compatible = "fixed-factor-clock";
 594                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 595                         #clock-cells = <0>;
 596                         clock-div = <6>;
 597                         clock-mult = <1>;
 598                         clock-output-names = "zs";
 599                 };
 600                 hp_clk: hp_clk {
 601                         compatible = "fixed-factor-clock";
 602                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 603                         #clock-cells = <0>;
 604                         clock-div = <12>;
 605                         clock-mult = <1>;
 606                         clock-output-names = "hp";
 607                 };
 608                 i_clk: i_clk {
 609                         compatible = "fixed-factor-clock";
 610                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 611                         #clock-cells = <0>;
 612                         clock-div = <2>;
 613                         clock-mult = <1>;
 614                         clock-output-names = "i";
 615                 };
 616                 b_clk: b_clk {
 617                         compatible = "fixed-factor-clock";
 618                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 619                         #clock-cells = <0>;
 620                         clock-div = <12>;
 621                         clock-mult = <1>;
 622                         clock-output-names = "b";
 623                 };
 624                 p_clk: p_clk {
 625                         compatible = "fixed-factor-clock";
 626                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 627                         #clock-cells = <0>;
 628                         clock-div = <24>;
 629                         clock-mult = <1>;
 630                         clock-output-names = "p";
 631                 };
 632                 cl_clk: cl_clk {
 633                         compatible = "fixed-factor-clock";
 634                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 635                         #clock-cells = <0>;
 636                         clock-div = <48>;
 637                         clock-mult = <1>;
 638                         clock-output-names = "cl";
 639                 };
 640                 m2_clk: m2_clk {
 641                         compatible = "fixed-factor-clock";
 642                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 643                         #clock-cells = <0>;
 644                         clock-div = <8>;
 645                         clock-mult = <1>;
 646                         clock-output-names = "m2";
 647                 };
 648                 imp_clk: imp_clk {
 649                         compatible = "fixed-factor-clock";
 650                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 651                         #clock-cells = <0>;
 652                         clock-div = <4>;
 653                         clock-mult = <1>;
 654                         clock-output-names = "imp";
 655                 };
 656                 rclk_clk: rclk_clk {
 657                         compatible = "fixed-factor-clock";
 658                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 659                         #clock-cells = <0>;
 660                         clock-div = <(48 * 1024)>;
 661                         clock-mult = <1>;
 662                         clock-output-names = "rclk";
 663                 };
 664                 oscclk_clk: oscclk_clk {
 665                         compatible = "fixed-factor-clock";
 666                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 667                         #clock-cells = <0>;
 668                         clock-div = <(12 * 1024)>;
 669                         clock-mult = <1>;
 670                         clock-output-names = "oscclk";
 671                 };
 672                 zb3_clk: zb3_clk {
 673                         compatible = "fixed-factor-clock";
 674                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 675                         #clock-cells = <0>;
 676                         clock-div = <4>;
 677                         clock-mult = <1>;
 678                         clock-output-names = "zb3";
 679                 };
 680                 zb3d2_clk: zb3d2_clk {
 681                         compatible = "fixed-factor-clock";
 682                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 683                         #clock-cells = <0>;
 684                         clock-div = <8>;
 685                         clock-mult = <1>;
 686                         clock-output-names = "zb3d2";
 687                 };
 688                 ddr_clk: ddr_clk {
 689                         compatible = "fixed-factor-clock";
 690                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 691                         #clock-cells = <0>;
 692                         clock-div = <8>;
 693                         clock-mult = <1>;
 694                         clock-output-names = "ddr";
 695                 };
 696                 mp_clk: mp_clk {
 697                         compatible = "fixed-factor-clock";
 698                         clocks = <&pll1_div2_clk>;
 699                         #clock-cells = <0>;
 700                         clock-div = <15>;
 701                         clock-mult = <1>;
 702                         clock-output-names = "mp";
 703                 };
 704                 cp_clk: cp_clk {
 705                         compatible = "fixed-factor-clock";
 706                         clocks = <&extal_clk>;
 707                         #clock-cells = <0>;
 708                         clock-div = <2>;
 709                         clock-mult = <1>;
 710                         clock-output-names = "cp";
 711                 };
 712
 713                 /* Gate clocks */
 714                 mstp0_clks: mstp0_clks@e6150130 {
 715                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 716                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
 717                         clocks = <&mp_clk>;
 718                         #clock-cells = <1>;
 719                         renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
 720                         clock-output-names = "msiof0";
 721                 };
 722                 mstp1_clks: mstp1_clks@e6150134 {
 723                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 724                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 725                         clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
 726                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
 727                         #clock-cells = <1>;
 728                         renesas,clock-indices = <
 729                                 R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
 730                                 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
 731                                 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S
 732                         >;
 733                         clock-output-names =
 734                                 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
 735                                 "vsp1-du0", "vsp1-sy";
 736                 };
 737                 mstp2_clks: mstp2_clks@e6150138 {
 738                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 739                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 740                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 741                                  <&mp_clk>, <&mp_clk>, <&mp_clk>;
 742                         #clock-cells = <1>;
 743                         renesas,clock-indices = <
 744                                 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
 745                                 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
 746                                 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
 747                         >;
 748                         clock-output-names =
 749                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
 750                                 "scifb1", "msiof1", "scifb2";
 751                 };
 752                 mstp3_clks: mstp3_clks@e615013c {
 753                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 754                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 755                         clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
 756                                  <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>;
 757                         #clock-cells = <1>;
 758                         renesas,clock-indices = <
 759                                 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
 760                                 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_IIC1 R8A7791_CLK_CMT1
 761                         >;
 762                         clock-output-names =
 763                                 "tpu0", "sdhi2", "sdhi1", "sdhi0",
 764                                 "mmcif0", "i2c7", "i2c8", "cmt1";
 765                 };
 766                 mstp5_clks: mstp5_clks@e6150144 {
 767                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 768                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
 769                         clocks = <&extal_clk>, <&p_clk>;
 770                         #clock-cells = <1>;
 771                         renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
 772                         clock-output-names = "thermal", "pwm";
 773                 };
 774                 mstp7_clks: mstp7_clks@e615014c {
 775                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 776                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 777                         clocks = <&mp_clk>,  <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
 778                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 779                                  <&zx_clk>, <&zx_clk>, <&zx_clk>;
 780                         #clock-cells = <1>;
 781                         renesas,clock-indices = <
 782                                 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
 783                                 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
 784                                 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
 785                                 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
 786                                 R8A7791_CLK_LVDS0
 787                         >;
 788                         clock-output-names =
 789                                 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
 790                                 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
 791                 };
 792                 mstp8_clks: mstp8_clks@e6150990 {
 793                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 794                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 795                         clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
 796                                  <&zs_clk>;
 797                         #clock-cells = <1>;
 798                         renesas,clock-indices = <
 799                                 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
 800                                 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
 801                         >;
 802                         clock-output-names =
 803                                 "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
 804                 };
 805                 mstp9_clks: mstp9_clks@e6150994 {
 806                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 807                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 808                         clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
 809                                  <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
 810                                  <&hp_clk>, <&hp_clk>;
 811                         #clock-cells = <1>;
 812                         renesas,clock-indices = <
 813                                 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
 814                                 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
 815                                 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
 816                         >;
 817                         clock-output-names =
 818                                 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3",
 819                                 "i2c2", "i2c1", "i2c0";
 820                 };
 821                 mstp11_clks: mstp11_clks@e615099c {
 822                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 823                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
 824                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
 825                         #clock-cells = <1>;
 826                         renesas,clock-indices = <
 827                                 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
 828                         >;
 829                         clock-output-names = "scifa3", "scifa4", "scifa5";
 830                 };
 831         };
 832
 833         qspi: spi@e6b10000 {
 834                 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
 835                 reg = <0 0xe6b10000 0 0x2c>;
 836                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
 837                 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
 838                 num-cs = <1>;
 839                 #address-cells = <1>;
 840                 #size-cells = <0>;
 841                 status = "disabled";
 842         };
 843
 844         msiof0: spi@e6e20000 {
 845                 compatible = "renesas,msiof-r8a7791";
 846                 reg = <0 0xe6e20000 0 0x0064>;
 847                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
 848                 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
 849                 #address-cells = <1>;
 850                 #size-cells = <0>;
 851                 status = "disabled";
 852         };
 853
 854         msiof1: spi@e6e10000 {
 855                 compatible = "renesas,msiof-r8a7791";
 856                 reg = <0 0xe6e10000 0 0x0064>;
 857                 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
 858                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
 859                 #address-cells = <1>;
 860                 #size-cells = <0>;
 861                 status = "disabled";
 862         };
 863
 864         msiof2: spi@e6e00000 {
 865                 compatible = "renesas,msiof-r8a7791";
 866                 reg = <0 0xe6e00000 0 0x0064>;
 867                 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
 868                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
 869                 #address-cells = <1>;
 870                 #size-cells = <0>;
 871                 status = "disabled";
 872         };
 873 };