arch/arm/boot/dts/r8a7791.dtsi

   1 /*
   2  * Device Tree Source for the r8a7791 SoC
   3  *
   4  * Copyright (C) 2013 Renesas Electronics Corporation
   5  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   6  * Copyright (C) 2014 Cogent Embedded Inc.
   7  *
   8  * This file is licensed under the terms of the GNU General Public License
   9  * version 2.  This program is licensed "as is" without any warranty of any
  10  * kind, whether express or implied.
  11  */
  12
  13 #include <dt-bindings/clock/r8a7791-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16
  17 / {
  18         compatible = "renesas,r8a7791";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 spi0 = &qspi;
  31         };
  32
  33         cpus {
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36
  37                 cpu0: cpu@0 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a15";
  40                         reg = <0>;
  41                         clock-frequency = <1500000000>;
  42                 };
  43
  44                 cpu1: cpu@1 {
  45                         device_type = "cpu";
  46                         compatible = "arm,cortex-a15";
  47                         reg = <1>;
  48                         clock-frequency = <1500000000>;
  49                 };
  50         };
  51
  52         gic: interrupt-controller@f1001000 {
  53                 compatible = "arm,cortex-a15-gic";
  54                 #interrupt-cells = <3>;
  55                 #address-cells = <0>;
  56                 interrupt-controller;
  57                 reg = <0 0xf1001000 0 0x1000>,
  58                         <0 0xf1002000 0 0x1000>,
  59                         <0 0xf1004000 0 0x2000>,
  60                         <0 0xf1006000 0 0x2000>;
  61                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  62         };
  63
  64         gpio0: gpio@e6050000 {
  65                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  66                 reg = <0 0xe6050000 0 0x50>;
  67                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
  68                 #gpio-cells = <2>;
  69                 gpio-controller;
  70                 gpio-ranges = <&pfc 0 0 32>;
  71                 #interrupt-cells = <2>;
  72                 interrupt-controller;
  73         };
  74
  75         gpio1: gpio@e6051000 {
  76                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  77                 reg = <0 0xe6051000 0 0x50>;
  78                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
  79                 #gpio-cells = <2>;
  80                 gpio-controller;
  81                 gpio-ranges = <&pfc 0 32 32>;
  82                 #interrupt-cells = <2>;
  83                 interrupt-controller;
  84         };
  85
  86         gpio2: gpio@e6052000 {
  87                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  88                 reg = <0 0xe6052000 0 0x50>;
  89                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
  90                 #gpio-cells = <2>;
  91                 gpio-controller;
  92                 gpio-ranges = <&pfc 0 64 32>;
  93                 #interrupt-cells = <2>;
  94                 interrupt-controller;
  95         };
  96
  97         gpio3: gpio@e6053000 {
  98                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  99                 reg = <0 0xe6053000 0 0x50>;
 100                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 101                 #gpio-cells = <2>;
 102                 gpio-controller;
 103                 gpio-ranges = <&pfc 0 96 32>;
 104                 #interrupt-cells = <2>;
 105                 interrupt-controller;
 106         };
 107
 108         gpio4: gpio@e6054000 {
 109                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 110                 reg = <0 0xe6054000 0 0x50>;
 111                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 112                 #gpio-cells = <2>;
 113                 gpio-controller;
 114                 gpio-ranges = <&pfc 0 128 32>;
 115                 #interrupt-cells = <2>;
 116                 interrupt-controller;
 117         };
 118
 119         gpio5: gpio@e6055000 {
 120                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 121                 reg = <0 0xe6055000 0 0x50>;
 122                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 123                 #gpio-cells = <2>;
 124                 gpio-controller;
 125                 gpio-ranges = <&pfc 0 160 32>;
 126                 #interrupt-cells = <2>;
 127                 interrupt-controller;
 128         };
 129
 130         gpio6: gpio@e6055400 {
 131                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 132                 reg = <0 0xe6055400 0 0x50>;
 133                 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 134                 #gpio-cells = <2>;
 135                 gpio-controller;
 136                 gpio-ranges = <&pfc 0 192 32>;
 137                 #interrupt-cells = <2>;
 138                 interrupt-controller;
 139         };
 140
 141         gpio7: gpio@e6055800 {
 142                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 143                 reg = <0 0xe6055800 0 0x50>;
 144                 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 145                 #gpio-cells = <2>;
 146                 gpio-controller;
 147                 gpio-ranges = <&pfc 0 224 26>;
 148                 #interrupt-cells = <2>;
 149                 interrupt-controller;
 150         };
 151
 152         thermal@e61f0000 {
 153                 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
 154                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 155                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 156                 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
 157         };
 158
 159         timer {
 160                 compatible = "arm,armv7-timer";
 161                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 162                              <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 163                              <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 164                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 165         };
 166
 167         irqc0: interrupt-controller@e61c0000 {
 168                 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
 169                 #interrupt-cells = <2>;
 170                 interrupt-controller;
 171                 reg = <0 0xe61c0000 0 0x200>;
 172                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 173                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 174                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 175                              <0 3 IRQ_TYPE_LEVEL_HIGH>,
 176                              <0 12 IRQ_TYPE_LEVEL_HIGH>,
 177                              <0 13 IRQ_TYPE_LEVEL_HIGH>,
 178                              <0 14 IRQ_TYPE_LEVEL_HIGH>,
 179                              <0 15 IRQ_TYPE_LEVEL_HIGH>,
 180                              <0 16 IRQ_TYPE_LEVEL_HIGH>,
 181                              <0 17 IRQ_TYPE_LEVEL_HIGH>;
 182         };
 183
 184         i2c0: i2c@e6508000 {
 185                 #address-cells = <1>;
 186                 #size-cells = <0>;
 187                 compatible = "renesas,i2c-r8a7791";
 188                 reg = <0 0xe6508000 0 0x40>;
 189                 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 190                 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
 191                 status = "disabled";
 192         };
 193
 194         i2c1: i2c@e6518000 {
 195                 #address-cells = <1>;
 196                 #size-cells = <0>;
 197                 compatible = "renesas,i2c-r8a7791";
 198                 reg = <0 0xe6518000 0 0x40>;
 199                 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 200                 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
 201                 status = "disabled";
 202         };
 203
 204         i2c2: i2c@e6530000 {
 205                 #address-cells = <1>;
 206                 #size-cells = <0>;
 207                 compatible = "renesas,i2c-r8a7791";
 208                 reg = <0 0xe6530000 0 0x40>;
 209                 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 210                 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
 211                 status = "disabled";
 212         };
 213
 214         i2c3: i2c@e6540000 {
 215                 #address-cells = <1>;
 216                 #size-cells = <0>;
 217                 compatible = "renesas,i2c-r8a7791";
 218                 reg = <0 0xe6540000 0 0x40>;
 219                 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 220                 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
 221                 status = "disabled";
 222         };
 223
 224         i2c4: i2c@e6520000 {
 225                 #address-cells = <1>;
 226                 #size-cells = <0>;
 227                 compatible = "renesas,i2c-r8a7791";
 228                 reg = <0 0xe6520000 0 0x40>;
 229                 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
 230                 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
 231                 status = "disabled";
 232         };
 233
 234         i2c5: i2c@e6528000 {
 235                 #address-cells = <1>;
 236                 #size-cells = <0>;
 237                 compatible = "renesas,i2c-r8a7791";
 238                 reg = <0 0xe6528000 0 0x40>;
 239                 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
 240                 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
 241                 status = "disabled";
 242         };
 243
 244         pfc: pfc@e6060000 {
 245                 compatible = "renesas,pfc-r8a7791";
 246                 reg = <0 0xe6060000 0 0x250>;
 247                 #gpio-range-cells = <3>;
 248         };
 249
 250         sdhi0: sd@ee100000 {
 251                 compatible = "renesas,sdhi-r8a7791";
 252                 reg = <0 0xee100000 0 0x200>;
 253                 interrupt-parent = <&gic>;
 254                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 255                 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
 256                 status = "disabled";
 257         };
 258
 259         sdhi1: sd@ee140000 {
 260                 compatible = "renesas,sdhi-r8a7791";
 261                 reg = <0 0xee140000 0 0x100>;
 262                 interrupt-parent = <&gic>;
 263                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 264                 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
 265                 status = "disabled";
 266         };
 267
 268         sdhi2: sd@ee160000 {
 269                 compatible = "renesas,sdhi-r8a7791";
 270                 reg = <0 0xee160000 0 0x100>;
 271                 interrupt-parent = <&gic>;
 272                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 273                 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
 274                 status = "disabled";
 275         };
 276
 277         scifa0: serial@e6c40000 {
 278                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 279                 reg = <0 0xe6c40000 0 64>;
 280                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 281                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
 282                 clock-names = "sci_ick";
 283                 status = "disabled";
 284         };
 285
 286         scifa1: serial@e6c50000 {
 287                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 288                 reg = <0 0xe6c50000 0 64>;
 289                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 290                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
 291                 clock-names = "sci_ick";
 292                 status = "disabled";
 293         };
 294
 295         scifa2: serial@e6c60000 {
 296                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 297                 reg = <0 0xe6c60000 0 64>;
 298                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 299                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
 300                 clock-names = "sci_ick";
 301                 status = "disabled";
 302         };
 303
 304         scifa3: serial@e6c70000 {
 305                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 306                 reg = <0 0xe6c70000 0 64>;
 307                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 308                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
 309                 clock-names = "sci_ick";
 310                 status = "disabled";
 311         };
 312
 313         scifa4: serial@e6c78000 {
 314                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 315                 reg = <0 0xe6c78000 0 64>;
 316                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 317                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
 318                 clock-names = "sci_ick";
 319                 status = "disabled";
 320         };
 321
 322         scifa5: serial@e6c80000 {
 323                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 324                 reg = <0 0xe6c80000 0 64>;
 325                 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 326                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
 327                 clock-names = "sci_ick";
 328                 status = "disabled";
 329         };
 330
 331         scifb0: serial@e6c20000 {
 332                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 333                 reg = <0 0xe6c20000 0 64>;
 334                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 335                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
 336                 clock-names = "sci_ick";
 337                 status = "disabled";
 338         };
 339
 340         scifb1: serial@e6c30000 {
 341                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 342                 reg = <0 0xe6c30000 0 64>;
 343                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 344                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
 345                 clock-names = "sci_ick";
 346                 status = "disabled";
 347         };
 348
 349         scifb2: serial@e6ce0000 {
 350                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 351                 reg = <0 0xe6ce0000 0 64>;
 352                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 353                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
 354                 clock-names = "sci_ick";
 355                 status = "disabled";
 356         };
 357
 358         scif0: serial@e6e60000 {
 359                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 360                 reg = <0 0xe6e60000 0 64>;
 361                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 362                 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
 363                 clock-names = "sci_ick";
 364                 status = "disabled";
 365         };
 366
 367         scif1: serial@e6e68000 {
 368                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 369                 reg = <0 0xe6e68000 0 64>;
 370                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 371                 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
 372                 clock-names = "sci_ick";
 373                 status = "disabled";
 374         };
 375
 376         scif2: serial@e6e58000 {
 377                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 378                 reg = <0 0xe6e58000 0 64>;
 379                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 380                 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
 381                 clock-names = "sci_ick";
 382                 status = "disabled";
 383         };
 384
 385         scif3: serial@e6ea8000 {
 386                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 387                 reg = <0 0xe6ea8000 0 64>;
 388                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 389                 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
 390                 clock-names = "sci_ick";
 391                 status = "disabled";
 392         };
 393
 394         scif4: serial@e6ee0000 {
 395                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 396                 reg = <0 0xe6ee0000 0 64>;
 397                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 398                 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
 399                 clock-names = "sci_ick";
 400                 status = "disabled";
 401         };
 402
 403         scif5: serial@e6ee8000 {
 404                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 405                 reg = <0 0xe6ee8000 0 64>;
 406                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 407                 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
 408                 clock-names = "sci_ick";
 409                 status = "disabled";
 410         };
 411
 412         hscif0: serial@e62c0000 {
 413                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 414                 reg = <0 0xe62c0000 0 96>;
 415                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 416                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
 417                 clock-names = "sci_ick";
 418                 status = "disabled";
 419         };
 420
 421         hscif1: serial@e62c8000 {
 422                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 423                 reg = <0 0xe62c8000 0 96>;
 424                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 425                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
 426                 clock-names = "sci_ick";
 427                 status = "disabled";
 428         };
 429
 430         hscif2: serial@e62d0000 {
 431                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 432                 reg = <0 0xe62d0000 0 96>;
 433                 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 434                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
 435                 clock-names = "sci_ick";
 436                 status = "disabled";
 437         };
 438
 439         ether: ethernet@ee700000 {
 440                 compatible = "renesas,ether-r8a7791";
 441                 reg = <0 0xee700000 0 0x400>;
 442                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 443                 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
 444                 phy-mode = "rmii";
 445                 #address-cells = <1>;
 446                 #size-cells = <0>;
 447                 status = "disabled";
 448         };
 449
 450         sata0: sata@ee300000 {
 451                 compatible = "renesas,sata-r8a7791";
 452                 reg = <0 0xee300000 0 0x2000>;
 453                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 454                 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
 455                 status = "disabled";
 456         };
 457
 458         sata1: sata@ee500000 {
 459                 compatible = "renesas,sata-r8a7791";
 460                 reg = <0 0xee500000 0 0x2000>;
 461                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 462                 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
 463                 status = "disabled";
 464         };
 465
 466         clocks {
 467                 #address-cells = <2>;
 468                 #size-cells = <2>;
 469                 ranges;
 470
 471                 /* External root clock */
 472                 extal_clk: extal_clk {
 473                         compatible = "fixed-clock";
 474                         #clock-cells = <0>;
 475                         /* This value must be overriden by the board. */
 476                         clock-frequency = <0>;
 477                         clock-output-names = "extal";
 478                 };
 479
 480                 /* Special CPG clocks */
 481                 cpg_clocks: cpg_clocks@e6150000 {
 482                         compatible = "renesas,r8a7791-cpg-clocks",
 483                                      "renesas,rcar-gen2-cpg-clocks";
 484                         reg = <0 0xe6150000 0 0x1000>;
 485                         clocks = <&extal_clk>;
 486                         #clock-cells = <1>;
 487                         clock-output-names = "main", "pll0", "pll1", "pll3",
 488                                              "lb", "qspi", "sdh", "sd0", "z";
 489                 };
 490
 491                 /* Variable factor clocks */
 492                 sd1_clk: sd2_clk@e6150078 {
 493                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 494                         reg = <0 0xe6150078 0 4>;
 495                         clocks = <&pll1_div2_clk>;
 496                         #clock-cells = <0>;
 497                         clock-output-names = "sd1";
 498                 };
 499                 sd2_clk: sd3_clk@e615007c {
 500                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 501                         reg = <0 0xe615007c 0 4>;
 502                         clocks = <&pll1_div2_clk>;
 503                         #clock-cells = <0>;
 504                         clock-output-names = "sd2";
 505                 };
 506                 mmc0_clk: mmc0_clk@e6150240 {
 507                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 508                         reg = <0 0xe6150240 0 4>;
 509                         clocks = <&pll1_div2_clk>;
 510                         #clock-cells = <0>;
 511                         clock-output-names = "mmc0";
 512                 };
 513                 ssp_clk: ssp_clk@e6150248 {
 514                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 515                         reg = <0 0xe6150248 0 4>;
 516                         clocks = <&pll1_div2_clk>;
 517                         #clock-cells = <0>;
 518                         clock-output-names = "ssp";
 519                 };
 520                 ssprs_clk: ssprs_clk@e615024c {
 521                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 522                         reg = <0 0xe615024c 0 4>;
 523                         clocks = <&pll1_div2_clk>;
 524                         #clock-cells = <0>;
 525                         clock-output-names = "ssprs";
 526                 };
 527
 528                 /* Fixed factor clocks */
 529                 pll1_div2_clk: pll1_div2_clk {
 530                         compatible = "fixed-factor-clock";
 531                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 532                         #clock-cells = <0>;
 533                         clock-div = <2>;
 534                         clock-mult = <1>;
 535                         clock-output-names = "pll1_div2";
 536                 };
 537                 zg_clk: zg_clk {
 538                         compatible = "fixed-factor-clock";
 539                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 540                         #clock-cells = <0>;
 541                         clock-div = <3>;
 542                         clock-mult = <1>;
 543                         clock-output-names = "zg";
 544                 };
 545                 zx_clk: zx_clk {
 546                         compatible = "fixed-factor-clock";
 547                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 548                         #clock-cells = <0>;
 549                         clock-div = <3>;
 550                         clock-mult = <1>;
 551                         clock-output-names = "zx";
 552                 };
 553                 zs_clk: zs_clk {
 554                         compatible = "fixed-factor-clock";
 555                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 556                         #clock-cells = <0>;
 557                         clock-div = <6>;
 558                         clock-mult = <1>;
 559                         clock-output-names = "zs";
 560                 };
 561                 hp_clk: hp_clk {
 562                         compatible = "fixed-factor-clock";
 563                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 564                         #clock-cells = <0>;
 565                         clock-div = <12>;
 566                         clock-mult = <1>;
 567                         clock-output-names = "hp";
 568                 };
 569                 i_clk: i_clk {
 570                         compatible = "fixed-factor-clock";
 571                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 572                         #clock-cells = <0>;
 573                         clock-div = <2>;
 574                         clock-mult = <1>;
 575                         clock-output-names = "i";
 576                 };
 577                 b_clk: b_clk {
 578                         compatible = "fixed-factor-clock";
 579                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 580                         #clock-cells = <0>;
 581                         clock-div = <12>;
 582                         clock-mult = <1>;
 583                         clock-output-names = "b";
 584                 };
 585                 p_clk: p_clk {
 586                         compatible = "fixed-factor-clock";
 587                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 588                         #clock-cells = <0>;
 589                         clock-div = <24>;
 590                         clock-mult = <1>;
 591                         clock-output-names = "p";
 592                 };
 593                 cl_clk: cl_clk {
 594                         compatible = "fixed-factor-clock";
 595                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 596                         #clock-cells = <0>;
 597                         clock-div = <48>;
 598                         clock-mult = <1>;
 599                         clock-output-names = "cl";
 600                 };
 601                 m2_clk: m2_clk {
 602                         compatible = "fixed-factor-clock";
 603                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 604                         #clock-cells = <0>;
 605                         clock-div = <8>;
 606                         clock-mult = <1>;
 607                         clock-output-names = "m2";
 608                 };
 609                 imp_clk: imp_clk {
 610                         compatible = "fixed-factor-clock";
 611                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 612                         #clock-cells = <0>;
 613                         clock-div = <4>;
 614                         clock-mult = <1>;
 615                         clock-output-names = "imp";
 616                 };
 617                 rclk_clk: rclk_clk {
 618                         compatible = "fixed-factor-clock";
 619                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 620                         #clock-cells = <0>;
 621                         clock-div = <(48 * 1024)>;
 622                         clock-mult = <1>;
 623                         clock-output-names = "rclk";
 624                 };
 625                 oscclk_clk: oscclk_clk {
 626                         compatible = "fixed-factor-clock";
 627                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 628                         #clock-cells = <0>;
 629                         clock-div = <(12 * 1024)>;
 630                         clock-mult = <1>;
 631                         clock-output-names = "oscclk";
 632                 };
 633                 zb3_clk: zb3_clk {
 634                         compatible = "fixed-factor-clock";
 635                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 636                         #clock-cells = <0>;
 637                         clock-div = <4>;
 638                         clock-mult = <1>;
 639                         clock-output-names = "zb3";
 640                 };
 641                 zb3d2_clk: zb3d2_clk {
 642                         compatible = "fixed-factor-clock";
 643                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 644                         #clock-cells = <0>;
 645                         clock-div = <8>;
 646                         clock-mult = <1>;
 647                         clock-output-names = "zb3d2";
 648                 };
 649                 ddr_clk: ddr_clk {
 650                         compatible = "fixed-factor-clock";
 651                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 652                         #clock-cells = <0>;
 653                         clock-div = <8>;
 654                         clock-mult = <1>;
 655                         clock-output-names = "ddr";
 656                 };
 657                 mp_clk: mp_clk {
 658                         compatible = "fixed-factor-clock";
 659                         clocks = <&pll1_div2_clk>;
 660                         #clock-cells = <0>;
 661                         clock-div = <15>;
 662                         clock-mult = <1>;
 663                         clock-output-names = "mp";
 664                 };
 665                 cp_clk: cp_clk {
 666                         compatible = "fixed-factor-clock";
 667                         clocks = <&extal_clk>;
 668                         #clock-cells = <0>;
 669                         clock-div = <2>;
 670                         clock-mult = <1>;
 671                         clock-output-names = "cp";
 672                 };
 673
 674                 /* Gate clocks */
 675                 mstp0_clks: mstp0_clks@e6150130 {
 676                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 677                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
 678                         clocks = <&mp_clk>;
 679                         #clock-cells = <1>;
 680                         renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
 681                         clock-output-names = "msiof0";
 682                 };
 683                 mstp1_clks: mstp1_clks@e6150134 {
 684                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 685                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 686                         clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
 687                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
 688                         #clock-cells = <1>;
 689                         renesas,clock-indices = <
 690                                 R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
 691                                 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
 692                                 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S
 693                         >;
 694                         clock-output-names =
 695                                 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
 696                                 "vsp1-du0", "vsp1-sy";
 697                 };
 698                 mstp2_clks: mstp2_clks@e6150138 {
 699                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 700                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 701                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 702                                  <&mp_clk>, <&mp_clk>, <&mp_clk>;
 703                         #clock-cells = <1>;
 704                         renesas,clock-indices = <
 705                                 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
 706                                 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
 707                                 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
 708                         >;
 709                         clock-output-names =
 710                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
 711                                 "scifb1", "msiof1", "scifb2";
 712                 };
 713                 mstp3_clks: mstp3_clks@e615013c {
 714                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 715                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 716                         clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>,
 717                                 <&cpg_clocks R8A7791_CLK_SD0>, <&mmc0_clk>, <&rclk_clk>;
 718                         #clock-cells = <1>;
 719                         renesas,clock-indices = <
 720                                 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1
 721                                 R8A7791_CLK_SDHI0 R8A7791_CLK_MMCIF0 R8A7791_CLK_CMT1
 722                         >;
 723                         clock-output-names =
 724                                 "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", "cmt1";
 725                 };
 726                 mstp5_clks: mstp5_clks@e6150144 {
 727                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 728                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
 729                         clocks = <&extal_clk>, <&p_clk>;
 730                         #clock-cells = <1>;
 731                         renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
 732                         clock-output-names = "thermal", "pwm";
 733                 };
 734                 mstp7_clks: mstp7_clks@e615014c {
 735                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 736                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 737                         clocks = <&mp_clk>,  <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
 738                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 739                                  <&zx_clk>, <&zx_clk>, <&zx_clk>;
 740                         #clock-cells = <1>;
 741                         renesas,clock-indices = <
 742                                 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
 743                                 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
 744                                 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
 745                                 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
 746                                 R8A7791_CLK_LVDS0
 747                         >;
 748                         clock-output-names =
 749                                 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
 750                                 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
 751                 };
 752                 mstp8_clks: mstp8_clks@e6150990 {
 753                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 754                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 755                         clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
 756                                  <&zs_clk>;
 757                         #clock-cells = <1>;
 758                         renesas,clock-indices = <
 759                                 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
 760                                 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
 761                         >;
 762                         clock-output-names =
 763                                 "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
 764                 };
 765                 mstp9_clks: mstp9_clks@e6150994 {
 766                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 767                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 768                         clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>,
 769                                  <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 770                                  <&p_clk>;
 771                         #clock-cells = <1>;
 772                         renesas,clock-indices = <
 773                                 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD
 774                                 R8A7791_CLK_I2C5 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3
 775                                 R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
 776                         >;
 777                         clock-output-names =
 778                                 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3",
 779                                 "i2c2", "i2c1", "i2c0";
 780                 };
 781                 mstp11_clks: mstp11_clks@e615099c {
 782                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 783                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
 784                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
 785                         #clock-cells = <1>;
 786                         renesas,clock-indices = <
 787                                 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
 788                         >;
 789                         clock-output-names = "scifa3", "scifa4", "scifa5";
 790                 };
 791         };
 792
 793         qspi: spi@e6b10000 {
 794                 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
 795                 reg = <0 0xe6b10000 0 0x2c>;
 796                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
 797                 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
 798                 num-cs = <1>;
 799                 #address-cells = <1>;
 800                 #size-cells = <0>;
 801                 status = "disabled";
 802         };
 803 };