2 * Device Tree Source for the r8a7791 SoC
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Renesas Solutions Corp.
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 #include <dt-bindings/clock/r8a7791-clock.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
17 compatible = "renesas,r8a7791";
18 interrupt-parent = <&gic>;
28 compatible = "arm,cortex-a15";
30 clock-frequency = <1300000000>;
35 compatible = "arm,cortex-a15";
37 clock-frequency = <1300000000>;
41 gic: interrupt-controller@f1001000 {
42 compatible = "arm,cortex-a15-gic";
43 #interrupt-cells = <3>;
46 reg = <0 0xf1001000 0 0x1000>,
47 <0 0xf1002000 0 0x1000>,
48 <0 0xf1004000 0 0x2000>,
49 <0 0xf1006000 0 0x2000>;
50 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
53 gpio0: gpio@e6050000 {
54 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
55 reg = <0 0xe6050000 0 0x50>;
56 interrupt-parent = <&gic>;
57 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
60 gpio-ranges = <&pfc 0 0 32>;
61 #interrupt-cells = <2>;
65 gpio1: gpio@e6051000 {
66 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
67 reg = <0 0xe6051000 0 0x50>;
68 interrupt-parent = <&gic>;
69 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
72 gpio-ranges = <&pfc 0 32 32>;
73 #interrupt-cells = <2>;
77 gpio2: gpio@e6052000 {
78 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
79 reg = <0 0xe6052000 0 0x50>;
80 interrupt-parent = <&gic>;
81 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
84 gpio-ranges = <&pfc 0 64 32>;
85 #interrupt-cells = <2>;
89 gpio3: gpio@e6053000 {
90 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
91 reg = <0 0xe6053000 0 0x50>;
92 interrupt-parent = <&gic>;
93 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
96 gpio-ranges = <&pfc 0 96 32>;
97 #interrupt-cells = <2>;
101 gpio4: gpio@e6054000 {
102 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
103 reg = <0 0xe6054000 0 0x50>;
104 interrupt-parent = <&gic>;
105 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
108 gpio-ranges = <&pfc 0 128 32>;
109 #interrupt-cells = <2>;
110 interrupt-controller;
113 gpio5: gpio@e6055000 {
114 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
115 reg = <0 0xe6055000 0 0x50>;
116 interrupt-parent = <&gic>;
117 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
120 gpio-ranges = <&pfc 0 160 32>;
121 #interrupt-cells = <2>;
122 interrupt-controller;
125 gpio6: gpio@e6055400 {
126 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
127 reg = <0 0xe6055400 0 0x50>;
128 interrupt-parent = <&gic>;
129 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
132 gpio-ranges = <&pfc 0 192 32>;
133 #interrupt-cells = <2>;
134 interrupt-controller;
137 gpio7: gpio@e6055800 {
138 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
139 reg = <0 0xe6055800 0 0x50>;
140 interrupt-parent = <&gic>;
141 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
144 gpio-ranges = <&pfc 0 224 26>;
145 #interrupt-cells = <2>;
146 interrupt-controller;
150 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
151 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
152 interrupt-parent = <&gic>;
153 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
157 compatible = "arm,armv7-timer";
158 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
159 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
160 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
161 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
164 irqc0: interrupt-controller@e61c0000 {
165 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
166 #interrupt-cells = <2>;
167 interrupt-controller;
168 reg = <0 0xe61c0000 0 0x200>;
169 interrupt-parent = <&gic>;
170 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
171 <0 1 IRQ_TYPE_LEVEL_HIGH>,
172 <0 2 IRQ_TYPE_LEVEL_HIGH>,
173 <0 3 IRQ_TYPE_LEVEL_HIGH>,
174 <0 12 IRQ_TYPE_LEVEL_HIGH>,
175 <0 13 IRQ_TYPE_LEVEL_HIGH>,
176 <0 14 IRQ_TYPE_LEVEL_HIGH>,
177 <0 15 IRQ_TYPE_LEVEL_HIGH>,
178 <0 16 IRQ_TYPE_LEVEL_HIGH>,
179 <0 17 IRQ_TYPE_LEVEL_HIGH>;
183 compatible = "renesas,pfc-r8a7791";
184 reg = <0 0xe6060000 0 0x250>;
185 #gpio-range-cells = <3>;
189 #address-cells = <2>;
193 /* External root clock */
194 extal_clk: extal_clk {
195 compatible = "fixed-clock";
197 /* This value must be overriden by the board. */
198 clock-frequency = <0>;
199 clock-output-names = "extal";
202 /* Special CPG clocks */
203 cpg_clocks: cpg_clocks@e6150000 {
204 compatible = "renesas,r8a7791-cpg-clocks",
205 "renesas,rcar-gen2-cpg-clocks";
206 reg = <0 0xe6150000 0 0x1000>;
207 clocks = <&extal_clk>;
209 clock-output-names = "main", "pll0", "pll1", "pll3",
210 "lb", "qspi", "sdh", "sd0", "z";
213 /* Variable factor clocks */
214 sd1_clk: sd2_clk@e6150078 {
215 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
216 reg = <0 0xe6150078 0 4>;
217 clocks = <&pll1_div2_clk>;
219 clock-output-names = "sd1";
221 sd2_clk: sd3_clk@e615007c {
222 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
223 reg = <0 0xe615007c 0 4>;
224 clocks = <&pll1_div2_clk>;
226 clock-output-names = "sd2";
228 mmc0_clk: mmc0_clk@e6150240 {
229 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
230 reg = <0 0xe6150240 0 4>;
231 clocks = <&pll1_div2_clk>;
233 clock-output-names = "mmc0";
235 ssp_clk: ssp_clk@e6150248 {
236 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
237 reg = <0 0xe6150248 0 4>;
238 clocks = <&pll1_div2_clk>;
240 clock-output-names = "ssp";
242 ssprs_clk: ssprs_clk@e615024c {
243 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
244 reg = <0 0xe615024c 0 4>;
245 clocks = <&pll1_div2_clk>;
247 clock-output-names = "ssprs";
250 /* Fixed factor clocks */
251 pll1_div2_clk: pll1_div2_clk {
252 compatible = "fixed-factor-clock";
253 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
257 clock-output-names = "pll1_div2";
260 compatible = "fixed-factor-clock";
261 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
265 clock-output-names = "zg";
268 compatible = "fixed-factor-clock";
269 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
273 clock-output-names = "zx";
276 compatible = "fixed-factor-clock";
277 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
281 clock-output-names = "zs";
284 compatible = "fixed-factor-clock";
285 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
289 clock-output-names = "hp";
292 compatible = "fixed-factor-clock";
293 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
297 clock-output-names = "i";
300 compatible = "fixed-factor-clock";
301 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
305 clock-output-names = "b";
308 compatible = "fixed-factor-clock";
309 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
313 clock-output-names = "p";
316 compatible = "fixed-factor-clock";
317 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
321 clock-output-names = "cl";
324 compatible = "fixed-factor-clock";
325 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
329 clock-output-names = "m2";
332 compatible = "fixed-factor-clock";
333 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
337 clock-output-names = "imp";
340 compatible = "fixed-factor-clock";
341 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
343 clock-div = <(48 * 1024)>;
345 clock-output-names = "rclk";
347 oscclk_clk: oscclk_clk {
348 compatible = "fixed-factor-clock";
349 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
351 clock-div = <(12 * 1024)>;
353 clock-output-names = "oscclk";
356 compatible = "fixed-factor-clock";
357 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
361 clock-output-names = "zb3";
363 zb3d2_clk: zb3d2_clk {
364 compatible = "fixed-factor-clock";
365 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
369 clock-output-names = "zb3d2";
372 compatible = "fixed-factor-clock";
373 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
377 clock-output-names = "ddr";
380 compatible = "fixed-factor-clock";
381 clocks = <&pll1_div2_clk>;
385 clock-output-names = "mp";
388 compatible = "fixed-factor-clock";
389 clocks = <&extal_clk>;
393 clock-output-names = "cp";
397 mstp0_clks: mstp0_clks@e6150130 {
398 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
399 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
402 renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
403 clock-output-names = "msiof0";
405 mstp1_clks: mstp1_clks@e6150134 {
406 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
407 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
408 clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
409 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
411 renesas,clock-indices = <
412 R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
413 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
414 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_SY
417 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
418 "vsp1-du0", "vsp1-sy";
420 mstp2_clks: mstp2_clks@e6150138 {
421 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
422 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
423 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
424 <&mp_clk>, <&mp_clk>, <&mp_clk>;
426 renesas,clock-indices = <
427 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
428 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
429 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
432 "scifa2", "scifa1", "scifa0", "misof2", "scifb0",
433 "scifb1", "msiof1", "scifb2";
435 mstp3_clks: mstp3_clks@e615013c {
436 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
437 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
438 clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>,
439 <&cpg_clocks R8A7791_CLK_SD0>, <&mmc0_clk>, <&rclk_clk>;
441 renesas,clock-indices = <
442 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1
443 R8A7791_CLK_SDHI0 R8A7791_CLK_MMCIF0 R8A7791_CLK_CMT1
446 "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", "cmt1";
448 mstp5_clks: mstp5_clks@e6150144 {
449 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
450 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
451 clocks = <&extal_clk>, <&p_clk>;
453 renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
454 clock-output-names = "thermal", "pwm";
456 mstp7_clks: mstp7_clks@e615014c {
457 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
458 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
459 clocks = <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
460 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
461 <&zx_clk>, <&zx_clk>, <&zx_clk>;
463 renesas,clock-indices = <
464 R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
465 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
466 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
467 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
471 "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
472 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
474 mstp8_clks: mstp8_clks@e6150990 {
475 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
476 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
479 renesas,clock-indices = <R8A7791_CLK_ETHER>;
480 clock-output-names = "ether";
482 mstp9_clks: mstp9_clks@e6150994 {
483 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
484 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
485 clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>,
486 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
489 renesas,clock-indices = <
490 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD
491 R8A7791_CLK_I2C4 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3
492 R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
495 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3",
496 "i2c2", "i2c1", "i2c0";
498 mstp11_clks: mstp11_clks@e615099c {
499 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
500 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
501 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
503 renesas,clock-indices = <
504 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
506 clock-output-names = "scifa3", "scifa4", "scifa5";