arch/arm/boot/dts/r8a7791.dtsi

   1 /*
   2  * Device Tree Source for the r8a7791 SoC
   3  *
   4  * Copyright (C) 2013 Renesas Electronics Corporation
   5  * Copyright (C) 2013 Renesas Solutions Corp.
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a7791-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,r8a7791";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25
  26                 cpu0: cpu@0 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a15";
  29                         reg = <0>;
  30                         clock-frequency = <1300000000>;
  31                 };
  32
  33                 cpu1: cpu@1 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a15";
  36                         reg = <1>;
  37                         clock-frequency = <1300000000>;
  38                 };
  39         };
  40
  41         gic: interrupt-controller@f1001000 {
  42                 compatible = "arm,cortex-a15-gic";
  43                 #interrupt-cells = <3>;
  44                 #address-cells = <0>;
  45                 interrupt-controller;
  46                 reg = <0 0xf1001000 0 0x1000>,
  47                         <0 0xf1002000 0 0x1000>,
  48                         <0 0xf1004000 0 0x2000>,
  49                         <0 0xf1006000 0 0x2000>;
  50                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  51         };
  52
  53         gpio0: gpio@e6050000 {
  54                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  55                 reg = <0 0xe6050000 0 0x50>;
  56                 interrupt-parent = <&gic>;
  57                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
  58                 #gpio-cells = <2>;
  59                 gpio-controller;
  60                 gpio-ranges = <&pfc 0 0 32>;
  61                 #interrupt-cells = <2>;
  62                 interrupt-controller;
  63         };
  64
  65         gpio1: gpio@e6051000 {
  66                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  67                 reg = <0 0xe6051000 0 0x50>;
  68                 interrupt-parent = <&gic>;
  69                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
  70                 #gpio-cells = <2>;
  71                 gpio-controller;
  72                 gpio-ranges = <&pfc 0 32 32>;
  73                 #interrupt-cells = <2>;
  74                 interrupt-controller;
  75         };
  76
  77         gpio2: gpio@e6052000 {
  78                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  79                 reg = <0 0xe6052000 0 0x50>;
  80                 interrupt-parent = <&gic>;
  81                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
  82                 #gpio-cells = <2>;
  83                 gpio-controller;
  84                 gpio-ranges = <&pfc 0 64 32>;
  85                 #interrupt-cells = <2>;
  86                 interrupt-controller;
  87         };
  88
  89         gpio3: gpio@e6053000 {
  90                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  91                 reg = <0 0xe6053000 0 0x50>;
  92                 interrupt-parent = <&gic>;
  93                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
  94                 #gpio-cells = <2>;
  95                 gpio-controller;
  96                 gpio-ranges = <&pfc 0 96 32>;
  97                 #interrupt-cells = <2>;
  98                 interrupt-controller;
  99         };
 100
 101         gpio4: gpio@e6054000 {
 102                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 103                 reg = <0 0xe6054000 0 0x50>;
 104                 interrupt-parent = <&gic>;
 105                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 106                 #gpio-cells = <2>;
 107                 gpio-controller;
 108                 gpio-ranges = <&pfc 0 128 32>;
 109                 #interrupt-cells = <2>;
 110                 interrupt-controller;
 111         };
 112
 113         gpio5: gpio@e6055000 {
 114                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 115                 reg = <0 0xe6055000 0 0x50>;
 116                 interrupt-parent = <&gic>;
 117                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 118                 #gpio-cells = <2>;
 119                 gpio-controller;
 120                 gpio-ranges = <&pfc 0 160 32>;
 121                 #interrupt-cells = <2>;
 122                 interrupt-controller;
 123         };
 124
 125         gpio6: gpio@e6055400 {
 126                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 127                 reg = <0 0xe6055400 0 0x50>;
 128                 interrupt-parent = <&gic>;
 129                 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 130                 #gpio-cells = <2>;
 131                 gpio-controller;
 132                 gpio-ranges = <&pfc 0 192 32>;
 133                 #interrupt-cells = <2>;
 134                 interrupt-controller;
 135         };
 136
 137         gpio7: gpio@e6055800 {
 138                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 139                 reg = <0 0xe6055800 0 0x50>;
 140                 interrupt-parent = <&gic>;
 141                 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 142                 #gpio-cells = <2>;
 143                 gpio-controller;
 144                 gpio-ranges = <&pfc 0 224 26>;
 145                 #interrupt-cells = <2>;
 146                 interrupt-controller;
 147         };
 148
 149         thermal@e61f0000 {
 150                 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
 151                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 152                 interrupt-parent = <&gic>;
 153                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 154                 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
 155         };
 156
 157         timer {
 158                 compatible = "arm,armv7-timer";
 159                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 160                              <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 161                              <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 162                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 163         };
 164
 165         irqc0: interrupt-controller@e61c0000 {
 166                 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
 167                 #interrupt-cells = <2>;
 168                 interrupt-controller;
 169                 reg = <0 0xe61c0000 0 0x200>;
 170                 interrupt-parent = <&gic>;
 171                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 172                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 173                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 174                              <0 3 IRQ_TYPE_LEVEL_HIGH>,
 175                              <0 12 IRQ_TYPE_LEVEL_HIGH>,
 176                              <0 13 IRQ_TYPE_LEVEL_HIGH>,
 177                              <0 14 IRQ_TYPE_LEVEL_HIGH>,
 178                              <0 15 IRQ_TYPE_LEVEL_HIGH>,
 179                              <0 16 IRQ_TYPE_LEVEL_HIGH>,
 180                              <0 17 IRQ_TYPE_LEVEL_HIGH>;
 181         };
 182
 183         pfc: pfc@e6060000 {
 184                 compatible = "renesas,pfc-r8a7791";
 185                 reg = <0 0xe6060000 0 0x250>;
 186                 #gpio-range-cells = <3>;
 187         };
 188
 189         clocks {
 190                 #address-cells = <2>;
 191                 #size-cells = <2>;
 192                 ranges;
 193
 194                 /* External root clock */
 195                 extal_clk: extal_clk {
 196                         compatible = "fixed-clock";
 197                         #clock-cells = <0>;
 198                         /* This value must be overriden by the board. */
 199                         clock-frequency = <0>;
 200                         clock-output-names = "extal";
 201                 };
 202
 203                 /* Special CPG clocks */
 204                 cpg_clocks: cpg_clocks@e6150000 {
 205                         compatible = "renesas,r8a7791-cpg-clocks",
 206                                      "renesas,rcar-gen2-cpg-clocks";
 207                         reg = <0 0xe6150000 0 0x1000>;
 208                         clocks = <&extal_clk>;
 209                         #clock-cells = <1>;
 210                         clock-output-names = "main", "pll0", "pll1", "pll3",
 211                                              "lb", "qspi", "sdh", "sd0", "z";
 212                 };
 213
 214                 /* Variable factor clocks */
 215                 sd1_clk: sd2_clk@e6150078 {
 216                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 217                         reg = <0 0xe6150078 0 4>;
 218                         clocks = <&pll1_div2_clk>;
 219                         #clock-cells = <0>;
 220                         clock-output-names = "sd1";
 221                 };
 222                 sd2_clk: sd3_clk@e615007c {
 223                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 224                         reg = <0 0xe615007c 0 4>;
 225                         clocks = <&pll1_div2_clk>;
 226                         #clock-cells = <0>;
 227                         clock-output-names = "sd2";
 228                 };
 229                 mmc0_clk: mmc0_clk@e6150240 {
 230                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 231                         reg = <0 0xe6150240 0 4>;
 232                         clocks = <&pll1_div2_clk>;
 233                         #clock-cells = <0>;
 234                         clock-output-names = "mmc0";
 235                 };
 236                 ssp_clk: ssp_clk@e6150248 {
 237                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 238                         reg = <0 0xe6150248 0 4>;
 239                         clocks = <&pll1_div2_clk>;
 240                         #clock-cells = <0>;
 241                         clock-output-names = "ssp";
 242                 };
 243                 ssprs_clk: ssprs_clk@e615024c {
 244                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 245                         reg = <0 0xe615024c 0 4>;
 246                         clocks = <&pll1_div2_clk>;
 247                         #clock-cells = <0>;
 248                         clock-output-names = "ssprs";
 249                 };
 250
 251                 /* Fixed factor clocks */
 252                 pll1_div2_clk: pll1_div2_clk {
 253                         compatible = "fixed-factor-clock";
 254                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 255                         #clock-cells = <0>;
 256                         clock-div = <2>;
 257                         clock-mult = <1>;
 258                         clock-output-names = "pll1_div2";
 259                 };
 260                 zg_clk: zg_clk {
 261                         compatible = "fixed-factor-clock";
 262                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 263                         #clock-cells = <0>;
 264                         clock-div = <3>;
 265                         clock-mult = <1>;
 266                         clock-output-names = "zg";
 267                 };
 268                 zx_clk: zx_clk {
 269                         compatible = "fixed-factor-clock";
 270                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 271                         #clock-cells = <0>;
 272                         clock-div = <3>;
 273                         clock-mult = <1>;
 274                         clock-output-names = "zx";
 275                 };
 276                 zs_clk: zs_clk {
 277                         compatible = "fixed-factor-clock";
 278                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 279                         #clock-cells = <0>;
 280                         clock-div = <6>;
 281                         clock-mult = <1>;
 282                         clock-output-names = "zs";
 283                 };
 284                 hp_clk: hp_clk {
 285                         compatible = "fixed-factor-clock";
 286                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 287                         #clock-cells = <0>;
 288                         clock-div = <12>;
 289                         clock-mult = <1>;
 290                         clock-output-names = "hp";
 291                 };
 292                 i_clk: i_clk {
 293                         compatible = "fixed-factor-clock";
 294                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 295                         #clock-cells = <0>;
 296                         clock-div = <2>;
 297                         clock-mult = <1>;
 298                         clock-output-names = "i";
 299                 };
 300                 b_clk: b_clk {
 301                         compatible = "fixed-factor-clock";
 302                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 303                         #clock-cells = <0>;
 304                         clock-div = <12>;
 305                         clock-mult = <1>;
 306                         clock-output-names = "b";
 307                 };
 308                 p_clk: p_clk {
 309                         compatible = "fixed-factor-clock";
 310                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 311                         #clock-cells = <0>;
 312                         clock-div = <24>;
 313                         clock-mult = <1>;
 314                         clock-output-names = "p";
 315                 };
 316                 cl_clk: cl_clk {
 317                         compatible = "fixed-factor-clock";
 318                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 319                         #clock-cells = <0>;
 320                         clock-div = <48>;
 321                         clock-mult = <1>;
 322                         clock-output-names = "cl";
 323                 };
 324                 m2_clk: m2_clk {
 325                         compatible = "fixed-factor-clock";
 326                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 327                         #clock-cells = <0>;
 328                         clock-div = <8>;
 329                         clock-mult = <1>;
 330                         clock-output-names = "m2";
 331                 };
 332                 imp_clk: imp_clk {
 333                         compatible = "fixed-factor-clock";
 334                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 335                         #clock-cells = <0>;
 336                         clock-div = <4>;
 337                         clock-mult = <1>;
 338                         clock-output-names = "imp";
 339                 };
 340                 rclk_clk: rclk_clk {
 341                         compatible = "fixed-factor-clock";
 342                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 343                         #clock-cells = <0>;
 344                         clock-div = <(48 * 1024)>;
 345                         clock-mult = <1>;
 346                         clock-output-names = "rclk";
 347                 };
 348                 oscclk_clk: oscclk_clk {
 349                         compatible = "fixed-factor-clock";
 350                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 351                         #clock-cells = <0>;
 352                         clock-div = <(12 * 1024)>;
 353                         clock-mult = <1>;
 354                         clock-output-names = "oscclk";
 355                 };
 356                 zb3_clk: zb3_clk {
 357                         compatible = "fixed-factor-clock";
 358                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 359                         #clock-cells = <0>;
 360                         clock-div = <4>;
 361                         clock-mult = <1>;
 362                         clock-output-names = "zb3";
 363                 };
 364                 zb3d2_clk: zb3d2_clk {
 365                         compatible = "fixed-factor-clock";
 366                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 367                         #clock-cells = <0>;
 368                         clock-div = <8>;
 369                         clock-mult = <1>;
 370                         clock-output-names = "zb3d2";
 371                 };
 372                 ddr_clk: ddr_clk {
 373                         compatible = "fixed-factor-clock";
 374                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 375                         #clock-cells = <0>;
 376                         clock-div = <8>;
 377                         clock-mult = <1>;
 378                         clock-output-names = "ddr";
 379                 };
 380                 mp_clk: mp_clk {
 381                         compatible = "fixed-factor-clock";
 382                         clocks = <&pll1_div2_clk>;
 383                         #clock-cells = <0>;
 384                         clock-div = <15>;
 385                         clock-mult = <1>;
 386                         clock-output-names = "mp";
 387                 };
 388                 cp_clk: cp_clk {
 389                         compatible = "fixed-factor-clock";
 390                         clocks = <&extal_clk>;
 391                         #clock-cells = <0>;
 392                         clock-div = <2>;
 393                         clock-mult = <1>;
 394                         clock-output-names = "cp";
 395                 };
 396
 397                 /* Gate clocks */
 398                 mstp0_clks: mstp0_clks@e6150130 {
 399                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 400                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
 401                         clocks = <&mp_clk>;
 402                         #clock-cells = <1>;
 403                         renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
 404                         clock-output-names = "msiof0";
 405                 };
 406                 mstp1_clks: mstp1_clks@e6150134 {
 407                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 408                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 409                         clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
 410                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
 411                         #clock-cells = <1>;
 412                         renesas,clock-indices = <
 413                                 R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
 414                                 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
 415                                 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_SY
 416                         >;
 417                         clock-output-names =
 418                                 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
 419                                 "vsp1-du0", "vsp1-sy";
 420                 };
 421                 mstp2_clks: mstp2_clks@e6150138 {
 422                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 423                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 424                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 425                                  <&mp_clk>, <&mp_clk>, <&mp_clk>;
 426                         #clock-cells = <1>;
 427                         renesas,clock-indices = <
 428                                 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
 429                                 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
 430                                 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
 431                         >;
 432                         clock-output-names =
 433                                 "scifa2", "scifa1", "scifa0", "misof2", "scifb0",
 434                                 "scifb1", "msiof1", "scifb2";
 435                 };
 436                 mstp3_clks: mstp3_clks@e615013c {
 437                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 438                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 439                         clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>,
 440                                 <&cpg_clocks R8A7791_CLK_SD0>, <&mmc0_clk>, <&rclk_clk>;
 441                         #clock-cells = <1>;
 442                         renesas,clock-indices = <
 443                                 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1
 444                                 R8A7791_CLK_SDHI0 R8A7791_CLK_MMCIF0 R8A7791_CLK_CMT1
 445                         >;
 446                         clock-output-names =
 447                                 "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", "cmt1";
 448                 };
 449                 mstp5_clks: mstp5_clks@e6150144 {
 450                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 451                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
 452                         clocks = <&extal_clk>, <&p_clk>;
 453                         #clock-cells = <1>;
 454                         renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
 455                         clock-output-names = "thermal", "pwm";
 456                 };
 457                 mstp7_clks: mstp7_clks@e615014c {
 458                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 459                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 460                         clocks = <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
 461                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 462                                  <&zx_clk>, <&zx_clk>, <&zx_clk>;
 463                         #clock-cells = <1>;
 464                         renesas,clock-indices = <
 465                                 R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
 466                                 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
 467                                 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
 468                                 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
 469                                 R8A7791_CLK_LVDS0
 470                         >;
 471                         clock-output-names =
 472                                 "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
 473                                 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
 474                 };
 475                 mstp8_clks: mstp8_clks@e6150990 {
 476                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 477                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 478                         clocks = <&p_clk>;
 479                         #clock-cells = <1>;
 480                         renesas,clock-indices = <R8A7791_CLK_ETHER>;
 481                         clock-output-names = "ether";
 482                 };
 483                 mstp9_clks: mstp9_clks@e6150994 {
 484                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 485                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 486                         clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>,
 487                                  <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 488                                  <&p_clk>;
 489                         #clock-cells = <1>;
 490                         renesas,clock-indices = <
 491                                 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD
 492                                 R8A7791_CLK_I2C4 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3
 493                                 R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
 494                         >;
 495                         clock-output-names =
 496                                 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3",
 497                                 "i2c2", "i2c1", "i2c0";
 498                 };
 499                 mstp11_clks: mstp11_clks@e615099c {
 500                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 501                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
 502                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
 503                         #clock-cells = <1>;
 504                         renesas,clock-indices = <
 505                                 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
 506                         >;
 507                         clock-output-names = "scifa3", "scifa4", "scifa5";
 508                 };
 509         };
 510 };