2 * Device Tree Source for the r8a7791 SoC
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Renesas Solutions Corp.
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
12 #include <dt-bindings/clock/r8a7791-clock.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
17 compatible = "renesas,r8a7791";
18 interrupt-parent = <&gic>;
28 compatible = "arm,cortex-a15";
30 clock-frequency = <1300000000>;
35 compatible = "arm,cortex-a15";
37 clock-frequency = <1300000000>;
41 gic: interrupt-controller@f1001000 {
42 compatible = "arm,cortex-a15-gic";
43 #interrupt-cells = <3>;
46 reg = <0 0xf1001000 0 0x1000>,
47 <0 0xf1002000 0 0x1000>,
48 <0 0xf1004000 0 0x2000>,
49 <0 0xf1006000 0 0x2000>;
50 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
53 gpio0: gpio@e6050000 {
54 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
55 reg = <0 0xe6050000 0 0x50>;
56 interrupt-parent = <&gic>;
57 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
60 gpio-ranges = <&pfc 0 0 32>;
61 #interrupt-cells = <2>;
65 gpio1: gpio@e6051000 {
66 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
67 reg = <0 0xe6051000 0 0x50>;
68 interrupt-parent = <&gic>;
69 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
72 gpio-ranges = <&pfc 0 32 32>;
73 #interrupt-cells = <2>;
77 gpio2: gpio@e6052000 {
78 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
79 reg = <0 0xe6052000 0 0x50>;
80 interrupt-parent = <&gic>;
81 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
84 gpio-ranges = <&pfc 0 64 32>;
85 #interrupt-cells = <2>;
89 gpio3: gpio@e6053000 {
90 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
91 reg = <0 0xe6053000 0 0x50>;
92 interrupt-parent = <&gic>;
93 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
96 gpio-ranges = <&pfc 0 96 32>;
97 #interrupt-cells = <2>;
101 gpio4: gpio@e6054000 {
102 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
103 reg = <0 0xe6054000 0 0x50>;
104 interrupt-parent = <&gic>;
105 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
108 gpio-ranges = <&pfc 0 128 32>;
109 #interrupt-cells = <2>;
110 interrupt-controller;
113 gpio5: gpio@e6055000 {
114 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
115 reg = <0 0xe6055000 0 0x50>;
116 interrupt-parent = <&gic>;
117 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
120 gpio-ranges = <&pfc 0 160 32>;
121 #interrupt-cells = <2>;
122 interrupt-controller;
125 gpio6: gpio@e6055400 {
126 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
127 reg = <0 0xe6055400 0 0x50>;
128 interrupt-parent = <&gic>;
129 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
132 gpio-ranges = <&pfc 0 192 32>;
133 #interrupt-cells = <2>;
134 interrupt-controller;
137 gpio7: gpio@e6055800 {
138 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
139 reg = <0 0xe6055800 0 0x50>;
140 interrupt-parent = <&gic>;
141 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
144 gpio-ranges = <&pfc 0 224 26>;
145 #interrupt-cells = <2>;
146 interrupt-controller;
150 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
151 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
152 interrupt-parent = <&gic>;
153 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
154 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
158 compatible = "arm,armv7-timer";
159 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
160 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
161 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
162 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
165 irqc0: interrupt-controller@e61c0000 {
166 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
167 #interrupt-cells = <2>;
168 interrupt-controller;
169 reg = <0 0xe61c0000 0 0x200>;
170 interrupt-parent = <&gic>;
171 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
172 <0 1 IRQ_TYPE_LEVEL_HIGH>,
173 <0 2 IRQ_TYPE_LEVEL_HIGH>,
174 <0 3 IRQ_TYPE_LEVEL_HIGH>,
175 <0 12 IRQ_TYPE_LEVEL_HIGH>,
176 <0 13 IRQ_TYPE_LEVEL_HIGH>,
177 <0 14 IRQ_TYPE_LEVEL_HIGH>,
178 <0 15 IRQ_TYPE_LEVEL_HIGH>,
179 <0 16 IRQ_TYPE_LEVEL_HIGH>,
180 <0 17 IRQ_TYPE_LEVEL_HIGH>;
184 compatible = "renesas,pfc-r8a7791";
185 reg = <0 0xe6060000 0 0x250>;
186 #gpio-range-cells = <3>;
189 scifa0: serial@e6c40000 {
190 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
191 reg = <0 0xe6c40000 0 64>;
192 interrupt-parent = <&gic>;
193 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
195 clock-names = "sci_ick";
199 scifa1: serial@e6c50000 {
200 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
201 interrupt-parent = <&gic>;
202 reg = <0 0xe6c50000 0 64>;
203 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
205 clock-names = "sci_ick";
209 scifa2: serial@e6c60000 {
210 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
211 interrupt-parent = <&gic>;
212 reg = <0 0xe6c60000 0 64>;
213 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
215 clock-names = "sci_ick";
219 scifa3: serial@e6c70000 {
220 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
221 interrupt-parent = <&gic>;
222 reg = <0 0xe6c70000 0 64>;
223 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
225 clock-names = "sci_ick";
229 scifa4: serial@e6c78000 {
230 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
231 interrupt-parent = <&gic>;
232 reg = <0 0xe6c78000 0 64>;
233 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
235 clock-names = "sci_ick";
239 scifa5: serial@e6c80000 {
240 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
241 interrupt-parent = <&gic>;
242 reg = <0 0xe6c80000 0 64>;
243 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
245 clock-names = "sci_ick";
249 scifb0: serial@e6c20000 {
250 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
251 interrupt-parent = <&gic>;
252 reg = <0 0xe6c20000 0 64>;
253 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
255 clock-names = "sci_ick";
259 scifb1: serial@e6c30000 {
260 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
261 interrupt-parent = <&gic>;
262 reg = <0 0xe6c30000 0 64>;
263 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
265 clock-names = "sci_ick";
269 scifb2: serial@e6ce0000 {
270 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
271 interrupt-parent = <&gic>;
272 reg = <0 0xe6ce0000 0 64>;
273 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
275 clock-names = "sci_ick";
279 scif0: serial@e6e60000 {
280 compatible = "renesas,scif-r8a7791", "renesas,scif";
281 interrupt-parent = <&gic>;
282 reg = <0 0xe6e60000 0 64>;
283 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
285 clock-names = "sci_ick";
289 scif1: serial@e6e68000 {
290 compatible = "renesas,scif-r8a7791", "renesas,scif";
291 interrupt-parent = <&gic>;
292 reg = <0 0xe6e68000 0 64>;
293 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
295 clock-names = "sci_ick";
299 scif2: serial@e6e58000 {
300 compatible = "renesas,scif-r8a7791", "renesas,scif";
301 interrupt-parent = <&gic>;
302 reg = <0 0xe6e58000 0 64>;
303 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
305 clock-names = "sci_ick";
309 scif3: serial@e6ea8000 {
310 compatible = "renesas,scif-r8a7791", "renesas,scif";
311 interrupt-parent = <&gic>;
312 reg = <0 0xe6ea8000 0 64>;
313 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
315 clock-names = "sci_ick";
319 scif4: serial@e6ee0000 {
320 compatible = "renesas,scif-r8a7791", "renesas,scif";
321 interrupt-parent = <&gic>;
322 reg = <0 0xe6ee0000 0 64>;
323 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
325 clock-names = "sci_ick";
329 scif5: serial@e6ee8000 {
330 compatible = "renesas,scif-r8a7791", "renesas,scif";
331 interrupt-parent = <&gic>;
332 reg = <0 0xe6ee8000 0 64>;
333 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
335 clock-names = "sci_ick";
339 hscif0: serial@e62c0000 {
340 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
341 interrupt-parent = <&gic>;
342 reg = <0 0xe62c0000 0 96>;
343 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
345 clock-names = "sci_ick";
349 hscif1: serial@e62c8000 {
350 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
351 interrupt-parent = <&gic>;
352 reg = <0 0xe62c8000 0 96>;
353 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
355 clock-names = "sci_ick";
359 hscif2: serial@e62d0000 {
360 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
361 interrupt-parent = <&gic>;
362 reg = <0 0xe62d0000 0 96>;
363 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
365 clock-names = "sci_ick";
369 sata0: sata@ee300000 {
370 compatible = "renesas,sata-r8a7791";
371 reg = <0 0xee300000 0 0x2000>;
372 interrupt-parent = <&gic>;
373 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
378 sata1: sata@ee500000 {
379 compatible = "renesas,sata-r8a7791";
380 reg = <0 0xee500000 0 0x2000>;
381 interrupt-parent = <&gic>;
382 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
388 #address-cells = <2>;
392 /* External root clock */
393 extal_clk: extal_clk {
394 compatible = "fixed-clock";
396 /* This value must be overriden by the board. */
397 clock-frequency = <0>;
398 clock-output-names = "extal";
401 /* Special CPG clocks */
402 cpg_clocks: cpg_clocks@e6150000 {
403 compatible = "renesas,r8a7791-cpg-clocks",
404 "renesas,rcar-gen2-cpg-clocks";
405 reg = <0 0xe6150000 0 0x1000>;
406 clocks = <&extal_clk>;
408 clock-output-names = "main", "pll0", "pll1", "pll3",
409 "lb", "qspi", "sdh", "sd0", "z";
412 /* Variable factor clocks */
413 sd1_clk: sd2_clk@e6150078 {
414 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
415 reg = <0 0xe6150078 0 4>;
416 clocks = <&pll1_div2_clk>;
418 clock-output-names = "sd1";
420 sd2_clk: sd3_clk@e615007c {
421 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
422 reg = <0 0xe615007c 0 4>;
423 clocks = <&pll1_div2_clk>;
425 clock-output-names = "sd2";
427 mmc0_clk: mmc0_clk@e6150240 {
428 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
429 reg = <0 0xe6150240 0 4>;
430 clocks = <&pll1_div2_clk>;
432 clock-output-names = "mmc0";
434 ssp_clk: ssp_clk@e6150248 {
435 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
436 reg = <0 0xe6150248 0 4>;
437 clocks = <&pll1_div2_clk>;
439 clock-output-names = "ssp";
441 ssprs_clk: ssprs_clk@e615024c {
442 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
443 reg = <0 0xe615024c 0 4>;
444 clocks = <&pll1_div2_clk>;
446 clock-output-names = "ssprs";
449 /* Fixed factor clocks */
450 pll1_div2_clk: pll1_div2_clk {
451 compatible = "fixed-factor-clock";
452 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
456 clock-output-names = "pll1_div2";
459 compatible = "fixed-factor-clock";
460 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
464 clock-output-names = "zg";
467 compatible = "fixed-factor-clock";
468 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
472 clock-output-names = "zx";
475 compatible = "fixed-factor-clock";
476 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
480 clock-output-names = "zs";
483 compatible = "fixed-factor-clock";
484 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
488 clock-output-names = "hp";
491 compatible = "fixed-factor-clock";
492 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
496 clock-output-names = "i";
499 compatible = "fixed-factor-clock";
500 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
504 clock-output-names = "b";
507 compatible = "fixed-factor-clock";
508 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
512 clock-output-names = "p";
515 compatible = "fixed-factor-clock";
516 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
520 clock-output-names = "cl";
523 compatible = "fixed-factor-clock";
524 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
528 clock-output-names = "m2";
531 compatible = "fixed-factor-clock";
532 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
536 clock-output-names = "imp";
539 compatible = "fixed-factor-clock";
540 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
542 clock-div = <(48 * 1024)>;
544 clock-output-names = "rclk";
546 oscclk_clk: oscclk_clk {
547 compatible = "fixed-factor-clock";
548 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
550 clock-div = <(12 * 1024)>;
552 clock-output-names = "oscclk";
555 compatible = "fixed-factor-clock";
556 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
560 clock-output-names = "zb3";
562 zb3d2_clk: zb3d2_clk {
563 compatible = "fixed-factor-clock";
564 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
568 clock-output-names = "zb3d2";
571 compatible = "fixed-factor-clock";
572 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
576 clock-output-names = "ddr";
579 compatible = "fixed-factor-clock";
580 clocks = <&pll1_div2_clk>;
584 clock-output-names = "mp";
587 compatible = "fixed-factor-clock";
588 clocks = <&extal_clk>;
592 clock-output-names = "cp";
596 mstp0_clks: mstp0_clks@e6150130 {
597 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
598 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
601 renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
602 clock-output-names = "msiof0";
604 mstp1_clks: mstp1_clks@e6150134 {
605 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
606 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
607 clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
608 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
610 renesas,clock-indices = <
611 R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
612 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
613 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_SY
616 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
617 "vsp1-du0", "vsp1-sy";
619 mstp2_clks: mstp2_clks@e6150138 {
620 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
621 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
622 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
623 <&mp_clk>, <&mp_clk>, <&mp_clk>;
625 renesas,clock-indices = <
626 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
627 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
628 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
631 "scifa2", "scifa1", "scifa0", "misof2", "scifb0",
632 "scifb1", "msiof1", "scifb2";
634 mstp3_clks: mstp3_clks@e615013c {
635 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
636 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
637 clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>,
638 <&cpg_clocks R8A7791_CLK_SD0>, <&mmc0_clk>, <&rclk_clk>;
640 renesas,clock-indices = <
641 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1
642 R8A7791_CLK_SDHI0 R8A7791_CLK_MMCIF0 R8A7791_CLK_CMT1
645 "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", "cmt1";
647 mstp5_clks: mstp5_clks@e6150144 {
648 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
649 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
650 clocks = <&extal_clk>, <&p_clk>;
652 renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
653 clock-output-names = "thermal", "pwm";
655 mstp7_clks: mstp7_clks@e615014c {
656 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
657 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
658 clocks = <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
659 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
660 <&zx_clk>, <&zx_clk>, <&zx_clk>;
662 renesas,clock-indices = <
663 R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
664 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
665 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
666 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
670 "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
671 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
673 mstp8_clks: mstp8_clks@e6150990 {
674 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
675 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
676 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
679 renesas,clock-indices = <
680 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
681 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
684 "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
686 mstp9_clks: mstp9_clks@e6150994 {
687 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
688 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
689 clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>,
690 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
693 renesas,clock-indices = <
694 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD
695 R8A7791_CLK_I2C4 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3
696 R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
699 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3",
700 "i2c2", "i2c1", "i2c0";
702 mstp11_clks: mstp11_clks@e615099c {
703 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
704 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
705 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
707 renesas,clock-indices = <
708 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
710 clock-output-names = "scifa3", "scifa4", "scifa5";