arch/arm/boot/dts/r8a7791.dtsi

   1 /*
   2  * Device Tree Source for the r8a7791 SoC
   3  *
   4  * Copyright (C) 2013-2014 Renesas Electronics Corporation
   5  * Copyright (C) 2013-2014 Renesas Solutions Corp.
   6  * Copyright (C) 2014 Cogent Embedded Inc.
   7  *
   8  * This file is licensed under the terms of the GNU General Public License
   9  * version 2.  This program is licensed "as is" without any warranty of any
  10  * kind, whether express or implied.
  11  */
  12
  13 #include <dt-bindings/clock/r8a7791-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16
  17 / {
  18         compatible = "renesas,r8a7791";
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         aliases {
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 i2c4 = &i2c4;
  29                 i2c5 = &i2c5;
  30                 i2c6 = &i2c6;
  31                 i2c7 = &i2c7;
  32                 i2c8 = &i2c8;
  33                 spi0 = &qspi;
  34                 spi1 = &msiof0;
  35                 spi2 = &msiof1;
  36                 spi3 = &msiof2;
  37                 vin0 = &vin0;
  38                 vin1 = &vin1;
  39                 vin2 = &vin2;
  40         };
  41
  42         cpus {
  43                 #address-cells = <1>;
  44                 #size-cells = <0>;
  45
  46                 cpu0: cpu@0 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a15";
  49                         reg = <0>;
  50                         clock-frequency = <1500000000>;
  51                         voltage-tolerance = <1>; /* 1% */
  52                         clocks = <&cpg_clocks R8A7791_CLK_Z>;
  53                         clock-latency = <300000>; /* 300 us */
  54
  55                         /* kHz - uV - OPPs unknown yet */
  56                         operating-points = <1500000 1000000>,
  57                                            <1312500 1000000>,
  58                                            <1125000 1000000>,
  59                                            < 937500 1000000>,
  60                                            < 750000 1000000>,
  61                                            < 375000 1000000>;
  62                 };
  63
  64                 cpu1: cpu@1 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a15";
  67                         reg = <1>;
  68                         clock-frequency = <1500000000>;
  69                 };
  70         };
  71
  72         gic: interrupt-controller@f1001000 {
  73                 compatible = "arm,cortex-a15-gic";
  74                 #interrupt-cells = <3>;
  75                 #address-cells = <0>;
  76                 interrupt-controller;
  77                 reg = <0 0xf1001000 0 0x1000>,
  78                         <0 0xf1002000 0 0x1000>,
  79                         <0 0xf1004000 0 0x2000>,
  80                         <0 0xf1006000 0 0x2000>;
  81                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  82         };
  83
  84         gpio0: gpio@e6050000 {
  85                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  86                 reg = <0 0xe6050000 0 0x50>;
  87                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
  88                 #gpio-cells = <2>;
  89                 gpio-controller;
  90                 gpio-ranges = <&pfc 0 0 32>;
  91                 #interrupt-cells = <2>;
  92                 interrupt-controller;
  93                 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
  94         };
  95
  96         gpio1: gpio@e6051000 {
  97                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  98                 reg = <0 0xe6051000 0 0x50>;
  99                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 100                 #gpio-cells = <2>;
 101                 gpio-controller;
 102                 gpio-ranges = <&pfc 0 32 32>;
 103                 #interrupt-cells = <2>;
 104                 interrupt-controller;
 105                 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
 106         };
 107
 108         gpio2: gpio@e6052000 {
 109                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 110                 reg = <0 0xe6052000 0 0x50>;
 111                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 112                 #gpio-cells = <2>;
 113                 gpio-controller;
 114                 gpio-ranges = <&pfc 0 64 32>;
 115                 #interrupt-cells = <2>;
 116                 interrupt-controller;
 117                 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
 118         };
 119
 120         gpio3: gpio@e6053000 {
 121                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 122                 reg = <0 0xe6053000 0 0x50>;
 123                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 124                 #gpio-cells = <2>;
 125                 gpio-controller;
 126                 gpio-ranges = <&pfc 0 96 32>;
 127                 #interrupt-cells = <2>;
 128                 interrupt-controller;
 129                 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
 130         };
 131
 132         gpio4: gpio@e6054000 {
 133                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 134                 reg = <0 0xe6054000 0 0x50>;
 135                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 136                 #gpio-cells = <2>;
 137                 gpio-controller;
 138                 gpio-ranges = <&pfc 0 128 32>;
 139                 #interrupt-cells = <2>;
 140                 interrupt-controller;
 141                 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
 142         };
 143
 144         gpio5: gpio@e6055000 {
 145                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 146                 reg = <0 0xe6055000 0 0x50>;
 147                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 148                 #gpio-cells = <2>;
 149                 gpio-controller;
 150                 gpio-ranges = <&pfc 0 160 32>;
 151                 #interrupt-cells = <2>;
 152                 interrupt-controller;
 153                 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
 154         };
 155
 156         gpio6: gpio@e6055400 {
 157                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 158                 reg = <0 0xe6055400 0 0x50>;
 159                 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 160                 #gpio-cells = <2>;
 161                 gpio-controller;
 162                 gpio-ranges = <&pfc 0 192 32>;
 163                 #interrupt-cells = <2>;
 164                 interrupt-controller;
 165                 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
 166         };
 167
 168         gpio7: gpio@e6055800 {
 169                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 170                 reg = <0 0xe6055800 0 0x50>;
 171                 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 172                 #gpio-cells = <2>;
 173                 gpio-controller;
 174                 gpio-ranges = <&pfc 0 224 26>;
 175                 #interrupt-cells = <2>;
 176                 interrupt-controller;
 177                 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
 178         };
 179
 180         thermal@e61f0000 {
 181                 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
 182                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 183                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 184                 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
 185         };
 186
 187         timer {
 188                 compatible = "arm,armv7-timer";
 189                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 190                              <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 191                              <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 192                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 193         };
 194
 195         cmt0: timer@ffca0000 {
 196                 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
 197                 reg = <0 0xffca0000 0 0x1004>;
 198                 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
 199                              <0 143 IRQ_TYPE_LEVEL_HIGH>;
 200                 clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
 201                 clock-names = "fck";
 202
 203                 renesas,channels-mask = <0x60>;
 204
 205                 status = "disabled";
 206         };
 207
 208         cmt1: timer@e6130000 {
 209                 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
 210                 reg = <0 0xe6130000 0 0x1004>;
 211                 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
 212                              <0 121 IRQ_TYPE_LEVEL_HIGH>,
 213                              <0 122 IRQ_TYPE_LEVEL_HIGH>,
 214                              <0 123 IRQ_TYPE_LEVEL_HIGH>,
 215                              <0 124 IRQ_TYPE_LEVEL_HIGH>,
 216                              <0 125 IRQ_TYPE_LEVEL_HIGH>,
 217                              <0 126 IRQ_TYPE_LEVEL_HIGH>,
 218                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 219                 clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
 220                 clock-names = "fck";
 221
 222                 renesas,channels-mask = <0xff>;
 223
 224                 status = "disabled";
 225         };
 226
 227         irqc0: interrupt-controller@e61c0000 {
 228                 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
 229                 #interrupt-cells = <2>;
 230                 interrupt-controller;
 231                 reg = <0 0xe61c0000 0 0x200>;
 232                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 233                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 234                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 235                              <0 3 IRQ_TYPE_LEVEL_HIGH>,
 236                              <0 12 IRQ_TYPE_LEVEL_HIGH>,
 237                              <0 13 IRQ_TYPE_LEVEL_HIGH>,
 238                              <0 14 IRQ_TYPE_LEVEL_HIGH>,
 239                              <0 15 IRQ_TYPE_LEVEL_HIGH>,
 240                              <0 16 IRQ_TYPE_LEVEL_HIGH>,
 241                              <0 17 IRQ_TYPE_LEVEL_HIGH>;
 242         };
 243
 244         dmac0: dma-controller@e6700000 {
 245                 compatible = "renesas,rcar-dmac";
 246                 reg = <0 0xe6700000 0 0x20000>;
 247                 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
 248                               0 200 IRQ_TYPE_LEVEL_HIGH
 249                               0 201 IRQ_TYPE_LEVEL_HIGH
 250                               0 202 IRQ_TYPE_LEVEL_HIGH
 251                               0 203 IRQ_TYPE_LEVEL_HIGH
 252                               0 204 IRQ_TYPE_LEVEL_HIGH
 253                               0 205 IRQ_TYPE_LEVEL_HIGH
 254                               0 206 IRQ_TYPE_LEVEL_HIGH
 255                               0 207 IRQ_TYPE_LEVEL_HIGH
 256                               0 208 IRQ_TYPE_LEVEL_HIGH
 257                               0 209 IRQ_TYPE_LEVEL_HIGH
 258                               0 210 IRQ_TYPE_LEVEL_HIGH
 259                               0 211 IRQ_TYPE_LEVEL_HIGH
 260                               0 212 IRQ_TYPE_LEVEL_HIGH
 261                               0 213 IRQ_TYPE_LEVEL_HIGH
 262                               0 214 IRQ_TYPE_LEVEL_HIGH>;
 263                 interrupt-names = "error",
 264                                 "ch0", "ch1", "ch2", "ch3",
 265                                 "ch4", "ch5", "ch6", "ch7",
 266                                 "ch8", "ch9", "ch10", "ch11",
 267                                 "ch12", "ch13", "ch14";
 268                 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
 269                 clock-names = "fck";
 270                 #dma-cells = <1>;
 271                 dma-channels = <15>;
 272         };
 273
 274         dmac1: dma-controller@e6720000 {
 275                 compatible = "renesas,rcar-dmac";
 276                 reg = <0 0xe6720000 0 0x20000>;
 277                 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
 278                               0 216 IRQ_TYPE_LEVEL_HIGH
 279                               0 217 IRQ_TYPE_LEVEL_HIGH
 280                               0 218 IRQ_TYPE_LEVEL_HIGH
 281                               0 219 IRQ_TYPE_LEVEL_HIGH
 282                               0 308 IRQ_TYPE_LEVEL_HIGH
 283                               0 309 IRQ_TYPE_LEVEL_HIGH
 284                               0 310 IRQ_TYPE_LEVEL_HIGH
 285                               0 311 IRQ_TYPE_LEVEL_HIGH
 286                               0 312 IRQ_TYPE_LEVEL_HIGH
 287                               0 313 IRQ_TYPE_LEVEL_HIGH
 288                               0 314 IRQ_TYPE_LEVEL_HIGH
 289                               0 315 IRQ_TYPE_LEVEL_HIGH
 290                               0 316 IRQ_TYPE_LEVEL_HIGH
 291                               0 317 IRQ_TYPE_LEVEL_HIGH
 292                               0 318 IRQ_TYPE_LEVEL_HIGH>;
 293                 interrupt-names = "error",
 294                                 "ch0", "ch1", "ch2", "ch3",
 295                                 "ch4", "ch5", "ch6", "ch7",
 296                                 "ch8", "ch9", "ch10", "ch11",
 297                                 "ch12", "ch13", "ch14";
 298                 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
 299                 clock-names = "fck";
 300                 #dma-cells = <1>;
 301                 dma-channels = <15>;
 302         };
 303
 304         audma0: dma-controller@ec700000 {
 305                 compatible = "renesas,rcar-dmac";
 306                 reg = <0 0xec700000 0 0x10000>;
 307                 interrupts =    <0 346 IRQ_TYPE_LEVEL_HIGH
 308                                  0 320 IRQ_TYPE_LEVEL_HIGH
 309                                  0 321 IRQ_TYPE_LEVEL_HIGH
 310                                  0 322 IRQ_TYPE_LEVEL_HIGH
 311                                  0 323 IRQ_TYPE_LEVEL_HIGH
 312                                  0 324 IRQ_TYPE_LEVEL_HIGH
 313                                  0 325 IRQ_TYPE_LEVEL_HIGH
 314                                  0 326 IRQ_TYPE_LEVEL_HIGH
 315                                  0 327 IRQ_TYPE_LEVEL_HIGH
 316                                  0 328 IRQ_TYPE_LEVEL_HIGH
 317                                  0 329 IRQ_TYPE_LEVEL_HIGH
 318                                  0 330 IRQ_TYPE_LEVEL_HIGH
 319                                  0 331 IRQ_TYPE_LEVEL_HIGH
 320                                  0 332 IRQ_TYPE_LEVEL_HIGH>;
 321                 interrupt-names = "error",
 322                                 "ch0", "ch1", "ch2", "ch3",
 323                                 "ch4", "ch5", "ch6", "ch7",
 324                                 "ch8", "ch9", "ch10", "ch11",
 325                                 "ch12";
 326                 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
 327                 clock-names = "fck";
 328                 #dma-cells = <1>;
 329                 dma-channels = <13>;
 330         };
 331
 332         audma1: dma-controller@ec720000 {
 333                 compatible = "renesas,rcar-dmac";
 334                 reg = <0 0xec720000 0 0x10000>;
 335                 interrupts =    <0 347 IRQ_TYPE_LEVEL_HIGH
 336                                  0 333 IRQ_TYPE_LEVEL_HIGH
 337                                  0 334 IRQ_TYPE_LEVEL_HIGH
 338                                  0 335 IRQ_TYPE_LEVEL_HIGH
 339                                  0 336 IRQ_TYPE_LEVEL_HIGH
 340                                  0 337 IRQ_TYPE_LEVEL_HIGH
 341                                  0 338 IRQ_TYPE_LEVEL_HIGH
 342                                  0 339 IRQ_TYPE_LEVEL_HIGH
 343                                  0 340 IRQ_TYPE_LEVEL_HIGH
 344                                  0 341 IRQ_TYPE_LEVEL_HIGH
 345                                  0 342 IRQ_TYPE_LEVEL_HIGH
 346                                  0 343 IRQ_TYPE_LEVEL_HIGH
 347                                  0 344 IRQ_TYPE_LEVEL_HIGH
 348                                  0 345 IRQ_TYPE_LEVEL_HIGH>;
 349                 interrupt-names = "error",
 350                                 "ch0", "ch1", "ch2", "ch3",
 351                                 "ch4", "ch5", "ch6", "ch7",
 352                                 "ch8", "ch9", "ch10", "ch11",
 353                                 "ch12";
 354                 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
 355                 clock-names = "fck";
 356                 #dma-cells = <1>;
 357                 dma-channels = <13>;
 358         };
 359
 360         /* The memory map in the User's Manual maps the cores to bus numbers */
 361         i2c0: i2c@e6508000 {
 362                 #address-cells = <1>;
 363                 #size-cells = <0>;
 364                 compatible = "renesas,i2c-r8a7791";
 365                 reg = <0 0xe6508000 0 0x40>;
 366                 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 367                 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
 368                 status = "disabled";
 369         };
 370
 371         i2c1: i2c@e6518000 {
 372                 #address-cells = <1>;
 373                 #size-cells = <0>;
 374                 compatible = "renesas,i2c-r8a7791";
 375                 reg = <0 0xe6518000 0 0x40>;
 376                 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 377                 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
 378                 status = "disabled";
 379         };
 380
 381         i2c2: i2c@e6530000 {
 382                 #address-cells = <1>;
 383                 #size-cells = <0>;
 384                 compatible = "renesas,i2c-r8a7791";
 385                 reg = <0 0xe6530000 0 0x40>;
 386                 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 387                 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
 388                 status = "disabled";
 389         };
 390
 391         i2c3: i2c@e6540000 {
 392                 #address-cells = <1>;
 393                 #size-cells = <0>;
 394                 compatible = "renesas,i2c-r8a7791";
 395                 reg = <0 0xe6540000 0 0x40>;
 396                 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 397                 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
 398                 status = "disabled";
 399         };
 400
 401         i2c4: i2c@e6520000 {
 402                 #address-cells = <1>;
 403                 #size-cells = <0>;
 404                 compatible = "renesas,i2c-r8a7791";
 405                 reg = <0 0xe6520000 0 0x40>;
 406                 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
 407                 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
 408                 status = "disabled";
 409         };
 410
 411         i2c5: i2c@e6528000 {
 412                 /* doesn't need pinmux */
 413                 #address-cells = <1>;
 414                 #size-cells = <0>;
 415                 compatible = "renesas,i2c-r8a7791";
 416                 reg = <0 0xe6528000 0 0x40>;
 417                 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
 418                 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
 419                 status = "disabled";
 420         };
 421
 422         i2c6: i2c@e60b0000 {
 423                 /* doesn't need pinmux */
 424                 #address-cells = <1>;
 425                 #size-cells = <0>;
 426                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 427                 reg = <0 0xe60b0000 0 0x425>;
 428                 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
 429                 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
 430                 status = "disabled";
 431         };
 432
 433         i2c7: i2c@e6500000 {
 434                 #address-cells = <1>;
 435                 #size-cells = <0>;
 436                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 437                 reg = <0 0xe6500000 0 0x425>;
 438                 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
 439                 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
 440                 status = "disabled";
 441         };
 442
 443         i2c8: i2c@e6510000 {
 444                 #address-cells = <1>;
 445                 #size-cells = <0>;
 446                 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
 447                 reg = <0 0xe6510000 0 0x425>;
 448                 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
 449                 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
 450                 status = "disabled";
 451         };
 452
 453         pfc: pfc@e6060000 {
 454                 compatible = "renesas,pfc-r8a7791";
 455                 reg = <0 0xe6060000 0 0x250>;
 456                 #gpio-range-cells = <3>;
 457         };
 458
 459         mmcif0: mmc@ee200000 {
 460                 compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
 461                 reg = <0 0xee200000 0 0x80>;
 462                 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
 463                 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
 464                 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
 465                 dma-names = "tx", "rx";
 466                 reg-io-width = <4>;
 467                 status = "disabled";
 468         };
 469
 470         sdhi0: sd@ee100000 {
 471                 compatible = "renesas,sdhi-r8a7791";
 472                 reg = <0 0xee100000 0 0x200>;
 473                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 474                 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
 475                 status = "disabled";
 476         };
 477
 478         sdhi1: sd@ee140000 {
 479                 compatible = "renesas,sdhi-r8a7791";
 480                 reg = <0 0xee140000 0 0x100>;
 481                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 482                 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
 483                 status = "disabled";
 484         };
 485
 486         sdhi2: sd@ee160000 {
 487                 compatible = "renesas,sdhi-r8a7791";
 488                 reg = <0 0xee160000 0 0x100>;
 489                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 490                 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
 491                 status = "disabled";
 492         };
 493
 494         scifa0: serial@e6c40000 {
 495                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 496                 reg = <0 0xe6c40000 0 64>;
 497                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 498                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
 499                 clock-names = "sci_ick";
 500                 status = "disabled";
 501         };
 502
 503         scifa1: serial@e6c50000 {
 504                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 505                 reg = <0 0xe6c50000 0 64>;
 506                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 507                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
 508                 clock-names = "sci_ick";
 509                 status = "disabled";
 510         };
 511
 512         scifa2: serial@e6c60000 {
 513                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 514                 reg = <0 0xe6c60000 0 64>;
 515                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 516                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
 517                 clock-names = "sci_ick";
 518                 status = "disabled";
 519         };
 520
 521         scifa3: serial@e6c70000 {
 522                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 523                 reg = <0 0xe6c70000 0 64>;
 524                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 525                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
 526                 clock-names = "sci_ick";
 527                 status = "disabled";
 528         };
 529
 530         scifa4: serial@e6c78000 {
 531                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 532                 reg = <0 0xe6c78000 0 64>;
 533                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 534                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
 535                 clock-names = "sci_ick";
 536                 status = "disabled";
 537         };
 538
 539         scifa5: serial@e6c80000 {
 540                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 541                 reg = <0 0xe6c80000 0 64>;
 542                 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 543                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
 544                 clock-names = "sci_ick";
 545                 status = "disabled";
 546         };
 547
 548         scifb0: serial@e6c20000 {
 549                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 550                 reg = <0 0xe6c20000 0 64>;
 551                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 552                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
 553                 clock-names = "sci_ick";
 554                 status = "disabled";
 555         };
 556
 557         scifb1: serial@e6c30000 {
 558                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 559                 reg = <0 0xe6c30000 0 64>;
 560                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 561                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
 562                 clock-names = "sci_ick";
 563                 status = "disabled";
 564         };
 565
 566         scifb2: serial@e6ce0000 {
 567                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 568                 reg = <0 0xe6ce0000 0 64>;
 569                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 570                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
 571                 clock-names = "sci_ick";
 572                 status = "disabled";
 573         };
 574
 575         scif0: serial@e6e60000 {
 576                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 577                 reg = <0 0xe6e60000 0 64>;
 578                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 579                 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
 580                 clock-names = "sci_ick";
 581                 status = "disabled";
 582         };
 583
 584         scif1: serial@e6e68000 {
 585                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 586                 reg = <0 0xe6e68000 0 64>;
 587                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 588                 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
 589                 clock-names = "sci_ick";
 590                 status = "disabled";
 591         };
 592
 593         scif2: serial@e6e58000 {
 594                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 595                 reg = <0 0xe6e58000 0 64>;
 596                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 597                 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
 598                 clock-names = "sci_ick";
 599                 status = "disabled";
 600         };
 601
 602         scif3: serial@e6ea8000 {
 603                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 604                 reg = <0 0xe6ea8000 0 64>;
 605                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 606                 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
 607                 clock-names = "sci_ick";
 608                 status = "disabled";
 609         };
 610
 611         scif4: serial@e6ee0000 {
 612                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 613                 reg = <0 0xe6ee0000 0 64>;
 614                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 615                 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
 616                 clock-names = "sci_ick";
 617                 status = "disabled";
 618         };
 619
 620         scif5: serial@e6ee8000 {
 621                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 622                 reg = <0 0xe6ee8000 0 64>;
 623                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 624                 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
 625                 clock-names = "sci_ick";
 626                 status = "disabled";
 627         };
 628
 629         hscif0: serial@e62c0000 {
 630                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 631                 reg = <0 0xe62c0000 0 96>;
 632                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 633                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
 634                 clock-names = "sci_ick";
 635                 status = "disabled";
 636         };
 637
 638         hscif1: serial@e62c8000 {
 639                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 640                 reg = <0 0xe62c8000 0 96>;
 641                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 642                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
 643                 clock-names = "sci_ick";
 644                 status = "disabled";
 645         };
 646
 647         hscif2: serial@e62d0000 {
 648                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 649                 reg = <0 0xe62d0000 0 96>;
 650                 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 651                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
 652                 clock-names = "sci_ick";
 653                 status = "disabled";
 654         };
 655
 656         ether: ethernet@ee700000 {
 657                 compatible = "renesas,ether-r8a7791";
 658                 reg = <0 0xee700000 0 0x400>;
 659                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 660                 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
 661                 phy-mode = "rmii";
 662                 #address-cells = <1>;
 663                 #size-cells = <0>;
 664                 status = "disabled";
 665         };
 666
 667         sata0: sata@ee300000 {
 668                 compatible = "renesas,sata-r8a7791";
 669                 reg = <0 0xee300000 0 0x2000>;
 670                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 671                 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
 672                 status = "disabled";
 673         };
 674
 675         sata1: sata@ee500000 {
 676                 compatible = "renesas,sata-r8a7791";
 677                 reg = <0 0xee500000 0 0x2000>;
 678                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 679                 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
 680                 status = "disabled";
 681         };
 682
 683         hsusb: usb@e6590000 {
 684                 compatible = "renesas,usbhs-r8a7791";
 685                 reg = <0 0xe6590000 0 0x100>;
 686                 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 687                 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
 688                 renesas,buswait = <4>;
 689                 phys = <&usb0 1>;
 690                 phy-names = "usb";
 691                 status = "disabled";
 692         };
 693
 694         usbphy: usb-phy@e6590100 {
 695                 compatible = "renesas,usb-phy-r8a7791";
 696                 reg = <0 0xe6590100 0 0x100>;
 697                 #address-cells = <1>;
 698                 #size-cells = <0>;
 699                 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
 700                 clock-names = "usbhs";
 701                 status = "disabled";
 702
 703                 usb0: usb-channel@0 {
 704                         reg = <0>;
 705                         #phy-cells = <1>;
 706                 };
 707                 usb2: usb-channel@2 {
 708                         reg = <2>;
 709                         #phy-cells = <1>;
 710                 };
 711         };
 712
 713         vin0: video@e6ef0000 {
 714                 compatible = "renesas,vin-r8a7791";
 715                 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
 716                 reg = <0 0xe6ef0000 0 0x1000>;
 717                 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
 718                 status = "disabled";
 719         };
 720
 721         vin1: video@e6ef1000 {
 722                 compatible = "renesas,vin-r8a7791";
 723                 clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
 724                 reg = <0 0xe6ef1000 0 0x1000>;
 725                 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
 726                 status = "disabled";
 727         };
 728
 729         vin2: video@e6ef2000 {
 730                 compatible = "renesas,vin-r8a7791";
 731                 clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
 732                 reg = <0 0xe6ef2000 0 0x1000>;
 733                 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
 734                 status = "disabled";
 735         };
 736
 737         vsp1@fe928000 {
 738                 compatible = "renesas,vsp1";
 739                 reg = <0 0xfe928000 0 0x8000>;
 740                 interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
 741                 clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
 742
 743                 renesas,has-lut;
 744                 renesas,has-sru;
 745                 renesas,#rpf = <5>;
 746                 renesas,#uds = <3>;
 747                 renesas,#wpf = <4>;
 748         };
 749
 750         vsp1@fe930000 {
 751                 compatible = "renesas,vsp1";
 752                 reg = <0 0xfe930000 0 0x8000>;
 753                 interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
 754                 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
 755
 756                 renesas,has-lif;
 757                 renesas,has-lut;
 758                 renesas,#rpf = <4>;
 759                 renesas,#uds = <1>;
 760                 renesas,#wpf = <4>;
 761         };
 762
 763         vsp1@fe938000 {
 764                 compatible = "renesas,vsp1";
 765                 reg = <0 0xfe938000 0 0x8000>;
 766                 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
 767                 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
 768
 769                 renesas,has-lif;
 770                 renesas,has-lut;
 771                 renesas,#rpf = <4>;
 772                 renesas,#uds = <1>;
 773                 renesas,#wpf = <4>;
 774         };
 775
 776         du: display@feb00000 {
 777                 compatible = "renesas,du-r8a7791";
 778                 reg = <0 0xfeb00000 0 0x40000>,
 779                       <0 0xfeb90000 0 0x1c>;
 780                 reg-names = "du", "lvds.0";
 781                 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
 782                              <0 268 IRQ_TYPE_LEVEL_HIGH>;
 783                 clocks = <&mstp7_clks R8A7791_CLK_DU0>,
 784                          <&mstp7_clks R8A7791_CLK_DU1>,
 785                          <&mstp7_clks R8A7791_CLK_LVDS0>;
 786                 clock-names = "du.0", "du.1", "lvds.0";
 787                 status = "disabled";
 788
 789                 ports {
 790                         #address-cells = <1>;
 791                         #size-cells = <0>;
 792
 793                         port@0 {
 794                                 reg = <0>;
 795                                 du_out_rgb: endpoint {
 796                                 };
 797                         };
 798                         port@1 {
 799                                 reg = <1>;
 800                                 du_out_lvds0: endpoint {
 801                                 };
 802                         };
 803                 };
 804         };
 805
 806         clocks {
 807                 #address-cells = <2>;
 808                 #size-cells = <2>;
 809                 ranges;
 810
 811                 /* External root clock */
 812                 extal_clk: extal_clk {
 813                         compatible = "fixed-clock";
 814                         #clock-cells = <0>;
 815                         /* This value must be overriden by the board. */
 816                         clock-frequency = <0>;
 817                         clock-output-names = "extal";
 818                 };
 819
 820                 /*
 821                  * The external audio clocks are configured as 0 Hz fixed frequency clocks by
 822                  * default. Boards that provide audio clocks should override them.
 823                  */
 824                 audio_clk_a: audio_clk_a {
 825                         compatible = "fixed-clock";
 826                         #clock-cells = <0>;
 827                         clock-frequency = <0>;
 828                         clock-output-names = "audio_clk_a";
 829                 };
 830                 audio_clk_b: audio_clk_b {
 831                         compatible = "fixed-clock";
 832                         #clock-cells = <0>;
 833                         clock-frequency = <0>;
 834                         clock-output-names = "audio_clk_b";
 835                 };
 836                 audio_clk_c: audio_clk_c {
 837                         compatible = "fixed-clock";
 838                         #clock-cells = <0>;
 839                         clock-frequency = <0>;
 840                         clock-output-names = "audio_clk_c";
 841                 };
 842
 843                 /* External PCIe clock - can be overridden by the board */
 844                 pcie_bus_clk: pcie_bus_clk {
 845                         compatible = "fixed-clock";
 846                         #clock-cells = <0>;
 847                         clock-frequency = <100000000>;
 848                         clock-output-names = "pcie_bus";
 849                         status = "disabled";
 850                 };
 851
 852                 /* Special CPG clocks */
 853                 cpg_clocks: cpg_clocks@e6150000 {
 854                         compatible = "renesas,r8a7791-cpg-clocks",
 855                                      "renesas,rcar-gen2-cpg-clocks";
 856                         reg = <0 0xe6150000 0 0x1000>;
 857                         clocks = <&extal_clk>;
 858                         #clock-cells = <1>;
 859                         clock-output-names = "main", "pll0", "pll1", "pll3",
 860                                              "lb", "qspi", "sdh", "sd0", "z";
 861                 };
 862
 863                 /* Variable factor clocks */
 864                 sd1_clk: sd2_clk@e6150078 {
 865                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 866                         reg = <0 0xe6150078 0 4>;
 867                         clocks = <&pll1_div2_clk>;
 868                         #clock-cells = <0>;
 869                         clock-output-names = "sd1";
 870                 };
 871                 sd2_clk: sd3_clk@e615026c {
 872                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 873                         reg = <0 0xe615026c 0 4>;
 874                         clocks = <&pll1_div2_clk>;
 875                         #clock-cells = <0>;
 876                         clock-output-names = "sd2";
 877                 };
 878                 mmc0_clk: mmc0_clk@e6150240 {
 879                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 880                         reg = <0 0xe6150240 0 4>;
 881                         clocks = <&pll1_div2_clk>;
 882                         #clock-cells = <0>;
 883                         clock-output-names = "mmc0";
 884                 };
 885                 ssp_clk: ssp_clk@e6150248 {
 886                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 887                         reg = <0 0xe6150248 0 4>;
 888                         clocks = <&pll1_div2_clk>;
 889                         #clock-cells = <0>;
 890                         clock-output-names = "ssp";
 891                 };
 892                 ssprs_clk: ssprs_clk@e615024c {
 893                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 894                         reg = <0 0xe615024c 0 4>;
 895                         clocks = <&pll1_div2_clk>;
 896                         #clock-cells = <0>;
 897                         clock-output-names = "ssprs";
 898                 };
 899
 900                 /* Fixed factor clocks */
 901                 pll1_div2_clk: pll1_div2_clk {
 902                         compatible = "fixed-factor-clock";
 903                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 904                         #clock-cells = <0>;
 905                         clock-div = <2>;
 906                         clock-mult = <1>;
 907                         clock-output-names = "pll1_div2";
 908                 };
 909                 zg_clk: zg_clk {
 910                         compatible = "fixed-factor-clock";
 911                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 912                         #clock-cells = <0>;
 913                         clock-div = <3>;
 914                         clock-mult = <1>;
 915                         clock-output-names = "zg";
 916                 };
 917                 zx_clk: zx_clk {
 918                         compatible = "fixed-factor-clock";
 919                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 920                         #clock-cells = <0>;
 921                         clock-div = <3>;
 922                         clock-mult = <1>;
 923                         clock-output-names = "zx";
 924                 };
 925                 zs_clk: zs_clk {
 926                         compatible = "fixed-factor-clock";
 927                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 928                         #clock-cells = <0>;
 929                         clock-div = <6>;
 930                         clock-mult = <1>;
 931                         clock-output-names = "zs";
 932                 };
 933                 hp_clk: hp_clk {
 934                         compatible = "fixed-factor-clock";
 935                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 936                         #clock-cells = <0>;
 937                         clock-div = <12>;
 938                         clock-mult = <1>;
 939                         clock-output-names = "hp";
 940                 };
 941                 i_clk: i_clk {
 942                         compatible = "fixed-factor-clock";
 943                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 944                         #clock-cells = <0>;
 945                         clock-div = <2>;
 946                         clock-mult = <1>;
 947                         clock-output-names = "i";
 948                 };
 949                 b_clk: b_clk {
 950                         compatible = "fixed-factor-clock";
 951                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 952                         #clock-cells = <0>;
 953                         clock-div = <12>;
 954                         clock-mult = <1>;
 955                         clock-output-names = "b";
 956                 };
 957                 p_clk: p_clk {
 958                         compatible = "fixed-factor-clock";
 959                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 960                         #clock-cells = <0>;
 961                         clock-div = <24>;
 962                         clock-mult = <1>;
 963                         clock-output-names = "p";
 964                 };
 965                 cl_clk: cl_clk {
 966                         compatible = "fixed-factor-clock";
 967                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 968                         #clock-cells = <0>;
 969                         clock-div = <48>;
 970                         clock-mult = <1>;
 971                         clock-output-names = "cl";
 972                 };
 973                 m2_clk: m2_clk {
 974                         compatible = "fixed-factor-clock";
 975                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 976                         #clock-cells = <0>;
 977                         clock-div = <8>;
 978                         clock-mult = <1>;
 979                         clock-output-names = "m2";
 980                 };
 981                 imp_clk: imp_clk {
 982                         compatible = "fixed-factor-clock";
 983                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 984                         #clock-cells = <0>;
 985                         clock-div = <4>;
 986                         clock-mult = <1>;
 987                         clock-output-names = "imp";
 988                 };
 989                 rclk_clk: rclk_clk {
 990                         compatible = "fixed-factor-clock";
 991                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 992                         #clock-cells = <0>;
 993                         clock-div = <(48 * 1024)>;
 994                         clock-mult = <1>;
 995                         clock-output-names = "rclk";
 996                 };
 997                 oscclk_clk: oscclk_clk {
 998                         compatible = "fixed-factor-clock";
 999                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1000                         #clock-cells = <0>;
1001                         clock-div = <(12 * 1024)>;
1002                         clock-mult = <1>;
1003                         clock-output-names = "oscclk";
1004                 };
1005                 zb3_clk: zb3_clk {
1006                         compatible = "fixed-factor-clock";
1007                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1008                         #clock-cells = <0>;
1009                         clock-div = <4>;
1010                         clock-mult = <1>;
1011                         clock-output-names = "zb3";
1012                 };
1013                 zb3d2_clk: zb3d2_clk {
1014                         compatible = "fixed-factor-clock";
1015                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1016                         #clock-cells = <0>;
1017                         clock-div = <8>;
1018                         clock-mult = <1>;
1019                         clock-output-names = "zb3d2";
1020                 };
1021                 ddr_clk: ddr_clk {
1022                         compatible = "fixed-factor-clock";
1023                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1024                         #clock-cells = <0>;
1025                         clock-div = <8>;
1026                         clock-mult = <1>;
1027                         clock-output-names = "ddr";
1028                 };
1029                 mp_clk: mp_clk {
1030                         compatible = "fixed-factor-clock";
1031                         clocks = <&pll1_div2_clk>;
1032                         #clock-cells = <0>;
1033                         clock-div = <15>;
1034                         clock-mult = <1>;
1035                         clock-output-names = "mp";
1036                 };
1037                 cp_clk: cp_clk {
1038                         compatible = "fixed-factor-clock";
1039                         clocks = <&extal_clk>;
1040                         #clock-cells = <0>;
1041                         clock-div = <2>;
1042                         clock-mult = <1>;
1043                         clock-output-names = "cp";
1044                 };
1045
1046                 /* Gate clocks */
1047                 mstp0_clks: mstp0_clks@e6150130 {
1048                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1049                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1050                         clocks = <&mp_clk>;
1051                         #clock-cells = <1>;
1052                         renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
1053                         clock-output-names = "msiof0";
1054                 };
1055                 mstp1_clks: mstp1_clks@e6150134 {
1056                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1057                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
1058                         clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
1059                                  <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1060                                  <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
1061                                  <&zs_clk>;
1062                         #clock-cells = <1>;
1063                         renesas,clock-indices = <
1064                                 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
1065                                 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
1066                                 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
1067                                 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
1068                                 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
1069                                 R8A7791_CLK_VSP1_S
1070                         >;
1071                         clock-output-names =
1072                                 "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
1073                                 "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
1074                                 "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
1075                 };
1076                 mstp2_clks: mstp2_clks@e6150138 {
1077                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1078                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1079                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
1080                                  <&mp_clk>, <&mp_clk>, <&mp_clk>,
1081                                  <&zs_clk>, <&zs_clk>;
1082                         #clock-cells = <1>;
1083                         renesas,clock-indices = <
1084                                 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
1085                                 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
1086                                 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
1087                                 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
1088                         >;
1089                         clock-output-names =
1090                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
1091                                 "scifb1", "msiof1", "scifb2",
1092                                 "sys-dmac1", "sys-dmac0";
1093                 };
1094                 mstp3_clks: mstp3_clks@e615013c {
1095                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1096                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1097                         clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
1098                                  <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
1099                         #clock-cells = <1>;
1100                         renesas,clock-indices = <
1101                                 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
1102                                 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
1103                                 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
1104                         >;
1105                         clock-output-names =
1106                                 "tpu0", "sdhi2", "sdhi1", "sdhi0",
1107                                 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1";
1108                 };
1109                 mstp5_clks: mstp5_clks@e6150144 {
1110                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1111                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1112                         clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>;
1113                         #clock-cells = <1>;
1114                         renesas,clock-indices = <R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
1115                                                  R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
1116                         clock-output-names = "audmac0", "audmac1", "thermal", "pwm";
1117                 };
1118                 mstp7_clks: mstp7_clks@e615014c {
1119                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1120                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1121                         clocks = <&mp_clk>,  <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
1122                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1123                                  <&zx_clk>, <&zx_clk>, <&zx_clk>;
1124                         #clock-cells = <1>;
1125                         renesas,clock-indices = <
1126                                 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
1127                                 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
1128                                 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
1129                                 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
1130                                 R8A7791_CLK_LVDS0
1131                         >;
1132                         clock-output-names =
1133                                 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
1134                                 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
1135                 };
1136                 mstp8_clks: mstp8_clks@e6150990 {
1137                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1138                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
1139                         clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
1140                                  <&zs_clk>;
1141                         #clock-cells = <1>;
1142                         renesas,clock-indices = <
1143                                 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
1144                                 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
1145                         >;
1146                         clock-output-names =
1147                                 "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
1148                 };
1149                 mstp9_clks: mstp9_clks@e6150994 {
1150                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1151                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
1152                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1153                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1154                                  <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
1155                                  <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1156                                  <&hp_clk>, <&hp_clk>;
1157                         #clock-cells = <1>;
1158                         renesas,clock-indices = <
1159                                 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
1160                                 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
1161                                 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
1162                                 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
1163                                 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
1164                         >;
1165                         clock-output-names =
1166                                 "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1167                                 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
1168                                 "i2c1", "i2c0";
1169                 };
1170                 mstp10_clks: mstp10_clks@e6150998 {
1171                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1172                         reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1173                         clocks = <&p_clk>,
1174                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1175                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1176                                 <&p_clk>,
1177                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1178                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1179                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1180                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1181                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1182                                 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
1183
1184                         #clock-cells = <1>;
1185                         clock-indices = <
1186                                 R8A7791_CLK_SSI_ALL
1187                                 R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
1188                                 R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
1189                                 R8A7791_CLK_SCU_ALL
1190                                 R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
1191                                 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
1192                                 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
1193                         >;
1194                         clock-output-names =
1195                                 "ssi-all",
1196                                 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1197                                 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1198                                 "scu-all",
1199                                 "scu-dvc1", "scu-dvc0",
1200                                 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1201                                 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1202                 };
1203                 mstp11_clks: mstp11_clks@e615099c {
1204                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1205                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1206                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1207                         #clock-cells = <1>;
1208                         renesas,clock-indices = <
1209                                 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
1210                         >;
1211                         clock-output-names = "scifa3", "scifa4", "scifa5";
1212                 };
1213         };
1214
1215         qspi: spi@e6b10000 {
1216                 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
1217                 reg = <0 0xe6b10000 0 0x2c>;
1218                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
1219                 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
1220                 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1221                 dma-names = "tx", "rx";
1222                 num-cs = <1>;
1223                 #address-cells = <1>;
1224                 #size-cells = <0>;
1225                 status = "disabled";
1226         };
1227
1228         msiof0: spi@e6e20000 {
1229                 compatible = "renesas,msiof-r8a7791";
1230                 reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
1231                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
1232                 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
1233                 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1234                 dma-names = "tx", "rx";
1235                 #address-cells = <1>;
1236                 #size-cells = <0>;
1237                 status = "disabled";
1238         };
1239
1240         msiof1: spi@e6e10000 {
1241                 compatible = "renesas,msiof-r8a7791";
1242                 reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
1243                 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
1244                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
1245                 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1246                 dma-names = "tx", "rx";
1247                 #address-cells = <1>;
1248                 #size-cells = <0>;
1249                 status = "disabled";
1250         };
1251
1252         msiof2: spi@e6e00000 {
1253                 compatible = "renesas,msiof-r8a7791";
1254                 reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
1255                 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
1256                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
1257                 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1258                 dma-names = "tx", "rx";
1259                 #address-cells = <1>;
1260                 #size-cells = <0>;
1261                 status = "disabled";
1262         };
1263
1264         xhci: usb@ee000000 {
1265                 compatible = "renesas,xhci-r8a7791";
1266                 reg = <0 0xee000000 0 0xc00>;
1267                 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
1268                 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
1269                 phys = <&usb2 1>;
1270                 phy-names = "usb";
1271                 status = "disabled";
1272         };
1273
1274         pci0: pci@ee090000 {
1275                 compatible = "renesas,pci-r8a7791";
1276                 device_type = "pci";
1277                 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1278                 reg = <0 0xee090000 0 0xc00>,
1279                       <0 0xee080000 0 0x1100>;
1280                 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1281                 status = "disabled";
1282
1283                 bus-range = <0 0>;
1284                 #address-cells = <3>;
1285                 #size-cells = <2>;
1286                 #interrupt-cells = <1>;
1287                 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1288                 interrupt-map-mask = <0xff00 0 0 0x7>;
1289                 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1290                                  0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1291                                  0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
1292
1293                 usb@0,1 {
1294                         reg = <0x800 0 0 0 0>;
1295                         device_type = "pci";
1296                         phys = <&usb0 0>;
1297                         phy-names = "usb";
1298                 };
1299
1300                 usb@0,2 {
1301                         reg = <0x1000 0 0 0 0>;
1302                         device_type = "pci";
1303                         phys = <&usb0 0>;
1304                         phy-names = "usb";
1305                 };
1306         };
1307
1308         pci1: pci@ee0d0000 {
1309                 compatible = "renesas,pci-r8a7791";
1310                 device_type = "pci";
1311                 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1312                 reg = <0 0xee0d0000 0 0xc00>,
1313                       <0 0xee0c0000 0 0x1100>;
1314                 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
1315                 status = "disabled";
1316
1317                 bus-range = <1 1>;
1318                 #address-cells = <3>;
1319                 #size-cells = <2>;
1320                 #interrupt-cells = <1>;
1321                 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1322                 interrupt-map-mask = <0xff00 0 0 0x7>;
1323                 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1324                                  0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1325                                  0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1326
1327                 usb@0,1 {
1328                         reg = <0x800 0 0 0 0>;
1329                         device_type = "pci";
1330                         phys = <&usb2 0>;
1331                         phy-names = "usb";
1332                 };
1333
1334                 usb@0,2 {
1335                         reg = <0x1000 0 0 0 0>;
1336                         device_type = "pci";
1337                         phys = <&usb2 0>;
1338                         phy-names = "usb";
1339                 };
1340         };
1341
1342         pciec: pcie@fe000000 {
1343                 compatible = "renesas,pcie-r8a7791";
1344                 reg = <0 0xfe000000 0 0x80000>;
1345                 #address-cells = <3>;
1346                 #size-cells = <2>;
1347                 bus-range = <0x00 0xff>;
1348                 device_type = "pci";
1349                 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1350                           0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1351                           0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1352                           0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1353                 /* Map all possible DDR as inbound ranges */
1354                 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1355                               0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
1356                 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1357                              <0 117 IRQ_TYPE_LEVEL_HIGH>,
1358                              <0 118 IRQ_TYPE_LEVEL_HIGH>;
1359                 #interrupt-cells = <1>;
1360                 interrupt-map-mask = <0 0 0 0>;
1361                 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1362                 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
1363                 clock-names = "pcie", "pcie_bus";
1364                 status = "disabled";
1365         };
1366
1367         rcar_sound: rcar_sound@ec500000 {
1368                 #sound-dai-cells = <1>;
1369                 compatible =  "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
1370                 reg =   <0 0xec500000 0 0x1000>, /* SCU */
1371                         <0 0xec5a0000 0 0x100>,  /* ADG */
1372                         <0 0xec540000 0 0x1000>, /* SSIU */
1373                         <0 0xec541000 0 0x1280>; /* SSI */
1374                 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1375                         <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
1376                         <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
1377                         <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
1378                         <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
1379                         <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
1380                         <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
1381                         <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
1382                         <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
1383                         <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
1384                         <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
1385                         <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
1386                         <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1387                 clock-names = "ssi-all",
1388                                 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1389                                 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1390                                 "src.9", "src.8", "src.7", "src.6", "src.5",
1391                                 "src.4", "src.3", "src.2", "src.1", "src.0",
1392                                 "dvc.0", "dvc.1",
1393                                 "clk_a", "clk_b", "clk_c", "clk_i";
1394
1395                 status = "disabled";
1396
1397                 rcar_sound,dvc {
1398                         dvc0: dvc@0 { };
1399                         dvc1: dvc@1 { };
1400                 };
1401
1402                 rcar_sound,src {
1403                         src0: src@0 { };
1404                         src1: src@1 { };
1405                         src2: src@2 { };
1406                         src3: src@3 { };
1407                         src4: src@4 { };
1408                         src5: src@5 { };
1409                         src6: src@6 { };
1410                         src7: src@7 { };
1411                         src8: src@8 { };
1412                         src9: src@9 { };
1413                 };
1414
1415                 rcar_sound,ssi {
1416                         ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
1417                         ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
1418                         ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
1419                         ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
1420                         ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
1421                         ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
1422                         ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
1423                         ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
1424                         ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
1425                         ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
1426                 };
1427         };
1428 };