2 * Device Tree Source for the r8a7791 SoC
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 #include <dt-bindings/clock/r8a7791-clock.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/interrupt-controller/irq.h>
18 compatible = "renesas,r8a7791";
19 interrupt-parent = <&gic>;
38 compatible = "arm,cortex-a15";
40 clock-frequency = <1300000000>;
45 compatible = "arm,cortex-a15";
47 clock-frequency = <1300000000>;
51 gic: interrupt-controller@f1001000 {
52 compatible = "arm,cortex-a15-gic";
53 #interrupt-cells = <3>;
56 reg = <0 0xf1001000 0 0x1000>,
57 <0 0xf1002000 0 0x1000>,
58 <0 0xf1004000 0 0x2000>,
59 <0 0xf1006000 0 0x2000>;
60 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
63 gpio0: gpio@e6050000 {
64 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
65 reg = <0 0xe6050000 0 0x50>;
66 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
69 gpio-ranges = <&pfc 0 0 32>;
70 #interrupt-cells = <2>;
74 gpio1: gpio@e6051000 {
75 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
76 reg = <0 0xe6051000 0 0x50>;
77 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
80 gpio-ranges = <&pfc 0 32 32>;
81 #interrupt-cells = <2>;
85 gpio2: gpio@e6052000 {
86 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
87 reg = <0 0xe6052000 0 0x50>;
88 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
91 gpio-ranges = <&pfc 0 64 32>;
92 #interrupt-cells = <2>;
96 gpio3: gpio@e6053000 {
97 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
98 reg = <0 0xe6053000 0 0x50>;
99 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
102 gpio-ranges = <&pfc 0 96 32>;
103 #interrupt-cells = <2>;
104 interrupt-controller;
107 gpio4: gpio@e6054000 {
108 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
109 reg = <0 0xe6054000 0 0x50>;
110 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
113 gpio-ranges = <&pfc 0 128 32>;
114 #interrupt-cells = <2>;
115 interrupt-controller;
118 gpio5: gpio@e6055000 {
119 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
120 reg = <0 0xe6055000 0 0x50>;
121 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
124 gpio-ranges = <&pfc 0 160 32>;
125 #interrupt-cells = <2>;
126 interrupt-controller;
129 gpio6: gpio@e6055400 {
130 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
131 reg = <0 0xe6055400 0 0x50>;
132 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
135 gpio-ranges = <&pfc 0 192 32>;
136 #interrupt-cells = <2>;
137 interrupt-controller;
140 gpio7: gpio@e6055800 {
141 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
142 reg = <0 0xe6055800 0 0x50>;
143 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
146 gpio-ranges = <&pfc 0 224 26>;
147 #interrupt-cells = <2>;
148 interrupt-controller;
152 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
153 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
154 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
155 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
159 compatible = "arm,armv7-timer";
160 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
161 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
162 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
163 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
166 irqc0: interrupt-controller@e61c0000 {
167 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
168 #interrupt-cells = <2>;
169 interrupt-controller;
170 reg = <0 0xe61c0000 0 0x200>;
171 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
172 <0 1 IRQ_TYPE_LEVEL_HIGH>,
173 <0 2 IRQ_TYPE_LEVEL_HIGH>,
174 <0 3 IRQ_TYPE_LEVEL_HIGH>,
175 <0 12 IRQ_TYPE_LEVEL_HIGH>,
176 <0 13 IRQ_TYPE_LEVEL_HIGH>,
177 <0 14 IRQ_TYPE_LEVEL_HIGH>,
178 <0 15 IRQ_TYPE_LEVEL_HIGH>,
179 <0 16 IRQ_TYPE_LEVEL_HIGH>,
180 <0 17 IRQ_TYPE_LEVEL_HIGH>;
184 #address-cells = <1>;
186 compatible = "renesas,i2c-r8a7791";
187 reg = <0 0xe6508000 0 0x40>;
188 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
194 #address-cells = <1>;
196 compatible = "renesas,i2c-r8a7791";
197 reg = <0 0xe6518000 0 0x40>;
198 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
199 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
204 #address-cells = <1>;
206 compatible = "renesas,i2c-r8a7791";
207 reg = <0 0xe6530000 0 0x40>;
208 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
214 #address-cells = <1>;
216 compatible = "renesas,i2c-r8a7791";
217 reg = <0 0xe6540000 0 0x40>;
218 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
224 #address-cells = <1>;
226 compatible = "renesas,i2c-r8a7791";
227 reg = <0 0xe6520000 0 0x40>;
228 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
234 #address-cells = <1>;
236 compatible = "renesas,i2c-r8a7791";
237 reg = <0 0xe6528000 0 0x40>;
238 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
244 compatible = "renesas,pfc-r8a7791";
245 reg = <0 0xe6060000 0 0x250>;
246 #gpio-range-cells = <3>;
249 scifa0: serial@e6c40000 {
250 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
251 reg = <0 0xe6c40000 0 64>;
252 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
254 clock-names = "sci_ick";
258 scifa1: serial@e6c50000 {
259 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
260 reg = <0 0xe6c50000 0 64>;
261 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
263 clock-names = "sci_ick";
267 scifa2: serial@e6c60000 {
268 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
269 reg = <0 0xe6c60000 0 64>;
270 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
272 clock-names = "sci_ick";
276 scifa3: serial@e6c70000 {
277 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
278 reg = <0 0xe6c70000 0 64>;
279 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
281 clock-names = "sci_ick";
285 scifa4: serial@e6c78000 {
286 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
287 reg = <0 0xe6c78000 0 64>;
288 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
290 clock-names = "sci_ick";
294 scifa5: serial@e6c80000 {
295 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
296 reg = <0 0xe6c80000 0 64>;
297 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
299 clock-names = "sci_ick";
303 scifb0: serial@e6c20000 {
304 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
305 reg = <0 0xe6c20000 0 64>;
306 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
308 clock-names = "sci_ick";
312 scifb1: serial@e6c30000 {
313 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
314 reg = <0 0xe6c30000 0 64>;
315 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
317 clock-names = "sci_ick";
321 scifb2: serial@e6ce0000 {
322 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
323 reg = <0 0xe6ce0000 0 64>;
324 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
326 clock-names = "sci_ick";
330 scif0: serial@e6e60000 {
331 compatible = "renesas,scif-r8a7791", "renesas,scif";
332 reg = <0 0xe6e60000 0 64>;
333 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
335 clock-names = "sci_ick";
339 scif1: serial@e6e68000 {
340 compatible = "renesas,scif-r8a7791", "renesas,scif";
341 reg = <0 0xe6e68000 0 64>;
342 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
344 clock-names = "sci_ick";
348 scif2: serial@e6e58000 {
349 compatible = "renesas,scif-r8a7791", "renesas,scif";
350 reg = <0 0xe6e58000 0 64>;
351 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
353 clock-names = "sci_ick";
357 scif3: serial@e6ea8000 {
358 compatible = "renesas,scif-r8a7791", "renesas,scif";
359 reg = <0 0xe6ea8000 0 64>;
360 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
362 clock-names = "sci_ick";
366 scif4: serial@e6ee0000 {
367 compatible = "renesas,scif-r8a7791", "renesas,scif";
368 reg = <0 0xe6ee0000 0 64>;
369 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
371 clock-names = "sci_ick";
375 scif5: serial@e6ee8000 {
376 compatible = "renesas,scif-r8a7791", "renesas,scif";
377 reg = <0 0xe6ee8000 0 64>;
378 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
380 clock-names = "sci_ick";
384 hscif0: serial@e62c0000 {
385 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
386 reg = <0 0xe62c0000 0 96>;
387 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
388 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
389 clock-names = "sci_ick";
393 hscif1: serial@e62c8000 {
394 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
395 reg = <0 0xe62c8000 0 96>;
396 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
398 clock-names = "sci_ick";
402 hscif2: serial@e62d0000 {
403 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
404 reg = <0 0xe62d0000 0 96>;
405 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
407 clock-names = "sci_ick";
411 ether: ethernet@ee700000 {
412 compatible = "renesas,ether-r8a7791";
413 reg = <0 0xee700000 0 0x400>;
414 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
417 #address-cells = <1>;
422 sata0: sata@ee300000 {
423 compatible = "renesas,sata-r8a7791";
424 reg = <0 0xee300000 0 0x2000>;
425 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
430 sata1: sata@ee500000 {
431 compatible = "renesas,sata-r8a7791";
432 reg = <0 0xee500000 0 0x2000>;
433 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
439 #address-cells = <2>;
443 /* External root clock */
444 extal_clk: extal_clk {
445 compatible = "fixed-clock";
447 /* This value must be overriden by the board. */
448 clock-frequency = <0>;
449 clock-output-names = "extal";
452 /* Special CPG clocks */
453 cpg_clocks: cpg_clocks@e6150000 {
454 compatible = "renesas,r8a7791-cpg-clocks",
455 "renesas,rcar-gen2-cpg-clocks";
456 reg = <0 0xe6150000 0 0x1000>;
457 clocks = <&extal_clk>;
459 clock-output-names = "main", "pll0", "pll1", "pll3",
460 "lb", "qspi", "sdh", "sd0", "z";
463 /* Variable factor clocks */
464 sd1_clk: sd2_clk@e6150078 {
465 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
466 reg = <0 0xe6150078 0 4>;
467 clocks = <&pll1_div2_clk>;
469 clock-output-names = "sd1";
471 sd2_clk: sd3_clk@e615007c {
472 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
473 reg = <0 0xe615007c 0 4>;
474 clocks = <&pll1_div2_clk>;
476 clock-output-names = "sd2";
478 mmc0_clk: mmc0_clk@e6150240 {
479 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
480 reg = <0 0xe6150240 0 4>;
481 clocks = <&pll1_div2_clk>;
483 clock-output-names = "mmc0";
485 ssp_clk: ssp_clk@e6150248 {
486 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
487 reg = <0 0xe6150248 0 4>;
488 clocks = <&pll1_div2_clk>;
490 clock-output-names = "ssp";
492 ssprs_clk: ssprs_clk@e615024c {
493 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
494 reg = <0 0xe615024c 0 4>;
495 clocks = <&pll1_div2_clk>;
497 clock-output-names = "ssprs";
500 /* Fixed factor clocks */
501 pll1_div2_clk: pll1_div2_clk {
502 compatible = "fixed-factor-clock";
503 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
507 clock-output-names = "pll1_div2";
510 compatible = "fixed-factor-clock";
511 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
515 clock-output-names = "zg";
518 compatible = "fixed-factor-clock";
519 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
523 clock-output-names = "zx";
526 compatible = "fixed-factor-clock";
527 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
531 clock-output-names = "zs";
534 compatible = "fixed-factor-clock";
535 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
539 clock-output-names = "hp";
542 compatible = "fixed-factor-clock";
543 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
547 clock-output-names = "i";
550 compatible = "fixed-factor-clock";
551 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
555 clock-output-names = "b";
558 compatible = "fixed-factor-clock";
559 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
563 clock-output-names = "p";
566 compatible = "fixed-factor-clock";
567 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
571 clock-output-names = "cl";
574 compatible = "fixed-factor-clock";
575 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
579 clock-output-names = "m2";
582 compatible = "fixed-factor-clock";
583 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
587 clock-output-names = "imp";
590 compatible = "fixed-factor-clock";
591 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
593 clock-div = <(48 * 1024)>;
595 clock-output-names = "rclk";
597 oscclk_clk: oscclk_clk {
598 compatible = "fixed-factor-clock";
599 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
601 clock-div = <(12 * 1024)>;
603 clock-output-names = "oscclk";
606 compatible = "fixed-factor-clock";
607 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
611 clock-output-names = "zb3";
613 zb3d2_clk: zb3d2_clk {
614 compatible = "fixed-factor-clock";
615 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
619 clock-output-names = "zb3d2";
622 compatible = "fixed-factor-clock";
623 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
627 clock-output-names = "ddr";
630 compatible = "fixed-factor-clock";
631 clocks = <&pll1_div2_clk>;
635 clock-output-names = "mp";
638 compatible = "fixed-factor-clock";
639 clocks = <&extal_clk>;
643 clock-output-names = "cp";
647 mstp0_clks: mstp0_clks@e6150130 {
648 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
649 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
652 renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
653 clock-output-names = "msiof0";
655 mstp1_clks: mstp1_clks@e6150134 {
656 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
657 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
658 clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
659 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
661 renesas,clock-indices = <
662 R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
663 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
664 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_SY
667 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
668 "vsp1-du0", "vsp1-sy";
670 mstp2_clks: mstp2_clks@e6150138 {
671 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
672 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
673 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
674 <&mp_clk>, <&mp_clk>, <&mp_clk>;
676 renesas,clock-indices = <
677 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
678 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
679 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
682 "scifa2", "scifa1", "scifa0", "misof2", "scifb0",
683 "scifb1", "msiof1", "scifb2";
685 mstp3_clks: mstp3_clks@e615013c {
686 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
687 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
688 clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>,
689 <&cpg_clocks R8A7791_CLK_SD0>, <&mmc0_clk>, <&rclk_clk>;
691 renesas,clock-indices = <
692 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1
693 R8A7791_CLK_SDHI0 R8A7791_CLK_MMCIF0 R8A7791_CLK_CMT1
696 "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", "cmt1";
698 mstp5_clks: mstp5_clks@e6150144 {
699 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
700 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
701 clocks = <&extal_clk>, <&p_clk>;
703 renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
704 clock-output-names = "thermal", "pwm";
706 mstp7_clks: mstp7_clks@e615014c {
707 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
708 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
709 clocks = <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
710 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
711 <&zx_clk>, <&zx_clk>, <&zx_clk>;
713 renesas,clock-indices = <
714 R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
715 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
716 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
717 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
721 "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
722 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
724 mstp8_clks: mstp8_clks@e6150990 {
725 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
726 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
727 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
730 renesas,clock-indices = <
731 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
732 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
735 "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
737 mstp9_clks: mstp9_clks@e6150994 {
738 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
739 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
740 clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>,
741 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
744 renesas,clock-indices = <
745 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD
746 R8A7791_CLK_I2C4 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3
747 R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
750 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3",
751 "i2c2", "i2c1", "i2c0";
753 mstp11_clks: mstp11_clks@e615099c {
754 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
755 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
756 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
758 renesas,clock-indices = <
759 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
761 clock-output-names = "scifa3", "scifa4", "scifa5";
766 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
767 reg = <0 0xe6b10000 0 0x2c>;
768 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
769 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
771 #address-cells = <1>;