arch/arm/boot/dts/r8a7791.dtsi

   1 /*
   2  * Device Tree Source for the r8a7791 SoC
   3  *
   4  * Copyright (C) 2013 Renesas Electronics Corporation
   5  * Copyright (C) 2013 Renesas Solutions Corp.
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a7791-clock.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "renesas,r8a7791";
  18         interrupt-parent = <&gic>;
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25
  26                 cpu0: cpu@0 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a15";
  29                         reg = <0>;
  30                         clock-frequency = <1300000000>;
  31                 };
  32
  33                 cpu1: cpu@1 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a15";
  36                         reg = <1>;
  37                         clock-frequency = <1300000000>;
  38                 };
  39         };
  40
  41         gic: interrupt-controller@f1001000 {
  42                 compatible = "arm,cortex-a15-gic";
  43                 #interrupt-cells = <3>;
  44                 #address-cells = <0>;
  45                 interrupt-controller;
  46                 reg = <0 0xf1001000 0 0x1000>,
  47                         <0 0xf1002000 0 0x1000>,
  48                         <0 0xf1004000 0 0x2000>,
  49                         <0 0xf1006000 0 0x2000>;
  50                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  51         };
  52
  53         gpio0: gpio@e6050000 {
  54                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  55                 reg = <0 0xe6050000 0 0x50>;
  56                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
  57                 #gpio-cells = <2>;
  58                 gpio-controller;
  59                 gpio-ranges = <&pfc 0 0 32>;
  60                 #interrupt-cells = <2>;
  61                 interrupt-controller;
  62         };
  63
  64         gpio1: gpio@e6051000 {
  65                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  66                 reg = <0 0xe6051000 0 0x50>;
  67                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
  68                 #gpio-cells = <2>;
  69                 gpio-controller;
  70                 gpio-ranges = <&pfc 0 32 32>;
  71                 #interrupt-cells = <2>;
  72                 interrupt-controller;
  73         };
  74
  75         gpio2: gpio@e6052000 {
  76                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  77                 reg = <0 0xe6052000 0 0x50>;
  78                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
  79                 #gpio-cells = <2>;
  80                 gpio-controller;
  81                 gpio-ranges = <&pfc 0 64 32>;
  82                 #interrupt-cells = <2>;
  83                 interrupt-controller;
  84         };
  85
  86         gpio3: gpio@e6053000 {
  87                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  88                 reg = <0 0xe6053000 0 0x50>;
  89                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
  90                 #gpio-cells = <2>;
  91                 gpio-controller;
  92                 gpio-ranges = <&pfc 0 96 32>;
  93                 #interrupt-cells = <2>;
  94                 interrupt-controller;
  95         };
  96
  97         gpio4: gpio@e6054000 {
  98                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
  99                 reg = <0 0xe6054000 0 0x50>;
 100                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 101                 #gpio-cells = <2>;
 102                 gpio-controller;
 103                 gpio-ranges = <&pfc 0 128 32>;
 104                 #interrupt-cells = <2>;
 105                 interrupt-controller;
 106         };
 107
 108         gpio5: gpio@e6055000 {
 109                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 110                 reg = <0 0xe6055000 0 0x50>;
 111                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 112                 #gpio-cells = <2>;
 113                 gpio-controller;
 114                 gpio-ranges = <&pfc 0 160 32>;
 115                 #interrupt-cells = <2>;
 116                 interrupt-controller;
 117         };
 118
 119         gpio6: gpio@e6055400 {
 120                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 121                 reg = <0 0xe6055400 0 0x50>;
 122                 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 123                 #gpio-cells = <2>;
 124                 gpio-controller;
 125                 gpio-ranges = <&pfc 0 192 32>;
 126                 #interrupt-cells = <2>;
 127                 interrupt-controller;
 128         };
 129
 130         gpio7: gpio@e6055800 {
 131                 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
 132                 reg = <0 0xe6055800 0 0x50>;
 133                 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 134                 #gpio-cells = <2>;
 135                 gpio-controller;
 136                 gpio-ranges = <&pfc 0 224 26>;
 137                 #interrupt-cells = <2>;
 138                 interrupt-controller;
 139         };
 140
 141         thermal@e61f0000 {
 142                 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
 143                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 144                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 145                 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
 146         };
 147
 148         timer {
 149                 compatible = "arm,armv7-timer";
 150                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 151                              <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 152                              <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 153                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 154         };
 155
 156         irqc0: interrupt-controller@e61c0000 {
 157                 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
 158                 #interrupt-cells = <2>;
 159                 interrupt-controller;
 160                 reg = <0 0xe61c0000 0 0x200>;
 161                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 162                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 163                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 164                              <0 3 IRQ_TYPE_LEVEL_HIGH>,
 165                              <0 12 IRQ_TYPE_LEVEL_HIGH>,
 166                              <0 13 IRQ_TYPE_LEVEL_HIGH>,
 167                              <0 14 IRQ_TYPE_LEVEL_HIGH>,
 168                              <0 15 IRQ_TYPE_LEVEL_HIGH>,
 169                              <0 16 IRQ_TYPE_LEVEL_HIGH>,
 170                              <0 17 IRQ_TYPE_LEVEL_HIGH>;
 171         };
 172
 173         pfc: pfc@e6060000 {
 174                 compatible = "renesas,pfc-r8a7791";
 175                 reg = <0 0xe6060000 0 0x250>;
 176                 #gpio-range-cells = <3>;
 177         };
 178
 179         scifa0: serial@e6c40000 {
 180                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 181                 reg = <0 0xe6c40000 0 64>;
 182                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 183                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
 184                 clock-names = "sci_ick";
 185                 status = "disabled";
 186         };
 187
 188         scifa1: serial@e6c50000 {
 189                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 190                 reg = <0 0xe6c50000 0 64>;
 191                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 192                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
 193                 clock-names = "sci_ick";
 194                 status = "disabled";
 195         };
 196
 197         scifa2: serial@e6c60000 {
 198                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 199                 reg = <0 0xe6c60000 0 64>;
 200                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 201                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
 202                 clock-names = "sci_ick";
 203                 status = "disabled";
 204         };
 205
 206         scifa3: serial@e6c70000 {
 207                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 208                 reg = <0 0xe6c70000 0 64>;
 209                 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 210                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
 211                 clock-names = "sci_ick";
 212                 status = "disabled";
 213         };
 214
 215         scifa4: serial@e6c78000 {
 216                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 217                 reg = <0 0xe6c78000 0 64>;
 218                 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 219                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
 220                 clock-names = "sci_ick";
 221                 status = "disabled";
 222         };
 223
 224         scifa5: serial@e6c80000 {
 225                 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
 226                 reg = <0 0xe6c80000 0 64>;
 227                 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 228                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
 229                 clock-names = "sci_ick";
 230                 status = "disabled";
 231         };
 232
 233         scifb0: serial@e6c20000 {
 234                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 235                 reg = <0 0xe6c20000 0 64>;
 236                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 237                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
 238                 clock-names = "sci_ick";
 239                 status = "disabled";
 240         };
 241
 242         scifb1: serial@e6c30000 {
 243                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 244                 reg = <0 0xe6c30000 0 64>;
 245                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 246                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
 247                 clock-names = "sci_ick";
 248                 status = "disabled";
 249         };
 250
 251         scifb2: serial@e6ce0000 {
 252                 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
 253                 reg = <0 0xe6ce0000 0 64>;
 254                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 255                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
 256                 clock-names = "sci_ick";
 257                 status = "disabled";
 258         };
 259
 260         scif0: serial@e6e60000 {
 261                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 262                 reg = <0 0xe6e60000 0 64>;
 263                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 264                 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
 265                 clock-names = "sci_ick";
 266                 status = "disabled";
 267         };
 268
 269         scif1: serial@e6e68000 {
 270                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 271                 reg = <0 0xe6e68000 0 64>;
 272                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 273                 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
 274                 clock-names = "sci_ick";
 275                 status = "disabled";
 276         };
 277
 278         scif2: serial@e6e58000 {
 279                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 280                 reg = <0 0xe6e58000 0 64>;
 281                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 282                 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
 283                 clock-names = "sci_ick";
 284                 status = "disabled";
 285         };
 286
 287         scif3: serial@e6ea8000 {
 288                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 289                 reg = <0 0xe6ea8000 0 64>;
 290                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 291                 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
 292                 clock-names = "sci_ick";
 293                 status = "disabled";
 294         };
 295
 296         scif4: serial@e6ee0000 {
 297                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 298                 reg = <0 0xe6ee0000 0 64>;
 299                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 300                 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
 301                 clock-names = "sci_ick";
 302                 status = "disabled";
 303         };
 304
 305         scif5: serial@e6ee8000 {
 306                 compatible = "renesas,scif-r8a7791", "renesas,scif";
 307                 reg = <0 0xe6ee8000 0 64>;
 308                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 309                 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
 310                 clock-names = "sci_ick";
 311                 status = "disabled";
 312         };
 313
 314         hscif0: serial@e62c0000 {
 315                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 316                 reg = <0 0xe62c0000 0 96>;
 317                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 318                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
 319                 clock-names = "sci_ick";
 320                 status = "disabled";
 321         };
 322
 323         hscif1: serial@e62c8000 {
 324                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 325                 reg = <0 0xe62c8000 0 96>;
 326                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 327                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
 328                 clock-names = "sci_ick";
 329                 status = "disabled";
 330         };
 331
 332         hscif2: serial@e62d0000 {
 333                 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
 334                 reg = <0 0xe62d0000 0 96>;
 335                 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
 336                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
 337                 clock-names = "sci_ick";
 338                 status = "disabled";
 339         };
 340
 341         sata0: sata@ee300000 {
 342                 compatible = "renesas,sata-r8a7791";
 343                 reg = <0 0xee300000 0 0x2000>;
 344                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 345                 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
 346                 status = "disabled";
 347         };
 348
 349         sata1: sata@ee500000 {
 350                 compatible = "renesas,sata-r8a7791";
 351                 reg = <0 0xee500000 0 0x2000>;
 352                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 353                 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
 354                 status = "disabled";
 355         };
 356
 357         clocks {
 358                 #address-cells = <2>;
 359                 #size-cells = <2>;
 360                 ranges;
 361
 362                 /* External root clock */
 363                 extal_clk: extal_clk {
 364                         compatible = "fixed-clock";
 365                         #clock-cells = <0>;
 366                         /* This value must be overriden by the board. */
 367                         clock-frequency = <0>;
 368                         clock-output-names = "extal";
 369                 };
 370
 371                 /* Special CPG clocks */
 372                 cpg_clocks: cpg_clocks@e6150000 {
 373                         compatible = "renesas,r8a7791-cpg-clocks",
 374                                      "renesas,rcar-gen2-cpg-clocks";
 375                         reg = <0 0xe6150000 0 0x1000>;
 376                         clocks = <&extal_clk>;
 377                         #clock-cells = <1>;
 378                         clock-output-names = "main", "pll0", "pll1", "pll3",
 379                                              "lb", "qspi", "sdh", "sd0", "z";
 380                 };
 381
 382                 /* Variable factor clocks */
 383                 sd1_clk: sd2_clk@e6150078 {
 384                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 385                         reg = <0 0xe6150078 0 4>;
 386                         clocks = <&pll1_div2_clk>;
 387                         #clock-cells = <0>;
 388                         clock-output-names = "sd1";
 389                 };
 390                 sd2_clk: sd3_clk@e615007c {
 391                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 392                         reg = <0 0xe615007c 0 4>;
 393                         clocks = <&pll1_div2_clk>;
 394                         #clock-cells = <0>;
 395                         clock-output-names = "sd2";
 396                 };
 397                 mmc0_clk: mmc0_clk@e6150240 {
 398                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 399                         reg = <0 0xe6150240 0 4>;
 400                         clocks = <&pll1_div2_clk>;
 401                         #clock-cells = <0>;
 402                         clock-output-names = "mmc0";
 403                 };
 404                 ssp_clk: ssp_clk@e6150248 {
 405                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 406                         reg = <0 0xe6150248 0 4>;
 407                         clocks = <&pll1_div2_clk>;
 408                         #clock-cells = <0>;
 409                         clock-output-names = "ssp";
 410                 };
 411                 ssprs_clk: ssprs_clk@e615024c {
 412                         compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
 413                         reg = <0 0xe615024c 0 4>;
 414                         clocks = <&pll1_div2_clk>;
 415                         #clock-cells = <0>;
 416                         clock-output-names = "ssprs";
 417                 };
 418
 419                 /* Fixed factor clocks */
 420                 pll1_div2_clk: pll1_div2_clk {
 421                         compatible = "fixed-factor-clock";
 422                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 423                         #clock-cells = <0>;
 424                         clock-div = <2>;
 425                         clock-mult = <1>;
 426                         clock-output-names = "pll1_div2";
 427                 };
 428                 zg_clk: zg_clk {
 429                         compatible = "fixed-factor-clock";
 430                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 431                         #clock-cells = <0>;
 432                         clock-div = <3>;
 433                         clock-mult = <1>;
 434                         clock-output-names = "zg";
 435                 };
 436                 zx_clk: zx_clk {
 437                         compatible = "fixed-factor-clock";
 438                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 439                         #clock-cells = <0>;
 440                         clock-div = <3>;
 441                         clock-mult = <1>;
 442                         clock-output-names = "zx";
 443                 };
 444                 zs_clk: zs_clk {
 445                         compatible = "fixed-factor-clock";
 446                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 447                         #clock-cells = <0>;
 448                         clock-div = <6>;
 449                         clock-mult = <1>;
 450                         clock-output-names = "zs";
 451                 };
 452                 hp_clk: hp_clk {
 453                         compatible = "fixed-factor-clock";
 454                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 455                         #clock-cells = <0>;
 456                         clock-div = <12>;
 457                         clock-mult = <1>;
 458                         clock-output-names = "hp";
 459                 };
 460                 i_clk: i_clk {
 461                         compatible = "fixed-factor-clock";
 462                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 463                         #clock-cells = <0>;
 464                         clock-div = <2>;
 465                         clock-mult = <1>;
 466                         clock-output-names = "i";
 467                 };
 468                 b_clk: b_clk {
 469                         compatible = "fixed-factor-clock";
 470                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 471                         #clock-cells = <0>;
 472                         clock-div = <12>;
 473                         clock-mult = <1>;
 474                         clock-output-names = "b";
 475                 };
 476                 p_clk: p_clk {
 477                         compatible = "fixed-factor-clock";
 478                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 479                         #clock-cells = <0>;
 480                         clock-div = <24>;
 481                         clock-mult = <1>;
 482                         clock-output-names = "p";
 483                 };
 484                 cl_clk: cl_clk {
 485                         compatible = "fixed-factor-clock";
 486                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 487                         #clock-cells = <0>;
 488                         clock-div = <48>;
 489                         clock-mult = <1>;
 490                         clock-output-names = "cl";
 491                 };
 492                 m2_clk: m2_clk {
 493                         compatible = "fixed-factor-clock";
 494                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 495                         #clock-cells = <0>;
 496                         clock-div = <8>;
 497                         clock-mult = <1>;
 498                         clock-output-names = "m2";
 499                 };
 500                 imp_clk: imp_clk {
 501                         compatible = "fixed-factor-clock";
 502                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 503                         #clock-cells = <0>;
 504                         clock-div = <4>;
 505                         clock-mult = <1>;
 506                         clock-output-names = "imp";
 507                 };
 508                 rclk_clk: rclk_clk {
 509                         compatible = "fixed-factor-clock";
 510                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 511                         #clock-cells = <0>;
 512                         clock-div = <(48 * 1024)>;
 513                         clock-mult = <1>;
 514                         clock-output-names = "rclk";
 515                 };
 516                 oscclk_clk: oscclk_clk {
 517                         compatible = "fixed-factor-clock";
 518                         clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
 519                         #clock-cells = <0>;
 520                         clock-div = <(12 * 1024)>;
 521                         clock-mult = <1>;
 522                         clock-output-names = "oscclk";
 523                 };
 524                 zb3_clk: zb3_clk {
 525                         compatible = "fixed-factor-clock";
 526                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 527                         #clock-cells = <0>;
 528                         clock-div = <4>;
 529                         clock-mult = <1>;
 530                         clock-output-names = "zb3";
 531                 };
 532                 zb3d2_clk: zb3d2_clk {
 533                         compatible = "fixed-factor-clock";
 534                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 535                         #clock-cells = <0>;
 536                         clock-div = <8>;
 537                         clock-mult = <1>;
 538                         clock-output-names = "zb3d2";
 539                 };
 540                 ddr_clk: ddr_clk {
 541                         compatible = "fixed-factor-clock";
 542                         clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
 543                         #clock-cells = <0>;
 544                         clock-div = <8>;
 545                         clock-mult = <1>;
 546                         clock-output-names = "ddr";
 547                 };
 548                 mp_clk: mp_clk {
 549                         compatible = "fixed-factor-clock";
 550                         clocks = <&pll1_div2_clk>;
 551                         #clock-cells = <0>;
 552                         clock-div = <15>;
 553                         clock-mult = <1>;
 554                         clock-output-names = "mp";
 555                 };
 556                 cp_clk: cp_clk {
 557                         compatible = "fixed-factor-clock";
 558                         clocks = <&extal_clk>;
 559                         #clock-cells = <0>;
 560                         clock-div = <2>;
 561                         clock-mult = <1>;
 562                         clock-output-names = "cp";
 563                 };
 564
 565                 /* Gate clocks */
 566                 mstp0_clks: mstp0_clks@e6150130 {
 567                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 568                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
 569                         clocks = <&mp_clk>;
 570                         #clock-cells = <1>;
 571                         renesas,clock-indices = <R8A7791_CLK_MSIOF0>;
 572                         clock-output-names = "msiof0";
 573                 };
 574                 mstp1_clks: mstp1_clks@e6150134 {
 575                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 576                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 577                         clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
 578                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
 579                         #clock-cells = <1>;
 580                         renesas,clock-indices = <
 581                                 R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
 582                                 R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
 583                                 R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_SY
 584                         >;
 585                         clock-output-names =
 586                                 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
 587                                 "vsp1-du0", "vsp1-sy";
 588                 };
 589                 mstp2_clks: mstp2_clks@e6150138 {
 590                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 591                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 592                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 593                                  <&mp_clk>, <&mp_clk>, <&mp_clk>;
 594                         #clock-cells = <1>;
 595                         renesas,clock-indices = <
 596                                 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
 597                                 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
 598                                 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
 599                         >;
 600                         clock-output-names =
 601                                 "scifa2", "scifa1", "scifa0", "misof2", "scifb0",
 602                                 "scifb1", "msiof1", "scifb2";
 603                 };
 604                 mstp3_clks: mstp3_clks@e615013c {
 605                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 606                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 607                         clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>,
 608                                 <&cpg_clocks R8A7791_CLK_SD0>, <&mmc0_clk>, <&rclk_clk>;
 609                         #clock-cells = <1>;
 610                         renesas,clock-indices = <
 611                                 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1
 612                                 R8A7791_CLK_SDHI0 R8A7791_CLK_MMCIF0 R8A7791_CLK_CMT1
 613                         >;
 614                         clock-output-names =
 615                                 "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", "cmt1";
 616                 };
 617                 mstp5_clks: mstp5_clks@e6150144 {
 618                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 619                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
 620                         clocks = <&extal_clk>, <&p_clk>;
 621                         #clock-cells = <1>;
 622                         renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>;
 623                         clock-output-names = "thermal", "pwm";
 624                 };
 625                 mstp7_clks: mstp7_clks@e615014c {
 626                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 627                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 628                         clocks = <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
 629                                  <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 630                                  <&zx_clk>, <&zx_clk>, <&zx_clk>;
 631                         #clock-cells = <1>;
 632                         renesas,clock-indices = <
 633                                 R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
 634                                 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
 635                                 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
 636                                 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
 637                                 R8A7791_CLK_LVDS0
 638                         >;
 639                         clock-output-names =
 640                                 "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
 641                                 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
 642                 };
 643                 mstp8_clks: mstp8_clks@e6150990 {
 644                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 645                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 646                         clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>, <&zs_clk>,
 647                                  <&zs_clk>;
 648                         #clock-cells = <1>;
 649                         renesas,clock-indices = <
 650                                 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
 651                                 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
 652                         >;
 653                         clock-output-names =
 654                                 "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
 655                 };
 656                 mstp9_clks: mstp9_clks@e6150994 {
 657                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 658                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 659                         clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>,
 660                                  <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
 661                                  <&p_clk>;
 662                         #clock-cells = <1>;
 663                         renesas,clock-indices = <
 664                                 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD
 665                                 R8A7791_CLK_I2C4 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3
 666                                 R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
 667                         >;
 668                         clock-output-names =
 669                                 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3",
 670                                 "i2c2", "i2c1", "i2c0";
 671                 };
 672                 mstp11_clks: mstp11_clks@e615099c {
 673                         compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 674                         reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
 675                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
 676                         #clock-cells = <1>;
 677                         renesas,clock-indices = <
 678                                 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
 679                         >;
 680                         clock-output-names = "scifa3", "scifa4", "scifa5";
 681                 };
 682         };
 683
 684         spi: spi@e6b10000 {
 685                 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
 686                 reg = <0 0xe6b10000 0 0x2c>;
 687                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
 688                 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
 689                 num-cs = <1>;
 690                 #address-cells = <1>;
 691                 #size-cells = <0>;
 692                 status = "disabled";
 693         };
 694 };