arch/arm/boot/dts/r8a7790.dtsi

   1 /*
   2  * Device Tree Source for the r8a7790 SoC
   3  *
   4  * Copyright (C) 2013 Renesas Solutions Corp.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/clock/r8a7790-clock.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/interrupt-controller/irq.h>
  14
  15 / {
  16         compatible = "renesas,r8a7790";
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu0: cpu@0 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a15";
  28                         reg = <0>;
  29                         clock-frequency = <1300000000>;
  30                 };
  31
  32                 cpu1: cpu@1 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a15";
  35                         reg = <1>;
  36                         clock-frequency = <1300000000>;
  37                 };
  38
  39                 cpu2: cpu@2 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a15";
  42                         reg = <2>;
  43                         clock-frequency = <1300000000>;
  44                 };
  45
  46                 cpu3: cpu@3 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a15";
  49                         reg = <3>;
  50                         clock-frequency = <1300000000>;
  51                 };
  52
  53                 cpu4: cpu@4 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a7";
  56                         reg = <0x100>;
  57                         clock-frequency = <780000000>;
  58                 };
  59
  60                 cpu5: cpu@5 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a7";
  63                         reg = <0x101>;
  64                         clock-frequency = <780000000>;
  65                 };
  66
  67                 cpu6: cpu@6 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a7";
  70                         reg = <0x102>;
  71                         clock-frequency = <780000000>;
  72                 };
  73
  74                 cpu7: cpu@7 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a7";
  77                         reg = <0x103>;
  78                         clock-frequency = <780000000>;
  79                 };
  80         };
  81
  82         gic: interrupt-controller@f1001000 {
  83                 compatible = "arm,cortex-a15-gic";
  84                 #interrupt-cells = <3>;
  85                 #address-cells = <0>;
  86                 interrupt-controller;
  87                 reg = <0 0xf1001000 0 0x1000>,
  88                         <0 0xf1002000 0 0x1000>,
  89                         <0 0xf1004000 0 0x2000>,
  90                         <0 0xf1006000 0 0x2000>;
  91                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  92         };
  93
  94         gpio0: gpio@e6050000 {
  95                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
  96                 reg = <0 0xe6050000 0 0x50>;
  97                 interrupt-parent = <&gic>;
  98                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
  99                 #gpio-cells = <2>;
 100                 gpio-controller;
 101                 gpio-ranges = <&pfc 0 0 32>;
 102                 #interrupt-cells = <2>;
 103                 interrupt-controller;
 104         };
 105
 106         gpio1: gpio@e6051000 {
 107                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 108                 reg = <0 0xe6051000 0 0x50>;
 109                 interrupt-parent = <&gic>;
 110                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 111                 #gpio-cells = <2>;
 112                 gpio-controller;
 113                 gpio-ranges = <&pfc 0 32 32>;
 114                 #interrupt-cells = <2>;
 115                 interrupt-controller;
 116         };
 117
 118         gpio2: gpio@e6052000 {
 119                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 120                 reg = <0 0xe6052000 0 0x50>;
 121                 interrupt-parent = <&gic>;
 122                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 123                 #gpio-cells = <2>;
 124                 gpio-controller;
 125                 gpio-ranges = <&pfc 0 64 32>;
 126                 #interrupt-cells = <2>;
 127                 interrupt-controller;
 128         };
 129
 130         gpio3: gpio@e6053000 {
 131                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 132                 reg = <0 0xe6053000 0 0x50>;
 133                 interrupt-parent = <&gic>;
 134                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 135                 #gpio-cells = <2>;
 136                 gpio-controller;
 137                 gpio-ranges = <&pfc 0 96 32>;
 138                 #interrupt-cells = <2>;
 139                 interrupt-controller;
 140         };
 141
 142         gpio4: gpio@e6054000 {
 143                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 144                 reg = <0 0xe6054000 0 0x50>;
 145                 interrupt-parent = <&gic>;
 146                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 147                 #gpio-cells = <2>;
 148                 gpio-controller;
 149                 gpio-ranges = <&pfc 0 128 32>;
 150                 #interrupt-cells = <2>;
 151                 interrupt-controller;
 152         };
 153
 154         gpio5: gpio@e6055000 {
 155                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 156                 reg = <0 0xe6055000 0 0x50>;
 157                 interrupt-parent = <&gic>;
 158                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 159                 #gpio-cells = <2>;
 160                 gpio-controller;
 161                 gpio-ranges = <&pfc 0 160 32>;
 162                 #interrupt-cells = <2>;
 163                 interrupt-controller;
 164         };
 165
 166         thermal@e61f0000 {
 167                 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
 168                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 169                 interrupt-parent = <&gic>;
 170                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 171                 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
 172         };
 173
 174         timer {
 175                 compatible = "arm,armv7-timer";
 176                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 177                              <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 178                              <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 179                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 180         };
 181
 182         irqc0: interrupt-controller@e61c0000 {
 183                 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
 184                 #interrupt-cells = <2>;
 185                 interrupt-controller;
 186                 reg = <0 0xe61c0000 0 0x200>;
 187                 interrupt-parent = <&gic>;
 188                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 189                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 190                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 191                              <0 3 IRQ_TYPE_LEVEL_HIGH>;
 192         };
 193
 194         i2c0: i2c@e6508000 {
 195                 #address-cells = <1>;
 196                 #size-cells = <0>;
 197                 compatible = "renesas,i2c-r8a7790";
 198                 reg = <0 0xe6508000 0 0x40>;
 199                 interrupt-parent = <&gic>;
 200                 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 201                 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
 202                 status = "disabled";
 203         };
 204
 205         i2c1: i2c@e6518000 {
 206                 #address-cells = <1>;
 207                 #size-cells = <0>;
 208                 compatible = "renesas,i2c-r8a7790";
 209                 reg = <0 0xe6518000 0 0x40>;
 210                 interrupt-parent = <&gic>;
 211                 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 212                 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
 213                 status = "disabled";
 214         };
 215
 216         i2c2: i2c@e6530000 {
 217                 #address-cells = <1>;
 218                 #size-cells = <0>;
 219                 compatible = "renesas,i2c-r8a7790";
 220                 reg = <0 0xe6530000 0 0x40>;
 221                 interrupt-parent = <&gic>;
 222                 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 223                 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
 224                 status = "disabled";
 225         };
 226
 227         i2c3: i2c@e6540000 {
 228                 #address-cells = <1>;
 229                 #size-cells = <0>;
 230                 compatible = "renesas,i2c-r8a7790";
 231                 reg = <0 0xe6540000 0 0x40>;
 232                 interrupt-parent = <&gic>;
 233                 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 234                 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
 235                 status = "disabled";
 236         };
 237
 238         mmcif0: mmcif@ee200000 {
 239                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 240                 reg = <0 0xee200000 0 0x80>;
 241                 interrupt-parent = <&gic>;
 242                 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
 243                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
 244                 reg-io-width = <4>;
 245                 status = "disabled";
 246         };
 247
 248         mmcif1: mmc@ee220000 {
 249                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 250                 reg = <0 0xee220000 0 0x80>;
 251                 interrupt-parent = <&gic>;
 252                 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
 253                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
 254                 reg-io-width = <4>;
 255                 status = "disabled";
 256         };
 257
 258         pfc: pfc@e6060000 {
 259                 compatible = "renesas,pfc-r8a7790";
 260                 reg = <0 0xe6060000 0 0x250>;
 261         };
 262
 263         sdhi0: sd@ee100000 {
 264                 compatible = "renesas,sdhi-r8a7790";
 265                 reg = <0 0xee100000 0 0x200>;
 266                 interrupt-parent = <&gic>;
 267                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 268                 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
 269                 cap-sd-highspeed;
 270                 status = "disabled";
 271         };
 272
 273         sdhi1: sd@ee120000 {
 274                 compatible = "renesas,sdhi-r8a7790";
 275                 reg = <0 0xee120000 0 0x200>;
 276                 interrupt-parent = <&gic>;
 277                 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
 278                 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
 279                 cap-sd-highspeed;
 280                 status = "disabled";
 281         };
 282
 283         sdhi2: sd@ee140000 {
 284                 compatible = "renesas,sdhi-r8a7790";
 285                 reg = <0 0xee140000 0 0x100>;
 286                 interrupt-parent = <&gic>;
 287                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 288                 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
 289                 cap-sd-highspeed;
 290                 status = "disabled";
 291         };
 292
 293         sdhi3: sd@ee160000 {
 294                 compatible = "renesas,sdhi-r8a7790";
 295                 reg = <0 0xee160000 0 0x100>;
 296                 interrupt-parent = <&gic>;
 297                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 298                 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
 299                 cap-sd-highspeed;
 300                 status = "disabled";
 301         };
 302
 303         scifa0: serial@e6c40000 {
 304                 compatible = "renesas,scifa-r8a7790", "renesas,scifa-generic";
 305                 reg = <0 0xe6c40000 0 64>;
 306                 interrupt-parent = <&gic>;
 307                 interrupts = <0 144 4>;
 308                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
 309                 clock-names = "sci_ick";
 310                 status = "disabled";
 311         };
 312
 313         scifa1: serial@e6c50000 {
 314                 compatible = "renesas,scifa-r8a7790", "renesas,scifa-generic";
 315                 interrupt-parent = <&gic>;
 316                 reg = <0 0xe6c50000 0 64>;
 317                 interrupts = <0 145 4>;
 318                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
 319                 clock-names = "sci_ick";
 320                 status = "disabled";
 321         };
 322
 323         scifa2: serial@e6c60000 {
 324                 compatible = "renesas,scifa-r8a7790", "renesas,scifa-generic";
 325                 interrupt-parent = <&gic>;
 326                 reg = <0 0xe6c60000 0 64>;
 327                 interrupts = <0 151 4>;
 328                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
 329                 clock-names = "sci_ick";
 330                 status = "disabled";
 331         };
 332
 333         scifb0: serial@e6c20000 {
 334                 compatible = "renesas,scifb-r8a7790", "renesas,scifb-generic";
 335                 interrupt-parent = <&gic>;
 336                 reg = <0 0xe6c20000 0 64>;
 337                 interrupts = <0 148 4>;
 338                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
 339                 clock-names = "sci_ick";
 340                 status = "disabled";
 341         };
 342
 343         scifb1: serial@e6c30000 {
 344                 compatible = "renesas,scifb-r8a7790", "renesas,scifb-generic";
 345                 interrupt-parent = <&gic>;
 346                 reg = <0 0xe6c30000 0 64>;
 347                 interrupts = <0 149 4>;
 348                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
 349                 clock-names = "sci_ick";
 350                 status = "disabled";
 351         };
 352
 353         scifb2: serial@e6ce0000 {
 354                 compatible = "renesas,scifb-r8a7790", "renesas,scifb-generic";
 355                 interrupt-parent = <&gic>;
 356                 reg = <0 0xe6ce0000 0 64>;
 357                 interrupts = <0 150 4>;
 358                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
 359                 clock-names = "sci_ick";
 360                 status = "disabled";
 361         };
 362
 363         scif0: serial@e6e60000 {
 364                 compatible = "renesas,scif-r8a7790", "renesas,scif-generic";
 365                 interrupt-parent = <&gic>;
 366                 reg = <0 0xe6e60000 0 64>;
 367                 interrupts = <0 152 4>;
 368                 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
 369                 clock-names = "sci_ick";
 370                 status = "disabled";
 371         };
 372
 373         scif1: serial@e6e68000 {
 374                 compatible = "renesas,scif-r8a7790", "renesas,scif-generic";
 375                 interrupt-parent = <&gic>;
 376                 reg = <0 0xe6e68000 0 64>;
 377                 interrupts = <0 153 4>;
 378                 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
 379                 clock-names = "sci_ick";
 380                 status = "disabled";
 381         };
 382
 383         hscif0: serial@e62c0000 {
 384                 compatible = "renesas,hscif-r8a7790", "renesas,hscif-generic";
 385                 interrupt-parent = <&gic>;
 386                 reg = <0 0xe62c0000 0 96>;
 387                 interrupts = <0 154 4>;
 388                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
 389                 clock-names = "sci_ick";
 390                 status = "disabled";
 391         };
 392
 393         hscif1: serial@e62c8000 {
 394                 compatible = "renesas,hscif-r8a7790", "renesas,hscif-generic";
 395                 interrupt-parent = <&gic>;
 396                 reg = <0 0xe62c8000 0 96>;
 397                 interrupts = <0 155 4>;
 398                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
 399                 clock-names = "sci_ick";
 400                 status = "disabled";
 401         };
 402
 403         clocks {
 404                 #address-cells = <2>;
 405                 #size-cells = <2>;
 406                 ranges;
 407
 408                 /* External root clock */
 409                 extal_clk: extal_clk {
 410                         compatible = "fixed-clock";
 411                         #clock-cells = <0>;
 412                         /* This value must be overriden by the board. */
 413                         clock-frequency = <0>;
 414                         clock-output-names = "extal";
 415                 };
 416
 417                 /* Special CPG clocks */
 418                 cpg_clocks: cpg_clocks@e6150000 {
 419                         compatible = "renesas,r8a7790-cpg-clocks",
 420                                      "renesas,rcar-gen2-cpg-clocks";
 421                         reg = <0 0xe6150000 0 0x1000>;
 422                         clocks = <&extal_clk>;
 423                         #clock-cells = <1>;
 424                         clock-output-names = "main", "pll0", "pll1", "pll3",
 425                                              "lb", "qspi", "sdh", "sd0", "sd1",
 426                                              "z";
 427                 };
 428
 429                 /* Variable factor clocks */
 430                 sd2_clk: sd2_clk@e6150078 {
 431                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 432                         reg = <0 0xe6150078 0 4>;
 433                         clocks = <&pll1_div2_clk>;
 434                         #clock-cells = <0>;
 435                         clock-output-names = "sd2";
 436                 };
 437                 sd3_clk: sd3_clk@e615007c {
 438                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 439                         reg = <0 0xe615007c 0 4>;
 440                         clocks = <&pll1_div2_clk>;
 441                         #clock-cells = <0>;
 442                         clock-output-names = "sd3";
 443                 };
 444                 mmc0_clk: mmc0_clk@e6150240 {
 445                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 446                         reg = <0 0xe6150240 0 4>;
 447                         clocks = <&pll1_div2_clk>;
 448                         #clock-cells = <0>;
 449                         clock-output-names = "mmc0";
 450                 };
 451                 mmc1_clk: mmc1_clk@e6150244 {
 452                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 453                         reg = <0 0xe6150244 0 4>;
 454                         clocks = <&pll1_div2_clk>;
 455                         #clock-cells = <0>;
 456                         clock-output-names = "mmc1";
 457                 };
 458                 ssp_clk: ssp_clk@e6150248 {
 459                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 460                         reg = <0 0xe6150248 0 4>;
 461                         clocks = <&pll1_div2_clk>;
 462                         #clock-cells = <0>;
 463                         clock-output-names = "ssp";
 464                 };
 465                 ssprs_clk: ssprs_clk@e615024c {
 466                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 467                         reg = <0 0xe615024c 0 4>;
 468                         clocks = <&pll1_div2_clk>;
 469                         #clock-cells = <0>;
 470                         clock-output-names = "ssprs";
 471                 };
 472
 473                 /* Fixed factor clocks */
 474                 pll1_div2_clk: pll1_div2_clk {
 475                         compatible = "fixed-factor-clock";
 476                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 477                         #clock-cells = <0>;
 478                         clock-div = <2>;
 479                         clock-mult = <1>;
 480                         clock-output-names = "pll1_div2";
 481                 };
 482                 z2_clk: z2_clk {
 483                         compatible = "fixed-factor-clock";
 484                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 485                         #clock-cells = <0>;
 486                         clock-div = <2>;
 487                         clock-mult = <1>;
 488                         clock-output-names = "z2";
 489                 };
 490                 zg_clk: zg_clk {
 491                         compatible = "fixed-factor-clock";
 492                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 493                         #clock-cells = <0>;
 494                         clock-div = <3>;
 495                         clock-mult = <1>;
 496                         clock-output-names = "zg";
 497                 };
 498                 zx_clk: zx_clk {
 499                         compatible = "fixed-factor-clock";
 500                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 501                         #clock-cells = <0>;
 502                         clock-div = <3>;
 503                         clock-mult = <1>;
 504                         clock-output-names = "zx";
 505                 };
 506                 zs_clk: zs_clk {
 507                         compatible = "fixed-factor-clock";
 508                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 509                         #clock-cells = <0>;
 510                         clock-div = <6>;
 511                         clock-mult = <1>;
 512                         clock-output-names = "zs";
 513                 };
 514                 hp_clk: hp_clk {
 515                         compatible = "fixed-factor-clock";
 516                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 517                         #clock-cells = <0>;
 518                         clock-div = <12>;
 519                         clock-mult = <1>;
 520                         clock-output-names = "hp";
 521                 };
 522                 i_clk: i_clk {
 523                         compatible = "fixed-factor-clock";
 524                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 525                         #clock-cells = <0>;
 526                         clock-div = <2>;
 527                         clock-mult = <1>;
 528                         clock-output-names = "i";
 529                 };
 530                 b_clk: b_clk {
 531                         compatible = "fixed-factor-clock";
 532                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 533                         #clock-cells = <0>;
 534                         clock-div = <12>;
 535                         clock-mult = <1>;
 536                         clock-output-names = "b";
 537                 };
 538                 p_clk: p_clk {
 539                         compatible = "fixed-factor-clock";
 540                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 541                         #clock-cells = <0>;
 542                         clock-div = <24>;
 543                         clock-mult = <1>;
 544                         clock-output-names = "p";
 545                 };
 546                 cl_clk: cl_clk {
 547                         compatible = "fixed-factor-clock";
 548                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 549                         #clock-cells = <0>;
 550                         clock-div = <48>;
 551                         clock-mult = <1>;
 552                         clock-output-names = "cl";
 553                 };
 554                 m2_clk: m2_clk {
 555                         compatible = "fixed-factor-clock";
 556                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 557                         #clock-cells = <0>;
 558                         clock-div = <8>;
 559                         clock-mult = <1>;
 560                         clock-output-names = "m2";
 561                 };
 562                 imp_clk: imp_clk {
 563                         compatible = "fixed-factor-clock";
 564                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 565                         #clock-cells = <0>;
 566                         clock-div = <4>;
 567                         clock-mult = <1>;
 568                         clock-output-names = "imp";
 569                 };
 570                 rclk_clk: rclk_clk {
 571                         compatible = "fixed-factor-clock";
 572                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 573                         #clock-cells = <0>;
 574                         clock-div = <(48 * 1024)>;
 575                         clock-mult = <1>;
 576                         clock-output-names = "rclk";
 577                 };
 578                 oscclk_clk: oscclk_clk {
 579                         compatible = "fixed-factor-clock";
 580                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 581                         #clock-cells = <0>;
 582                         clock-div = <(12 * 1024)>;
 583                         clock-mult = <1>;
 584                         clock-output-names = "oscclk";
 585                 };
 586                 zb3_clk: zb3_clk {
 587                         compatible = "fixed-factor-clock";
 588                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 589                         #clock-cells = <0>;
 590                         clock-div = <4>;
 591                         clock-mult = <1>;
 592                         clock-output-names = "zb3";
 593                 };
 594                 zb3d2_clk: zb3d2_clk {
 595                         compatible = "fixed-factor-clock";
 596                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 597                         #clock-cells = <0>;
 598                         clock-div = <8>;
 599                         clock-mult = <1>;
 600                         clock-output-names = "zb3d2";
 601                 };
 602                 ddr_clk: ddr_clk {
 603                         compatible = "fixed-factor-clock";
 604                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 605                         #clock-cells = <0>;
 606                         clock-div = <8>;
 607                         clock-mult = <1>;
 608                         clock-output-names = "ddr";
 609                 };
 610                 mp_clk: mp_clk {
 611                         compatible = "fixed-factor-clock";
 612                         clocks = <&pll1_div2_clk>;
 613                         #clock-cells = <0>;
 614                         clock-div = <15>;
 615                         clock-mult = <1>;
 616                         clock-output-names = "mp";
 617                 };
 618                 cp_clk: cp_clk {
 619                         compatible = "fixed-factor-clock";
 620                         clocks = <&extal_clk>;
 621                         #clock-cells = <0>;
 622                         clock-div = <2>;
 623                         clock-mult = <1>;
 624                         clock-output-names = "cp";
 625                 };
 626
 627                 /* Gate clocks */
 628                 mstp0_clks: mstp0_clks@e6150130 {
 629                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 630                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
 631                         clocks = <&mp_clk>;
 632                         #clock-cells = <1>;
 633                         renesas,clock-indices = <R8A7790_CLK_MSIOF0>;
 634                         clock-output-names = "msiof0";
 635                 };
 636                 mstp1_clks: mstp1_clks@e6150134 {
 637                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 638                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 639                         clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
 640                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
 641                                  <&zs_clk>;
 642                         #clock-cells = <1>;
 643                         renesas,clock-indices = <
 644                                 R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
 645                                 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
 646                                 R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_RT R8A7790_CLK_VSP1_SY
 647                         >;
 648                         clock-output-names =
 649                                 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
 650                                 "vsp1-du0", "vsp1-rt", "vsp1-sy";
 651                 };
 652                 mstp2_clks: mstp2_clks@e6150138 {
 653                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 654                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 655                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 656                                  <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>;
 657                         #clock-cells = <1>;
 658                         renesas,clock-indices = <
 659                                 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
 660                                 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
 661                                 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
 662                         >;
 663                         clock-output-names =
 664                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
 665                                 "scifb1", "msiof1", "msiof3", "scifb2";
 666                 };
 667                 mstp3_clks: mstp3_clks@e615013c {
 668                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 669                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 670                         clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,
 671                                  <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,
 672                                  <&mmc0_clk>, <&rclk_clk>;
 673                         #clock-cells = <1>;
 674                         renesas,clock-indices = <
 675                                 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
 676                                 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
 677                                 R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1
 678                         >;
 679                         clock-output-names =
 680                                 "tpu0", "mmcif1", "sdhi3", "sdhi2",
 681                                 "sdhi1", "sdhi0", "mmcif0", "cmt1";
 682                 };
 683                 mstp5_clks: mstp5_clks@e6150144 {
 684                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 685                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
 686                         clocks = <&extal_clk>, <&p_clk>;
 687                         #clock-cells = <1>;
 688                         renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
 689                         clock-output-names = "thermal", "pwm";
 690                 };
 691                 mstp7_clks: mstp7_clks@e615014c {
 692                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 693                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 694                         clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
 695                                  <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
 696                                  <&zx_clk>;
 697                         #clock-cells = <1>;
 698                         renesas,clock-indices = <
 699                                 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
 700                                 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
 701                                 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
 702                                 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
 703                         >;
 704                         clock-output-names =
 705                                 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
 706                                 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
 707                 };
 708                 mstp8_clks: mstp8_clks@e6150990 {
 709                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 710                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 711                         clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>;
 712                         #clock-cells = <1>;
 713                         renesas,clock-indices = <
 714                                 R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1
 715                                 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER
 716                         >;
 717                         clock-output-names = "vin3", "vin2", "vin1", "vin0", "ether";
 718                 };
 719                 mstp9_clks: mstp9_clks@e6150994 {
 720                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 721                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 722                         clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>,
 723                                  <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
 724                         #clock-cells = <1>;
 725                         renesas,clock-indices = <
 726                                 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD
 727                                 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1
 728                                 R8A7790_CLK_I2C0
 729                         >;
 730                         clock-output-names =
 731                                 "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0";
 732                 };
 733         };
 734 };