2 * Device Tree Source for the r8a7790 SoC
4 * Copyright (C) 2013 Renesas Solutions Corp.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <dt-bindings/clock/r8a7790-clock.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
16 compatible = "renesas,r8a7790";
17 interrupt-parent = <&gic>;
27 compatible = "arm,cortex-a15";
29 clock-frequency = <1300000000>;
34 compatible = "arm,cortex-a15";
36 clock-frequency = <1300000000>;
41 compatible = "arm,cortex-a15";
43 clock-frequency = <1300000000>;
48 compatible = "arm,cortex-a15";
50 clock-frequency = <1300000000>;
55 compatible = "arm,cortex-a7";
57 clock-frequency = <780000000>;
62 compatible = "arm,cortex-a7";
64 clock-frequency = <780000000>;
69 compatible = "arm,cortex-a7";
71 clock-frequency = <780000000>;
76 compatible = "arm,cortex-a7";
78 clock-frequency = <780000000>;
82 gic: interrupt-controller@f1001000 {
83 compatible = "arm,cortex-a15-gic";
84 #interrupt-cells = <3>;
87 reg = <0 0xf1001000 0 0x1000>,
88 <0 0xf1002000 0 0x1000>,
89 <0 0xf1004000 0 0x2000>,
90 <0 0xf1006000 0 0x2000>;
91 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
94 gpio0: gpio@e6050000 {
95 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
96 reg = <0 0xe6050000 0 0x50>;
97 interrupt-parent = <&gic>;
98 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
101 gpio-ranges = <&pfc 0 0 32>;
102 #interrupt-cells = <2>;
103 interrupt-controller;
106 gpio1: gpio@e6051000 {
107 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
108 reg = <0 0xe6051000 0 0x50>;
109 interrupt-parent = <&gic>;
110 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
113 gpio-ranges = <&pfc 0 32 32>;
114 #interrupt-cells = <2>;
115 interrupt-controller;
118 gpio2: gpio@e6052000 {
119 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
120 reg = <0 0xe6052000 0 0x50>;
121 interrupt-parent = <&gic>;
122 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
125 gpio-ranges = <&pfc 0 64 32>;
126 #interrupt-cells = <2>;
127 interrupt-controller;
130 gpio3: gpio@e6053000 {
131 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
132 reg = <0 0xe6053000 0 0x50>;
133 interrupt-parent = <&gic>;
134 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
137 gpio-ranges = <&pfc 0 96 32>;
138 #interrupt-cells = <2>;
139 interrupt-controller;
142 gpio4: gpio@e6054000 {
143 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
144 reg = <0 0xe6054000 0 0x50>;
145 interrupt-parent = <&gic>;
146 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
149 gpio-ranges = <&pfc 0 128 32>;
150 #interrupt-cells = <2>;
151 interrupt-controller;
154 gpio5: gpio@e6055000 {
155 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
156 reg = <0 0xe6055000 0 0x50>;
157 interrupt-parent = <&gic>;
158 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
161 gpio-ranges = <&pfc 0 160 32>;
162 #interrupt-cells = <2>;
163 interrupt-controller;
167 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
168 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
169 interrupt-parent = <&gic>;
170 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
171 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
175 compatible = "arm,armv7-timer";
176 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
177 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
178 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
179 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
182 irqc0: interrupt-controller@e61c0000 {
183 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
184 #interrupt-cells = <2>;
185 interrupt-controller;
186 reg = <0 0xe61c0000 0 0x200>;
187 interrupt-parent = <&gic>;
188 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
189 <0 1 IRQ_TYPE_LEVEL_HIGH>,
190 <0 2 IRQ_TYPE_LEVEL_HIGH>,
191 <0 3 IRQ_TYPE_LEVEL_HIGH>;
195 #address-cells = <1>;
197 compatible = "renesas,i2c-r8a7790";
198 reg = <0 0xe6508000 0 0x40>;
199 interrupt-parent = <&gic>;
200 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
206 #address-cells = <1>;
208 compatible = "renesas,i2c-r8a7790";
209 reg = <0 0xe6518000 0 0x40>;
210 interrupt-parent = <&gic>;
211 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
217 #address-cells = <1>;
219 compatible = "renesas,i2c-r8a7790";
220 reg = <0 0xe6530000 0 0x40>;
221 interrupt-parent = <&gic>;
222 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
228 #address-cells = <1>;
230 compatible = "renesas,i2c-r8a7790";
231 reg = <0 0xe6540000 0 0x40>;
232 interrupt-parent = <&gic>;
233 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
238 mmcif0: mmcif@ee200000 {
239 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
240 reg = <0 0xee200000 0 0x80>;
241 interrupt-parent = <&gic>;
242 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
248 mmcif1: mmc@ee220000 {
249 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
250 reg = <0 0xee220000 0 0x80>;
251 interrupt-parent = <&gic>;
252 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
259 compatible = "renesas,pfc-r8a7790";
260 reg = <0 0xe6060000 0 0x250>;
264 compatible = "renesas,sdhi-r8a7790";
265 reg = <0 0xee100000 0 0x200>;
266 interrupt-parent = <&gic>;
267 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
274 compatible = "renesas,sdhi-r8a7790";
275 reg = <0 0xee120000 0 0x200>;
276 interrupt-parent = <&gic>;
277 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
278 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
284 compatible = "renesas,sdhi-r8a7790";
285 reg = <0 0xee140000 0 0x100>;
286 interrupt-parent = <&gic>;
287 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
294 compatible = "renesas,sdhi-r8a7790";
295 reg = <0 0xee160000 0 0x100>;
296 interrupt-parent = <&gic>;
297 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
303 scifa0: serial@e6c40000 {
304 compatible = "renesas,scifa-r8a7790", "renesas,scifa-generic";
305 reg = <0 0xe6c40000 0 64>;
306 interrupt-parent = <&gic>;
307 interrupts = <0 144 4>;
308 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
309 clock-names = "sci_ick";
313 scifa1: serial@e6c50000 {
314 compatible = "renesas,scifa-r8a7790", "renesas,scifa-generic";
315 interrupt-parent = <&gic>;
316 reg = <0 0xe6c50000 0 64>;
317 interrupts = <0 145 4>;
318 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
319 clock-names = "sci_ick";
323 scifa2: serial@e6c60000 {
324 compatible = "renesas,scifa-r8a7790", "renesas,scifa-generic";
325 interrupt-parent = <&gic>;
326 reg = <0 0xe6c60000 0 64>;
327 interrupts = <0 151 4>;
328 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
329 clock-names = "sci_ick";
333 scifb0: serial@e6c20000 {
334 compatible = "renesas,scifb-r8a7790", "renesas,scifb-generic";
335 interrupt-parent = <&gic>;
336 reg = <0 0xe6c20000 0 64>;
337 interrupts = <0 148 4>;
338 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
339 clock-names = "sci_ick";
343 scifb1: serial@e6c30000 {
344 compatible = "renesas,scifb-r8a7790", "renesas,scifb-generic";
345 interrupt-parent = <&gic>;
346 reg = <0 0xe6c30000 0 64>;
347 interrupts = <0 149 4>;
348 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
349 clock-names = "sci_ick";
353 scifb2: serial@e6ce0000 {
354 compatible = "renesas,scifb-r8a7790", "renesas,scifb-generic";
355 interrupt-parent = <&gic>;
356 reg = <0 0xe6ce0000 0 64>;
357 interrupts = <0 150 4>;
358 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
359 clock-names = "sci_ick";
363 scif0: serial@e6e60000 {
364 compatible = "renesas,scif-r8a7790", "renesas,scif-generic";
365 interrupt-parent = <&gic>;
366 reg = <0 0xe6e60000 0 64>;
367 interrupts = <0 152 4>;
368 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
369 clock-names = "sci_ick";
373 scif1: serial@e6e68000 {
374 compatible = "renesas,scif-r8a7790", "renesas,scif-generic";
375 interrupt-parent = <&gic>;
376 reg = <0 0xe6e68000 0 64>;
377 interrupts = <0 153 4>;
378 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
379 clock-names = "sci_ick";
383 hscif0: serial@e62c0000 {
384 compatible = "renesas,hscif-r8a7790", "renesas,hscif-generic";
385 interrupt-parent = <&gic>;
386 reg = <0 0xe62c0000 0 96>;
387 interrupts = <0 154 4>;
388 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
389 clock-names = "sci_ick";
393 hscif1: serial@e62c8000 {
394 compatible = "renesas,hscif-r8a7790", "renesas,hscif-generic";
395 interrupt-parent = <&gic>;
396 reg = <0 0xe62c8000 0 96>;
397 interrupts = <0 155 4>;
398 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
399 clock-names = "sci_ick";
403 sata0: sata@ee300000 {
404 compatible = "renesas,sata-r8a7790";
405 reg = <0 0xee300000 0 0x2000>;
406 interrupt-parent = <&gic>;
407 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
412 sata1: sata@ee500000 {
413 compatible = "renesas,sata-r8a7790";
414 reg = <0 0xee500000 0 0x2000>;
415 interrupt-parent = <&gic>;
416 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
422 #address-cells = <2>;
426 /* External root clock */
427 extal_clk: extal_clk {
428 compatible = "fixed-clock";
430 /* This value must be overriden by the board. */
431 clock-frequency = <0>;
432 clock-output-names = "extal";
435 /* Special CPG clocks */
436 cpg_clocks: cpg_clocks@e6150000 {
437 compatible = "renesas,r8a7790-cpg-clocks",
438 "renesas,rcar-gen2-cpg-clocks";
439 reg = <0 0xe6150000 0 0x1000>;
440 clocks = <&extal_clk>;
442 clock-output-names = "main", "pll0", "pll1", "pll3",
443 "lb", "qspi", "sdh", "sd0", "sd1",
447 /* Variable factor clocks */
448 sd2_clk: sd2_clk@e6150078 {
449 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
450 reg = <0 0xe6150078 0 4>;
451 clocks = <&pll1_div2_clk>;
453 clock-output-names = "sd2";
455 sd3_clk: sd3_clk@e615007c {
456 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
457 reg = <0 0xe615007c 0 4>;
458 clocks = <&pll1_div2_clk>;
460 clock-output-names = "sd3";
462 mmc0_clk: mmc0_clk@e6150240 {
463 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
464 reg = <0 0xe6150240 0 4>;
465 clocks = <&pll1_div2_clk>;
467 clock-output-names = "mmc0";
469 mmc1_clk: mmc1_clk@e6150244 {
470 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
471 reg = <0 0xe6150244 0 4>;
472 clocks = <&pll1_div2_clk>;
474 clock-output-names = "mmc1";
476 ssp_clk: ssp_clk@e6150248 {
477 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
478 reg = <0 0xe6150248 0 4>;
479 clocks = <&pll1_div2_clk>;
481 clock-output-names = "ssp";
483 ssprs_clk: ssprs_clk@e615024c {
484 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
485 reg = <0 0xe615024c 0 4>;
486 clocks = <&pll1_div2_clk>;
488 clock-output-names = "ssprs";
491 /* Fixed factor clocks */
492 pll1_div2_clk: pll1_div2_clk {
493 compatible = "fixed-factor-clock";
494 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
498 clock-output-names = "pll1_div2";
501 compatible = "fixed-factor-clock";
502 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
506 clock-output-names = "z2";
509 compatible = "fixed-factor-clock";
510 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
514 clock-output-names = "zg";
517 compatible = "fixed-factor-clock";
518 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
522 clock-output-names = "zx";
525 compatible = "fixed-factor-clock";
526 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
530 clock-output-names = "zs";
533 compatible = "fixed-factor-clock";
534 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
538 clock-output-names = "hp";
541 compatible = "fixed-factor-clock";
542 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
546 clock-output-names = "i";
549 compatible = "fixed-factor-clock";
550 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
554 clock-output-names = "b";
557 compatible = "fixed-factor-clock";
558 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
562 clock-output-names = "p";
565 compatible = "fixed-factor-clock";
566 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
570 clock-output-names = "cl";
573 compatible = "fixed-factor-clock";
574 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
578 clock-output-names = "m2";
581 compatible = "fixed-factor-clock";
582 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
586 clock-output-names = "imp";
589 compatible = "fixed-factor-clock";
590 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
592 clock-div = <(48 * 1024)>;
594 clock-output-names = "rclk";
596 oscclk_clk: oscclk_clk {
597 compatible = "fixed-factor-clock";
598 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
600 clock-div = <(12 * 1024)>;
602 clock-output-names = "oscclk";
605 compatible = "fixed-factor-clock";
606 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
610 clock-output-names = "zb3";
612 zb3d2_clk: zb3d2_clk {
613 compatible = "fixed-factor-clock";
614 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
618 clock-output-names = "zb3d2";
621 compatible = "fixed-factor-clock";
622 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
626 clock-output-names = "ddr";
629 compatible = "fixed-factor-clock";
630 clocks = <&pll1_div2_clk>;
634 clock-output-names = "mp";
637 compatible = "fixed-factor-clock";
638 clocks = <&extal_clk>;
642 clock-output-names = "cp";
646 mstp0_clks: mstp0_clks@e6150130 {
647 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
648 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
651 renesas,clock-indices = <R8A7790_CLK_MSIOF0>;
652 clock-output-names = "msiof0";
654 mstp1_clks: mstp1_clks@e6150134 {
655 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
656 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
657 clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
658 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
661 renesas,clock-indices = <
662 R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
663 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
664 R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_RT R8A7790_CLK_VSP1_SY
667 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
668 "vsp1-du0", "vsp1-rt", "vsp1-sy";
670 mstp2_clks: mstp2_clks@e6150138 {
671 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
672 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
673 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
674 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>;
676 renesas,clock-indices = <
677 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
678 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
679 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
682 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
683 "scifb1", "msiof1", "msiof3", "scifb2";
685 mstp3_clks: mstp3_clks@e615013c {
686 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
687 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
688 clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,
689 <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,
690 <&mmc0_clk>, <&rclk_clk>;
692 renesas,clock-indices = <
693 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
694 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
695 R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1
698 "tpu0", "mmcif1", "sdhi3", "sdhi2",
699 "sdhi1", "sdhi0", "mmcif0", "cmt1";
701 mstp5_clks: mstp5_clks@e6150144 {
702 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
703 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
704 clocks = <&extal_clk>, <&p_clk>;
706 renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
707 clock-output-names = "thermal", "pwm";
709 mstp7_clks: mstp7_clks@e615014c {
710 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
711 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
712 clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
713 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
716 renesas,clock-indices = <
717 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
718 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
719 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
720 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
723 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
724 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
726 mstp8_clks: mstp8_clks@e6150990 {
727 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
728 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
729 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>,
730 <&zs_clk>, <&zs_clk>;
732 renesas,clock-indices = <
733 R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1
734 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1
738 "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
740 mstp9_clks: mstp9_clks@e6150994 {
741 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
742 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
743 clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>,
744 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
746 renesas,clock-indices = <
747 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD
748 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1
752 "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0";