arch/arm/boot/dts/r8a7790.dtsi

   1 /*
   2  * Device Tree Source for the r8a7790 SoC
   3  *
   4  * Copyright (C) 2013 Renesas Solutions Corp.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/clock/r8a7790-clock.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/interrupt-controller/irq.h>
  14
  15 / {
  16         compatible = "renesas,r8a7790";
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 i2c0 = &i2c0;
  23                 i2c1 = &i2c1;
  24                 i2c2 = &i2c2;
  25                 i2c3 = &i2c3;
  26         };
  27
  28         cpus {
  29                 #address-cells = <1>;
  30                 #size-cells = <0>;
  31
  32                 cpu0: cpu@0 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a15";
  35                         reg = <0>;
  36                         clock-frequency = <1300000000>;
  37                 };
  38
  39                 cpu1: cpu@1 {
  40                         device_type = "cpu";
  41                         compatible = "arm,cortex-a15";
  42                         reg = <1>;
  43                         clock-frequency = <1300000000>;
  44                 };
  45
  46                 cpu2: cpu@2 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a15";
  49                         reg = <2>;
  50                         clock-frequency = <1300000000>;
  51                 };
  52
  53                 cpu3: cpu@3 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a15";
  56                         reg = <3>;
  57                         clock-frequency = <1300000000>;
  58                 };
  59
  60                 cpu4: cpu@4 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a7";
  63                         reg = <0x100>;
  64                         clock-frequency = <780000000>;
  65                 };
  66
  67                 cpu5: cpu@5 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a7";
  70                         reg = <0x101>;
  71                         clock-frequency = <780000000>;
  72                 };
  73
  74                 cpu6: cpu@6 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a7";
  77                         reg = <0x102>;
  78                         clock-frequency = <780000000>;
  79                 };
  80
  81                 cpu7: cpu@7 {
  82                         device_type = "cpu";
  83                         compatible = "arm,cortex-a7";
  84                         reg = <0x103>;
  85                         clock-frequency = <780000000>;
  86                 };
  87         };
  88
  89         gic: interrupt-controller@f1001000 {
  90                 compatible = "arm,cortex-a15-gic";
  91                 #interrupt-cells = <3>;
  92                 #address-cells = <0>;
  93                 interrupt-controller;
  94                 reg = <0 0xf1001000 0 0x1000>,
  95                         <0 0xf1002000 0 0x1000>,
  96                         <0 0xf1004000 0 0x2000>,
  97                         <0 0xf1006000 0 0x2000>;
  98                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  99         };
 100
 101         gpio0: gpio@e6050000 {
 102                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 103                 reg = <0 0xe6050000 0 0x50>;
 104                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
 105                 #gpio-cells = <2>;
 106                 gpio-controller;
 107                 gpio-ranges = <&pfc 0 0 32>;
 108                 #interrupt-cells = <2>;
 109                 interrupt-controller;
 110         };
 111
 112         gpio1: gpio@e6051000 {
 113                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 114                 reg = <0 0xe6051000 0 0x50>;
 115                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 116                 #gpio-cells = <2>;
 117                 gpio-controller;
 118                 gpio-ranges = <&pfc 0 32 32>;
 119                 #interrupt-cells = <2>;
 120                 interrupt-controller;
 121         };
 122
 123         gpio2: gpio@e6052000 {
 124                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 125                 reg = <0 0xe6052000 0 0x50>;
 126                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 127                 #gpio-cells = <2>;
 128                 gpio-controller;
 129                 gpio-ranges = <&pfc 0 64 32>;
 130                 #interrupt-cells = <2>;
 131                 interrupt-controller;
 132         };
 133
 134         gpio3: gpio@e6053000 {
 135                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 136                 reg = <0 0xe6053000 0 0x50>;
 137                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 138                 #gpio-cells = <2>;
 139                 gpio-controller;
 140                 gpio-ranges = <&pfc 0 96 32>;
 141                 #interrupt-cells = <2>;
 142                 interrupt-controller;
 143         };
 144
 145         gpio4: gpio@e6054000 {
 146                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 147                 reg = <0 0xe6054000 0 0x50>;
 148                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 149                 #gpio-cells = <2>;
 150                 gpio-controller;
 151                 gpio-ranges = <&pfc 0 128 32>;
 152                 #interrupt-cells = <2>;
 153                 interrupt-controller;
 154         };
 155
 156         gpio5: gpio@e6055000 {
 157                 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
 158                 reg = <0 0xe6055000 0 0x50>;
 159                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 160                 #gpio-cells = <2>;
 161                 gpio-controller;
 162                 gpio-ranges = <&pfc 0 160 32>;
 163                 #interrupt-cells = <2>;
 164                 interrupt-controller;
 165         };
 166
 167         thermal@e61f0000 {
 168                 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
 169                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 170                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 171                 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
 172         };
 173
 174         timer {
 175                 compatible = "arm,armv7-timer";
 176                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 177                              <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 178                              <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 179                              <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 180         };
 181
 182         irqc0: interrupt-controller@e61c0000 {
 183                 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
 184                 #interrupt-cells = <2>;
 185                 interrupt-controller;
 186                 reg = <0 0xe61c0000 0 0x200>;
 187                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 188                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 189                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 190                              <0 3 IRQ_TYPE_LEVEL_HIGH>;
 191         };
 192
 193         i2c0: i2c@e6508000 {
 194                 #address-cells = <1>;
 195                 #size-cells = <0>;
 196                 compatible = "renesas,i2c-r8a7790";
 197                 reg = <0 0xe6508000 0 0x40>;
 198                 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
 199                 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
 200                 status = "disabled";
 201         };
 202
 203         i2c1: i2c@e6518000 {
 204                 #address-cells = <1>;
 205                 #size-cells = <0>;
 206                 compatible = "renesas,i2c-r8a7790";
 207                 reg = <0 0xe6518000 0 0x40>;
 208                 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
 209                 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
 210                 status = "disabled";
 211         };
 212
 213         i2c2: i2c@e6530000 {
 214                 #address-cells = <1>;
 215                 #size-cells = <0>;
 216                 compatible = "renesas,i2c-r8a7790";
 217                 reg = <0 0xe6530000 0 0x40>;
 218                 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
 219                 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
 220                 status = "disabled";
 221         };
 222
 223         i2c3: i2c@e6540000 {
 224                 #address-cells = <1>;
 225                 #size-cells = <0>;
 226                 compatible = "renesas,i2c-r8a7790";
 227                 reg = <0 0xe6540000 0 0x40>;
 228                 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
 229                 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
 230                 status = "disabled";
 231         };
 232
 233         mmcif0: mmcif@ee200000 {
 234                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 235                 reg = <0 0xee200000 0 0x80>;
 236                 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
 237                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
 238                 reg-io-width = <4>;
 239                 status = "disabled";
 240         };
 241
 242         mmcif1: mmc@ee220000 {
 243                 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
 244                 reg = <0 0xee220000 0 0x80>;
 245                 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
 246                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
 247                 reg-io-width = <4>;
 248                 status = "disabled";
 249         };
 250
 251         pfc: pfc@e6060000 {
 252                 compatible = "renesas,pfc-r8a7790";
 253                 reg = <0 0xe6060000 0 0x250>;
 254         };
 255
 256         sdhi0: sd@ee100000 {
 257                 compatible = "renesas,sdhi-r8a7790";
 258                 reg = <0 0xee100000 0 0x200>;
 259                 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 260                 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
 261                 cap-sd-highspeed;
 262                 status = "disabled";
 263         };
 264
 265         sdhi1: sd@ee120000 {
 266                 compatible = "renesas,sdhi-r8a7790";
 267                 reg = <0 0xee120000 0 0x200>;
 268                 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
 269                 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
 270                 cap-sd-highspeed;
 271                 status = "disabled";
 272         };
 273
 274         sdhi2: sd@ee140000 {
 275                 compatible = "renesas,sdhi-r8a7790";
 276                 reg = <0 0xee140000 0 0x100>;
 277                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
 278                 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
 279                 cap-sd-highspeed;
 280                 status = "disabled";
 281         };
 282
 283         sdhi3: sd@ee160000 {
 284                 compatible = "renesas,sdhi-r8a7790";
 285                 reg = <0 0xee160000 0 0x100>;
 286                 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
 287                 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
 288                 cap-sd-highspeed;
 289                 status = "disabled";
 290         };
 291
 292         scifa0: serial@e6c40000 {
 293                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 294                 reg = <0 0xe6c40000 0 64>;
 295                 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
 296                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
 297                 clock-names = "sci_ick";
 298                 status = "disabled";
 299         };
 300
 301         scifa1: serial@e6c50000 {
 302                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 303                 reg = <0 0xe6c50000 0 64>;
 304                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
 305                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
 306                 clock-names = "sci_ick";
 307                 status = "disabled";
 308         };
 309
 310         scifa2: serial@e6c60000 {
 311                 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
 312                 reg = <0 0xe6c60000 0 64>;
 313                 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
 314                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
 315                 clock-names = "sci_ick";
 316                 status = "disabled";
 317         };
 318
 319         scifb0: serial@e6c20000 {
 320                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 321                 reg = <0 0xe6c20000 0 64>;
 322                 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 323                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
 324                 clock-names = "sci_ick";
 325                 status = "disabled";
 326         };
 327
 328         scifb1: serial@e6c30000 {
 329                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 330                 reg = <0 0xe6c30000 0 64>;
 331                 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 332                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
 333                 clock-names = "sci_ick";
 334                 status = "disabled";
 335         };
 336
 337         scifb2: serial@e6ce0000 {
 338                 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
 339                 reg = <0 0xe6ce0000 0 64>;
 340                 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
 341                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
 342                 clock-names = "sci_ick";
 343                 status = "disabled";
 344         };
 345
 346         scif0: serial@e6e60000 {
 347                 compatible = "renesas,scif-r8a7790", "renesas,scif";
 348                 reg = <0 0xe6e60000 0 64>;
 349                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 350                 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
 351                 clock-names = "sci_ick";
 352                 status = "disabled";
 353         };
 354
 355         scif1: serial@e6e68000 {
 356                 compatible = "renesas,scif-r8a7790", "renesas,scif";
 357                 reg = <0 0xe6e68000 0 64>;
 358                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 359                 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
 360                 clock-names = "sci_ick";
 361                 status = "disabled";
 362         };
 363
 364         hscif0: serial@e62c0000 {
 365                 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
 366                 reg = <0 0xe62c0000 0 96>;
 367                 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
 368                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
 369                 clock-names = "sci_ick";
 370                 status = "disabled";
 371         };
 372
 373         hscif1: serial@e62c8000 {
 374                 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
 375                 reg = <0 0xe62c8000 0 96>;
 376                 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
 377                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
 378                 clock-names = "sci_ick";
 379                 status = "disabled";
 380         };
 381
 382         sata0: sata@ee300000 {
 383                 compatible = "renesas,sata-r8a7790";
 384                 reg = <0 0xee300000 0 0x2000>;
 385                 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 386                 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
 387                 status = "disabled";
 388         };
 389
 390         sata1: sata@ee500000 {
 391                 compatible = "renesas,sata-r8a7790";
 392                 reg = <0 0xee500000 0 0x2000>;
 393                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 394                 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
 395                 status = "disabled";
 396         };
 397
 398         clocks {
 399                 #address-cells = <2>;
 400                 #size-cells = <2>;
 401                 ranges;
 402
 403                 /* External root clock */
 404                 extal_clk: extal_clk {
 405                         compatible = "fixed-clock";
 406                         #clock-cells = <0>;
 407                         /* This value must be overriden by the board. */
 408                         clock-frequency = <0>;
 409                         clock-output-names = "extal";
 410                 };
 411
 412                 /*
 413                  * The external audio clocks are configured as 0 Hz fixed frequency clocks by
 414                  * default. Boards that provide audio clocks should override them.
 415                  */
 416                 audio_clk_a: audio_clk_a {
 417                         compatible = "fixed-clock";
 418                         #clock-cells = <0>;
 419                         clock-frequency = <0>;
 420                         clock-output-names = "audio_clk_a";
 421                 };
 422                 audio_clk_b: audio_clk_b {
 423                         compatible = "fixed-clock";
 424                         #clock-cells = <0>;
 425                         clock-frequency = <0>;
 426                         clock-output-names = "audio_clk_b";
 427                 };
 428                 audio_clk_c: audio_clk_c {
 429                         compatible = "fixed-clock";
 430                         #clock-cells = <0>;
 431                         clock-frequency = <0>;
 432                         clock-output-names = "audio_clk_c";
 433                 };
 434
 435                 /* Special CPG clocks */
 436                 cpg_clocks: cpg_clocks@e6150000 {
 437                         compatible = "renesas,r8a7790-cpg-clocks",
 438                                      "renesas,rcar-gen2-cpg-clocks";
 439                         reg = <0 0xe6150000 0 0x1000>;
 440                         clocks = <&extal_clk>;
 441                         #clock-cells = <1>;
 442                         clock-output-names = "main", "pll0", "pll1", "pll3",
 443                                              "lb", "qspi", "sdh", "sd0", "sd1",
 444                                              "z";
 445                 };
 446
 447                 /* Variable factor clocks */
 448                 sd2_clk: sd2_clk@e6150078 {
 449                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 450                         reg = <0 0xe6150078 0 4>;
 451                         clocks = <&pll1_div2_clk>;
 452                         #clock-cells = <0>;
 453                         clock-output-names = "sd2";
 454                 };
 455                 sd3_clk: sd3_clk@e615007c {
 456                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 457                         reg = <0 0xe615007c 0 4>;
 458                         clocks = <&pll1_div2_clk>;
 459                         #clock-cells = <0>;
 460                         clock-output-names = "sd3";
 461                 };
 462                 mmc0_clk: mmc0_clk@e6150240 {
 463                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 464                         reg = <0 0xe6150240 0 4>;
 465                         clocks = <&pll1_div2_clk>;
 466                         #clock-cells = <0>;
 467                         clock-output-names = "mmc0";
 468                 };
 469                 mmc1_clk: mmc1_clk@e6150244 {
 470                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 471                         reg = <0 0xe6150244 0 4>;
 472                         clocks = <&pll1_div2_clk>;
 473                         #clock-cells = <0>;
 474                         clock-output-names = "mmc1";
 475                 };
 476                 ssp_clk: ssp_clk@e6150248 {
 477                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 478                         reg = <0 0xe6150248 0 4>;
 479                         clocks = <&pll1_div2_clk>;
 480                         #clock-cells = <0>;
 481                         clock-output-names = "ssp";
 482                 };
 483                 ssprs_clk: ssprs_clk@e615024c {
 484                         compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
 485                         reg = <0 0xe615024c 0 4>;
 486                         clocks = <&pll1_div2_clk>;
 487                         #clock-cells = <0>;
 488                         clock-output-names = "ssprs";
 489                 };
 490
 491                 /* Fixed factor clocks */
 492                 pll1_div2_clk: pll1_div2_clk {
 493                         compatible = "fixed-factor-clock";
 494                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 495                         #clock-cells = <0>;
 496                         clock-div = <2>;
 497                         clock-mult = <1>;
 498                         clock-output-names = "pll1_div2";
 499                 };
 500                 z2_clk: z2_clk {
 501                         compatible = "fixed-factor-clock";
 502                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 503                         #clock-cells = <0>;
 504                         clock-div = <2>;
 505                         clock-mult = <1>;
 506                         clock-output-names = "z2";
 507                 };
 508                 zg_clk: zg_clk {
 509                         compatible = "fixed-factor-clock";
 510                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 511                         #clock-cells = <0>;
 512                         clock-div = <3>;
 513                         clock-mult = <1>;
 514                         clock-output-names = "zg";
 515                 };
 516                 zx_clk: zx_clk {
 517                         compatible = "fixed-factor-clock";
 518                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 519                         #clock-cells = <0>;
 520                         clock-div = <3>;
 521                         clock-mult = <1>;
 522                         clock-output-names = "zx";
 523                 };
 524                 zs_clk: zs_clk {
 525                         compatible = "fixed-factor-clock";
 526                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 527                         #clock-cells = <0>;
 528                         clock-div = <6>;
 529                         clock-mult = <1>;
 530                         clock-output-names = "zs";
 531                 };
 532                 hp_clk: hp_clk {
 533                         compatible = "fixed-factor-clock";
 534                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 535                         #clock-cells = <0>;
 536                         clock-div = <12>;
 537                         clock-mult = <1>;
 538                         clock-output-names = "hp";
 539                 };
 540                 i_clk: i_clk {
 541                         compatible = "fixed-factor-clock";
 542                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 543                         #clock-cells = <0>;
 544                         clock-div = <2>;
 545                         clock-mult = <1>;
 546                         clock-output-names = "i";
 547                 };
 548                 b_clk: b_clk {
 549                         compatible = "fixed-factor-clock";
 550                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 551                         #clock-cells = <0>;
 552                         clock-div = <12>;
 553                         clock-mult = <1>;
 554                         clock-output-names = "b";
 555                 };
 556                 p_clk: p_clk {
 557                         compatible = "fixed-factor-clock";
 558                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 559                         #clock-cells = <0>;
 560                         clock-div = <24>;
 561                         clock-mult = <1>;
 562                         clock-output-names = "p";
 563                 };
 564                 cl_clk: cl_clk {
 565                         compatible = "fixed-factor-clock";
 566                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 567                         #clock-cells = <0>;
 568                         clock-div = <48>;
 569                         clock-mult = <1>;
 570                         clock-output-names = "cl";
 571                 };
 572                 m2_clk: m2_clk {
 573                         compatible = "fixed-factor-clock";
 574                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 575                         #clock-cells = <0>;
 576                         clock-div = <8>;
 577                         clock-mult = <1>;
 578                         clock-output-names = "m2";
 579                 };
 580                 imp_clk: imp_clk {
 581                         compatible = "fixed-factor-clock";
 582                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 583                         #clock-cells = <0>;
 584                         clock-div = <4>;
 585                         clock-mult = <1>;
 586                         clock-output-names = "imp";
 587                 };
 588                 rclk_clk: rclk_clk {
 589                         compatible = "fixed-factor-clock";
 590                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 591                         #clock-cells = <0>;
 592                         clock-div = <(48 * 1024)>;
 593                         clock-mult = <1>;
 594                         clock-output-names = "rclk";
 595                 };
 596                 oscclk_clk: oscclk_clk {
 597                         compatible = "fixed-factor-clock";
 598                         clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
 599                         #clock-cells = <0>;
 600                         clock-div = <(12 * 1024)>;
 601                         clock-mult = <1>;
 602                         clock-output-names = "oscclk";
 603                 };
 604                 zb3_clk: zb3_clk {
 605                         compatible = "fixed-factor-clock";
 606                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 607                         #clock-cells = <0>;
 608                         clock-div = <4>;
 609                         clock-mult = <1>;
 610                         clock-output-names = "zb3";
 611                 };
 612                 zb3d2_clk: zb3d2_clk {
 613                         compatible = "fixed-factor-clock";
 614                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 615                         #clock-cells = <0>;
 616                         clock-div = <8>;
 617                         clock-mult = <1>;
 618                         clock-output-names = "zb3d2";
 619                 };
 620                 ddr_clk: ddr_clk {
 621                         compatible = "fixed-factor-clock";
 622                         clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
 623                         #clock-cells = <0>;
 624                         clock-div = <8>;
 625                         clock-mult = <1>;
 626                         clock-output-names = "ddr";
 627                 };
 628                 mp_clk: mp_clk {
 629                         compatible = "fixed-factor-clock";
 630                         clocks = <&pll1_div2_clk>;
 631                         #clock-cells = <0>;
 632                         clock-div = <15>;
 633                         clock-mult = <1>;
 634                         clock-output-names = "mp";
 635                 };
 636                 cp_clk: cp_clk {
 637                         compatible = "fixed-factor-clock";
 638                         clocks = <&extal_clk>;
 639                         #clock-cells = <0>;
 640                         clock-div = <2>;
 641                         clock-mult = <1>;
 642                         clock-output-names = "cp";
 643                 };
 644
 645                 /* Gate clocks */
 646                 mstp0_clks: mstp0_clks@e6150130 {
 647                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 648                         reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
 649                         clocks = <&mp_clk>;
 650                         #clock-cells = <1>;
 651                         renesas,clock-indices = <R8A7790_CLK_MSIOF0>;
 652                         clock-output-names = "msiof0";
 653                 };
 654                 mstp1_clks: mstp1_clks@e6150134 {
 655                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 656                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 657                         clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
 658                                  <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
 659                                  <&zs_clk>;
 660                         #clock-cells = <1>;
 661                         renesas,clock-indices = <
 662                                 R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
 663                                 R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
 664                                 R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_RT R8A7790_CLK_VSP1_SY
 665                         >;
 666                         clock-output-names =
 667                                 "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
 668                                 "vsp1-du0", "vsp1-rt", "vsp1-sy";
 669                 };
 670                 mstp2_clks: mstp2_clks@e6150138 {
 671                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 672                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 673                         clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
 674                                  <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>;
 675                         #clock-cells = <1>;
 676                         renesas,clock-indices = <
 677                                 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
 678                                 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
 679                                 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
 680                         >;
 681                         clock-output-names =
 682                                 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
 683                                 "scifb1", "msiof1", "msiof3", "scifb2";
 684                 };
 685                 mstp3_clks: mstp3_clks@e615013c {
 686                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 687                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 688                         clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,
 689                                  <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,
 690                                  <&mmc0_clk>, <&rclk_clk>;
 691                         #clock-cells = <1>;
 692                         renesas,clock-indices = <
 693                                 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
 694                                 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
 695                                 R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1
 696                         >;
 697                         clock-output-names =
 698                                 "tpu0", "mmcif1", "sdhi3", "sdhi2",
 699                                 "sdhi1", "sdhi0", "mmcif0", "cmt1";
 700                 };
 701                 mstp5_clks: mstp5_clks@e6150144 {
 702                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 703                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
 704                         clocks = <&extal_clk>, <&p_clk>;
 705                         #clock-cells = <1>;
 706                         renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
 707                         clock-output-names = "thermal", "pwm";
 708                 };
 709                 mstp7_clks: mstp7_clks@e615014c {
 710                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 711                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 712                         clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
 713                                  <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
 714                                  <&zx_clk>;
 715                         #clock-cells = <1>;
 716                         renesas,clock-indices = <
 717                                 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
 718                                 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
 719                                 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
 720                                 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
 721                         >;
 722                         clock-output-names =
 723                                 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
 724                                 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
 725                 };
 726                 mstp8_clks: mstp8_clks@e6150990 {
 727                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 728                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 729                         clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>,
 730                                  <&zs_clk>, <&zs_clk>;
 731                         #clock-cells = <1>;
 732                         renesas,clock-indices = <
 733                                 R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1
 734                                 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1
 735                                 R8A7790_CLK_SATA0
 736                         >;
 737                         clock-output-names =
 738                                 "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
 739                 };
 740                 mstp9_clks: mstp9_clks@e6150994 {
 741                         compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
 742                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 743                         clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>,
 744                                  <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
 745                         #clock-cells = <1>;
 746                         renesas,clock-indices = <
 747                                 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD
 748                                 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1
 749                                 R8A7790_CLK_I2C0
 750                         >;
 751                         clock-output-names =
 752                                 "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0";
 753                 };
 754         };
 755
 756         spi: spi@e6b10000 {
 757                 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
 758                 reg = <0 0xe6b10000 0 0x2c>;
 759                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
 760                 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
 761                 num-cs = <1>;
 762                 #address-cells = <1>;
 763                 #size-cells = <0>;
 764                 status = "disabled";
 765         };
 766 };